阅读说明：本技术 阵列基板及液晶显示面板 (Array substrate and liquid crystal display panel ) 是由 王洋 冯博 魏旃 王世君 穆文凯 刘屹 田丽 于 2020-02-28 设计创作，主要内容包括：一种阵列基板及液晶显示面板,由于像素晶体管(02)中还包括与扫描线(G1)连接的补偿栅极(024)以及与第一电极(021)连接的补偿电极(025)；补偿电极(025)与第一电极电极(021)沿扫描线(G1)的延伸方向并排设置；补偿栅极(024)与栅极(023)沿扫描线(G1)的延伸方向并排且间隔设置；补偿栅极(024)与补偿电极(025)位于栅极(023)同一侧。在制备阵列基板时,当栅极(023)在沿扫描线(G1)方向发生对位误差时,虽然栅极(023)与第一电极(021)和第二电极(022)的重叠面积变小,但是由于对位偏移使补偿栅极(023)与补偿电极(025)重叠,从而利用补偿栅极(024)与补偿电极(025)的重叠面积来补偿因对位偏移而导致的栅极(023)与第一电极(021)和第二电极(022)的重叠面积的变小,从而稳定像素晶体管(02)的性能。(An array substrate and a liquid crystal display panel, wherein the pixel transistor (02) further comprises a compensation gate (024) connected with a scanning line (G1) and a compensation electrode (025) connected with a first electrode (021); the compensation electrode (025) and the first electrode (021) are arranged side by side along the extending direction of the scanning line (G1); the compensating grid electrode (024) and the grid electrode (023) are arranged side by side and at intervals along the extending direction of the scanning line (G1); the compensation gate (024) is located on the same side of the gate (023) as the compensation electrode (025). When an alignment error occurs in the gate electrode (023) along the scanning line (G1) during the preparation of the array substrate, although the overlapping area of the gate electrode (023) and the first electrode (021) and the second electrode (022) is reduced, the compensation gate electrode (023) and the compensation electrode (025) are overlapped due to the alignment offset, so that the overlapping area of the gate electrode (023) and the first electrode (021) and the second electrode (022) caused by the alignment offset is compensated by the overlapping area of the compensation gate electrode (024) and the compensation electrode (025), and the performance of the pixel transistor (02) is stabilized.)