阅读说明：本技术 具有完全扫描覆盖的基于三态和通过栅极的电路 (Tri-state and pass gate based circuit with full scan overlay ) 是由 伊什瓦尔·拉古拉曼 萨蒂什·瑟拉曼 爱德华·布莱西 于 2020-04-06 设计创作，主要内容包括：描述了具有完全扫描覆盖能力的基于三态和通过栅极的复用器电路结构。所述电路在其输出端处提供确定性状态,从而避免硅的高阻抗(Z)逻辑状态。这是利用上拉晶体管、下拉晶体管或通过多级组合逻辑来实现的,该组合逻辑组合馈送至上拉或下拉晶体管的复用器选择信号/使能信号。(A tri-state and pass gate based multiplexer circuit architecture with full scan overlay capability is described. The circuit provides a deterministic state at its output, avoiding the high impedance (Z) logic state of silicon. This is accomplished using pull-up transistors, pull-down transistors, or through multi-stage combinational logic that combines multiplexer select/enable signals fed to either pull-up or pull-down transistors.)

1. An apparatus, comprising:

a first pass gate controllable by a first signal and a second signal, wherein the second signal is a complement of the first signal;

a second pass gate controllable by a third signal and a fourth signal, wherein the fourth signal is a complement of the third signal;

a third pass gate controllable by a fifth signal and a sixth signal, wherein the sixth signal is a complement of the fifth signal, wherein the first, second, and third pass gates are coupled to a node; and

a network of devices coupled to the node, wherein the network of devices is controllable by at least three of the first, second, third, fourth, fifth, or sixth signals.

2. The apparatus of claim 1, wherein the network of devices comprises a pull-down network coupled to the node and ground.

3. The apparatus of claim 2, wherein the pull-down network comprises at least three transistors coupled in series between the node and the ground.

4. The apparatus of claim 3, wherein the three transistors are n-type transistors.

5. The apparatus of claim 1, wherein the network of devices comprises a pull-up network coupled to the node and a power supply node.

6. The apparatus of claim 5, wherein the pull-up network comprises at least three transistors coupled in series between the node and the power supply node.

7. The apparatus of claim 6, wherein the three transistors are p-type transistors.

8. The apparatus of claim 1, wherein the network of devices comprises:

a transistor coupled to the node and ground; and

a combinational logic gate coupled to the gate of the transistor.

9. The apparatus of claim 1, wherein the network of devices comprises:

a first transistor coupled to the node;

a second transistor coupled in series with the first transistor; and

a combinational logic gate coupled to a gate of the first transistor or the second transistor.

10. The apparatus of any of claims 1 to 9, comprising:

a first inverter coupled to the first pass gate, wherein the first inverter is to be driven by a first input signal;

a second inverter coupled to the second pass gate, wherein the second inverter is to be driven by a second input signal;

a third inverter coupled to the third pass gate, wherein the third inverter is to be driven by a third input signal; and

a fourth inverter coupled to the third pass gate, wherein the fourth inverter is to be driven by a fourth input signal.

11. An apparatus, comprising:

a first tristatable buffer or inverter controllable by a first signal and a second signal, wherein the second signal is complementary to the first signal;

a second tristatable buffer or inverter controllable by a third signal and a fourth signal, wherein said fourth signal is the complement of said third signal;

a third tri-stable buffer or inverter controllable by a fifth signal and a sixth signal, wherein the sixth signal is a complement of the fifth signal, wherein the first, second and third tri-stable buffers or inverters are coupled to a node; and

a network of devices coupled to the node, wherein the network of devices is controllable by at least three of the first, second, third, fourth, fifth, or sixth signals.

12. The apparatus of claim 11, wherein the network of devices comprises a pull-down network coupled to the node and ground.

13. The apparatus of claim 12, wherein the pull-down network comprises at least three transistors coupled in series between the node and the ground.

14. The apparatus of claim 13, wherein the three transistors are n-type transistors.

15. The apparatus of claim 11, wherein the network of devices comprises a pull-up network coupled to the node and a power supply node.

16. The apparatus of claim 15, wherein the pull-up network comprises at least three transistors coupled in series between the node and the power supply node.

17. The apparatus of claim 16, wherein the three transistors are p-type transistors.

18. The apparatus of any of claims 11 to 17, wherein the network of devices comprises:

a transistor coupled to the node and ground; and

a combinational logic gate coupled to the gate of the transistor.

19. The apparatus of any of claims 11 to 17, wherein the network of devices comprises:

a first transistor coupled to the node;

a second transistor coupled in series with the first transistor; and

a combinational logic gate coupled to a gate of the second transistor.

20. A system, comprising:

a memory; and

a processor coupled to the memory, wherein the processor comprises a multiplexer comprising the apparatus of any one of claims 1 to 10; and

a wireless interface communicatively coupled to the processor.

21. A system, comprising:

a memory; and

a processor coupled to the memory, wherein the processor comprises a multiplexer comprising the apparatus of any of claims 11 to 19; and

a wireless interface communicatively coupled to the processor.

22. A method, comprising:

controlling a first pass gate by a first signal and a second signal, wherein the second signal is a complement of the first signal;

controlling a second pass gate by a third signal and a fourth signal, wherein the fourth signal is a complement of the third signal;

controlling a third pass gate by a fifth signal and a sixth signal, wherein the sixth signal is a complement of the fifth signal, wherein the first, second, and third pass gates are coupled to a node; and

controlling, by at least three of the first, second, third, fourth, fifth, or sixth signals, a network of devices coupled to the node.

23. The method of claim 22, wherein the network of devices comprises a pull-down network coupled to the node and ground.

24. The method of claim 23, wherein the pull-down network comprises at least three transistors coupled in series between a node and the ground.

25. The method of claim 24, wherein the three transistors are n-type transistors.

Background

Pass-gate multiplexers are widely used in high-speed processors. Undetected faults on pins (or nodes) of certain circuits may cause computational errors. Faults at select pins (or nodes) of such circuits can cause high impedance (Z) output states that cannot be detected with a tester. Undetected faults on pins (or nodes) of such circuits may prevent us from distinguishing good chips from faulty chips. It may be desirable to detect all faults in a circuit to meet ultra-low parts per million defect rates (DPM), for example, typically less than 50 for automotive industry circuits. Due to the large scale use of pass gate multiplexers in high speed circuits, the loss of coverage caused by these undetected faults is large and must be addressed to meet ultra-low parts per million defect rate (DPM) standards.

Drawings

Embodiments of the present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure; however, the detailed description and drawings should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

Fig. 1A to 1B show circuits showing a high impedance output state caused by logic fixed to 0 or 1.

Fig. 2A-2B illustrate a 4:1 multiplexer and associated timing diagram, respectively.

FIG. 3 illustrates a 4:1 multiplexer circuit, according to some embodiments.

Fig. 4A-4B illustrate timing diagrams of the circuit of fig. 3 shown as a 0-fixed overlay and a 1-fixed overlay, respectively, according to some embodiments.

Fig. 5A-5C illustrate a pass gate multiplexer according to some embodiments.

Figure 6 illustrates a non-decoding pass gate based multiplexer with extra diffusion capacitance according to some embodiments.

Fig. 7A-7B show graphs illustrating delay effects across pins and delay effects versus multiplexer drive strength.

Fig. 8 shows a graph showing noise sources at the selection input and the response at the output.

Fig. 9 illustrates a smart device or computer system or SoC (system on a chip) having tri-gate and pass-gate based circuits with full scan coverage, according to some embodiments of the present disclosure.

Detailed Description

Some embodiments describe novel tri-state or pass-gate based multiplexer circuit architectures (or a combination of both) with full scan overlay capability. The circuit provides deterministic states at its output to avoid high impedance (Z) logic states of silicon. The circuit may be implemented using pull-up transistors, pull-down transistors, or using multi-stage combinational logic that combines multiplexer select signals (select) and/or enable signals (enable) fed to the pull-up or pull-down circuits.

The embodiments described herein provide the ability to significantly improve or improve test coverage on processors and other high-speed Intellectual Property (IP) blocks, which are common in today's system-on-a-chip (SoC) assemblies. Such test coverage enhancement is valuable because it improves customer-oriented factory product quality by promoting defect screening capabilities in manufacturing. This capability is crucial for new generations of processes of different maturity. Embodiments also provide improved on-site hardware diagnostic coverage, and thus improved functional safety (FuSa) capabilities. Other technical effects will be apparent from the various figures and embodiments.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form (rather than in detail) in order to avoid obscuring embodiments of the present disclosure.

It is noted that in the corresponding figures of the embodiments, signals are represented by lines. Some lines may be thicker, to indicate more constituent signal paths; and/or may have arrows at one or more ends to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, these lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic cell. Any represented signal (as indicated by design requirements or preferences) may actually comprise one or more signals that may travel in either direction and may be implemented in any suitable type of signal scheme.

Throughout the specification, and in the claims, the term "connected" means directly connected, such as electrically, mechanically or magnetically, between the things that are connected, without any intervening device.

The term "coupled" means directly or indirectly connected, such as through a direct electrical, mechanical, or magnetic connection between the things that are connected, or indirectly connected through one or more passive or active intermediary devices.

The term "adjacent" herein generally refers to a location of something that is adjacent (e.g., immediately adjacent, or near-by-one or more things between them) or that is adjacent (e.g., abuts) another thing.

The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with one another to provide a desired function.

The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a", "an" and "the" includes plural references. The meaning of "in … …" includes "in … …" and "on … …".

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another, and may subsequently reduce the layout area. In some cases, scaling also refers to expanding a design from one process technology to another, and may subsequently increase layout area. The term "scaling" also generally refers to shrinking or enlarging layouts and devices within the same technology node. The term "scaling" may also refer to an adjustment (e.g., slowing down or speeding up-i.e., zooming in or out, respectively) of a signal frequency relative to another parameter (e.g., a power supply level). The terms "substantially," "near," "about," "near," and "about" generally refer to within +/-10% of a target value.

Unless otherwise specified, the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

For the purposes of this disclosure, the phrases "a and/or B" and "a or B" mean (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" means (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).

The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

It is pointed out that those elements of the drawings having the same reference numbers (or names) as the elements of any other drawing can operate or function in any manner similar to that described, but are not limited to such.

For purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are Metal Oxide Semiconductor (MOS) transistors or derivatives thereof, where MOS transistors include drain, source, gate, and body terminals. Transistors and/or MOS transistor derivatives also include tri-gate and FinFET transistors, gate-around cylindrical transistors, tunneling fet (tfet), square wire, or rectangular ribbon transistors, ferroelectric fet (fefet), or other devices that perform a transistor function, such as carbon nanotubes or spintronic devices. MOSFET symmetric source and drain terminals are equivalent terminals and are used interchangeably herein. TFET devices, on the other hand, have asymmetric source and drain terminals. Those skilled in the art will appreciate that other transistors (e.g., bipolar junction transistors (BJTs PNP/NPN), BiCMOS, CMOS, etc.) may be used without departing from the scope of the present disclosure.

Fig. 1A-1B illustrate circuits 100 and 120, respectively, which illustrate high impedance output states resulting from an enable signal fixed at 0 or 1. The circuit 100 (and circuit 120) is shown with two tri-state drivers T1 and T2 (or multiplexers T1 and T2) controlled by select or enable signals en1 and en2, respectively. The input to driver T1 is d1, and the input to driver T2 is d 2. The outputs of the two drivers T1 and T2 are combined into a single output node.

The problem arises with pass gate and tri-state multiplexing circuits (T1 and/or T2), when there is a defect that causes a stuck-at 0 fault (fig. 1A) or a stuck-at 1 fault (fig. 1B), the output of the cell resolves to a Z (high impedance) or contention state. These two states are unknown values and are not available for detecting faults. For a logic fault to be robustly detected, for example, by result testing with a Scan ATPG (automatic test pattern generation) tool, the output of a cell under test conditions must resolve to a deterministic 1 or 0 in the presence of a defect. The non-deterministic state at the output results in a loss of fault coverage across the logic cone that drives the select signal. One solution is to resolve the Z-state using a p-type pull-up transistor at the output node, resulting in a distinguishable difference between the good machine value and the failed machine value. The gate G of the recovery p-type transistor is controlled so that Z resolves to 1 on the tri-state bus through the scan pattern. Another solution is to use an analog based approach to detect faults on the select lines, for example assuming the bus network will hold a particular value of the previous clock cycle instead of Z.

There are drawbacks to the p-type pull-up solution. For example, contention between functional mode testing and weak pull-up p-type transistors causes problems with the increase in scan power and the value of the output voltage due to the contention. This contention minimizes its design effectiveness for field scanning, where the design will be under scanning conditions for a considerable length of time. Contention results in undesirable short circuit power dissipation by the recovery p-type transistors during scan mode, which in turn leads to scan power increase, noise and reliability problems. This implementation, which results in contention, may also not be used during speed testing because cell delay increases significantly during scan testing due to contention between the pull-up and functional cells.

The simulation-based approach has the following disadvantages: the holding of the output bus value is not guaranteed. Leakage, noise, local process variations, and minor faults can all invalidate the assumptions of simulation and probability. Importantly, the fault effects are robustly resolved to discrete logical values and are thus considered detected.

Various embodiments describe circuits that provide deterministic states during reduced-coverage Hi-Z (high impedance) possible states. This is achieved using pull-up, pull-down, or using multi-stage combinational logic that combines the enable signals fed to the pull-up or pull-down circuits.

Fig. 2A-2B illustrate a 4:1 non-decoding Multiplexer (MUX)200 and associated timing diagram 220, respectively, that suffers from a loss of fault coverage. Multiplexer 200 includes input nodes a, b, c, and d; controlling nodes sa, sa _ b, sb _ b, sc _ b, sd and sd _ b by gates; inverter 201_1-4(also labeled inv 1-inv 4), and a Pass Gate (PG)202_1-4(also labeled PG 1-PG 4). Here, the labels of the nodes and the signals on those nodes may be used interchangeably. For example, node a carries signal a. In addition, the suffix "_ b" indicates inversion. For example, sa _ b is an inverted signal of sa.

Fig. 2A shows a non-decoding 4:1 Pass Gate (PG) based multiplexer that has the potential to test scenarios to show problems. When the select signal sb is 1, the output conforms to the input data b as indicated by the waveform 221. When the select signal sb is fixed at 0, the output of the MUX is uncontrolled and is floating due to the mutually exclusive (mutually exclusive) nature of the other select signals. The output "o" (which is assumed to be stable at "0") can potentially drift toward "1" due to leakage and noise, as shown by waveform 222. This non-deterministic state results in a loss of fault coverage across the logic cone of the select signal.

Fig. 3 illustrates a circuit (Mux)300 according to some embodiments. Fig. 3 shows the proposed circuit with fault coverage capability. The multiplexer 300 is similar to the Mux 200, but the additional pull-down network is controlled by the multiplexer's select signal to form a deterministic output "0" when none of the PGs control the output. The pull-down network in this example comprises n-type transistors MN1, MN2, MN3 and MN4 coupled in series, such that transistor MN1 is coupled to the output "O" and transistor MN4 is coupled to ground (Vss). The gate of the transistor MN1 is controlled by sa _ b, the gate of the transistor MN2 is controlled by sb _ b, the gate of the transistor MN3 is controlled by sc _ b, and the gate of the transistor MN4 is controlled by sd _ b. Although Mux 300 is shown as a 4:1Mux, various embodiments are applicable to any multiplexer size (e.g., 5:1Mux, 6:1Mux, etc.). The pull-down network satisfies the noise and leakage limits to provide a strong "0" at the output. Thus, full fault coverage capability is provided.

Fig. 4A-4B illustrate timing diagrams 400 and 420, respectively, of the circuit of fig. 3, the timing diagrams 400 and 420 illustrating a fix-to-0 overlay and a fix-to-1 overlay, respectively, according to some embodiments. Fig. 4A shows that when the selection signal sb is fixed to "0", the output "O" is in a deterministic state, so that the scan pattern can distinguish between a good machine (waveform 401) and a faulty machine (waveform 402). The circuit of fig. 3 can also be used to identify a fault stuck at a "1" by driving all select signals to 0, as shown in fig. 4B. In a good machine with the proposed circuit 300 (waveform 421), the output is in a "0" deterministic state independent of the input data b. In a faulty machine (waveform 422) with the select signal b fixed at 1, the output "O" will conform to the input data b to allow ATPG to distinguish between good and faulty machines. The circuitry of various embodiments provides 100% fault coverage.

Fig. 5A-5C illustrate pass gate multiplexers 500, 520, and 530, respectively, according to some embodiments. The circuits of fig. 5A-5C illustrate alternative implementations that utilize the same concepts as shown in fig. 3. These circuits are implemented using pull-up networks, pull-down networks, or by feeding the output of combinational logic that combines select signals to either a pull-up or a pull-down network. Selecting the correct configuration between options and sizing it as a design tradeoff between the bank stack limitations, input noise limitations for the MUX, timing effects on the data and select signals. The same technique can be used for tristate logic by adding pull-down/pull-up transistors controlled by tristate enable signals.

Fig. 5A is similar to fig. 3, but replaces the pull-down network with a pull-up network. In some embodiments, the pull-up network of mux 500 includes p-type transistors MP11, MP22, MP33, and MP44 coupled together in series, such that transistor MP11 is coupled to the output "O" and transistor MP44 is coupled to the power supply node (Vdd). The gate of transistor MP11 is controlled by sa, the gate of transistor MP22 is controlled by sb, the gate of transistor MP33 is controlled by sc, and the gate of transistor MP44 is controlled by sd. Although Mux 500 is shown as a 4:1Mux, various embodiments are applicable to any multiplexer size (e.g., 3:1Mux, 5:1Mux, 6:1Mux, etc.).

FIG. 5B is similar to FIG. 3, but with the pull-down network replaced with a pull-down network controlled by combinational logic. The pull-down network of fig. 5B includes n-type transistor MN1, n-type transistor MN2, and NOR gate 521. The gate of MN1 is controlled by sa, while the gate of transistor MN2 is controlled by the output of NOR gate 521. The inputs of NOR gate 521 are sb, sc, and sd. Although Mux 520 is shown as a 4:1Mux, various embodiments are applicable to any multiplexer size (e.g., 3:1Mux, 5:1Mux, 6:1Mux, etc.). With large multiplexers (e.g., more input signals), large NOR gates (e.g., with more inputs) may be utilized.

Fig. 5C is similar to fig. 5B, but with one transistor and combinatorial logic controlling the transistor replacing the pull-down network. In this example, the pull-down network of mux 530 includes an n-type transistor MN1 coupled to output node "O" and ground. The gate of transistor MN1 is controlled by a 4-input NOR gate 522 for a 4-input Mux. The inputs to NOR gate 522 are sa, sb, sc, and sd. Those skilled in the art will appreciate that the pull-up network may comprise p-type devices, and the polarity of the signal controlling the gates of these p-type devices may be appropriately adjusted to achieve the same function as all n-type transistors. To this end, the pull-down network may include p-type transistors instead of and/or in addition to the n-type transistors, and the signal polarity controlling the gates of those p-type devices may be appropriately adjusted to achieve the same function as all n-type transistors. In some embodiments, the combinational logic (such as NOR gates 521 and 522) may be replaced with other suitable logic (such as NAND gates) as well, and the polarity of the signals controlling the gates of those p-type devices may be adjusted appropriately to achieve the same function.

Optimally sizing the pull-down network minimizes the impact on the area, timing, and power of the functional circuit. Considering the case of driving the inverter and the Pass Gate (PG), the sizes of the INV1 and PG1 in fig. 3 are set to be 16 times (e.g., 16 Diffusion Grids (DG)) of the minimum allowable width of the transistor. The output load capacitance can potentially reach cmax of the library cell (the maximum capacitance that the library cell can drive). This would require sizing the pull down stack to at least the size of INV1 (e.g., larger for a stacked pull down configuration) to allow speed scan testing. This results in a significant area impact on each Multiplexer (MUX) that accumulates across the IP or SOC. This problem is compounded by the higher impact on functional timing arcs due to the increased output capacitance due to the diffusion of large pull-down networks.

To reduce the size of the pull-down network, the scan patterns are ordered such that the output node has been discharged by the pass gate (PG1) utilizing the inverter (INV 1). Thus, the pull-down network functions similarly to the keeper to meet noise and leakage limits. Thus, the pull-down/pull-up network can be sized to the minimum width allowed by the process technology. This technique minimizes the impact on the area, timing and power of the functional circuit.

The above automatic test event generation (ATPG) reordering enables the dimensions of the pull-down transistors to be set to the minimum allowed width of the process (1DG) technology. Thus, the area cost of adding a pull-down network may be limited. In one example, the area increase of the library cell level is 3 poly spacings for a 3:1 multiplexer and 5 poly spacings for a 4:1 multiplexer over the full drive strength of the mux.

The timing cost of the data pin in the circuit of some embodiments is due to the extra diffusion capacitance at the output of the pull-down transistor that needs to be charged/discharged through the drive inverter (example: INV 1). In the select pin, the timing cost is due to the gate capacitance of the pull-down transistor and the extra diffusion capacitance at the output pin.

Fig. 6 illustrates a non-decoding pass gate based multiplexer 600 with extra diffusion capacitance according to some embodiments. Mux 600 is the same as Mux 300, but has diffusion capacitances C1, C2, and C3. Cload represents the load capacitance on the output node "O". In the 4-input non-decoding MUX 600, the three n-type transistors in the pull-down stack are turned on at any point in time due to the mutually exclusive (mutually exclusive) nature of the select signals. The most severe case timing impact on the select and/or data pins in functional mode would be for the sd/d pin of the MUX. This is due to the fact that: when the select signal sd is selected, the other select signals sa, sb, and sc are "0", thereby exposing the diffusion capacitances of the top 3 pull-down transistors to the output. The next more severe impact pair will be sc/c, then sb/b and sa/a. This effect is minimized by reducing the size of the pull-down stack and the size of the extra capacitance.

Although the mux of the various embodiments with full scan coverage is shown as a pass-gate based mux, the pass-gate can be replaced with a tristatable device without changing the essence of the embodiments. The tristatable buffer may be enabled or disabled with the same signals used to control the pass gate.

Fig. 7A-7B show graphs 700 and 720, respectively, illustrating the delay impact across the pins and the delay impact versus multiplexer drive strength. Graph 700 shows the timing effect of delay increase for different arcs of 4:1mux for the minimum drive strength (2DG) available in the bank. The pull-down transistor is sized to a minimum size (1 DG). The delay impact is small for other subsequent pins, as discussed herein.

As the driving strength of the multiplexer increases, the delay impact caused by the extra pull-down network becomes negligible. Graph 720 shows the delay impact for different drive strengths/Diffusion Grids (DG) for select pin sd (waveform 721) and data pin d (waveform 722) or mux. The reference delay remains the same as the above setting. The delay effect decreases as the Mux drive strength increases due to the large inverter of the Mux driving the small diffusion capacitance of the pull-down network.

The power impact is limited by the extra capacitance introduced by the pull-down network. This effect is largely minimal due to the minimal size of the pull-down network.

Fig. 8 shows a graph 800, graph 800 showing noise sources at a select input and a response at an output. The pull-down stack is sized to the minimum size allowed by the technology node (1 DG). The circuit remains in keeper mode with the pull-down network remaining at "0" at the output. It was found that this circuit meets the required noise limit of 50% VDD even in the case of pessimistic noise input of 30% VDD on the select input (acting simultaneously) and data input configured to drive 1 on the output. Since the pull-down network is connected through the internal inverter, the inverter shields noise of the external selection signal to enable the output node to be restored to an original state. Graph 800 shows the noise source with respect to the select signal s, the suppressed noise with respect to s _ b, and the output node response to noise.

Fig. 9 illustrates a smart device, computer system, or SoC (system on a chip) having tri-gate and pass-gate based circuits with full scan coverage, according to some embodiments of the present disclosure. In some embodiments, computing device 2400 represents a mobile computing device, such as a computing tablet, mobile phone or smartphone, wireless-enabled e-reader, or other wireless mobile device. It should be understood that certain components are generally shown, and not all components of such a device are shown in computing device 2400. Any block herein may have tri-gate and pass gate based circuitry with full scan coverage.

In some embodiments, device 2400 represents a suitable computing device, such as a computing tablet, mobile or smart phone, laptop, desktop, internet of things (IOT) device, server, wearable device, set-top box, wireless-enabled e-reader, and so forth. It should be understood that certain components are generally shown, and not all components of such a device are shown in device 2400.

In an example, the apparatus 2400 includes a SoC (system on a chip) 2401. Example boundaries of SOC 2401 are shown in dashed lines in fig. 9, with some example components shown as being included within SOC 2401 — however, SOC 2401 may include any suitable components of device 2400.

In some embodiments, device 2400 includes a processor 2404. Processor 2404 may include one or more physical devices such as microprocessors, application processors, microcontrollers, programmable logic devices, processing cores, or other processing appliances. The processing operations performed by processor 2404 include the execution of an operating platform or operating system on which applications and/or device functions are executed. Processing operations include operations involving a human user or I/O (input/output) of other devices, operations involving power management, operations involving connecting computing device 2400 to another device, and so forth. The processing operations may also include operations related to audio I/O and/or display I/O.

In some embodiments, processor 2404 includes multiple processing cores (also referred to as cores) 2408a, 2408b, 2408 c. Although fig. 1 shows only three cores 2408a, 2408b, 2408c, processor 2404 may include any other suitable number of processing cores, such as tens or hundreds of processing cores. Processor cores 2408a, 2408b, 2408c may be implemented on a single Integrated Circuit (IC) chip. Further, a chip may include one or more shared and/or private caches, buses or interconnects, graphics and/or memory controllers, or other components.

In some embodiments, processor 2404 includes cache 2406. In an example, a section of the cache 2406 may be dedicated to an individual core 2408 (e.g., a first section of the cache 2406 is dedicated to core 2408a, a second section of the cache 2406 is dedicated to core 2408b, etc.). In an example, one or more sections of the cache 2406 may be shared between two or more of the cores 2408. The cache 2406 may be divided into different levels, such as a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, and so on.

In some embodiments, processor core 2404 may include a fetch unit to fetch instructions (including instructions with conditional branches) for execution by core 2404. Instructions may be fetched from any storage device, such as the memory 2430. Processor core 2404 may also include a decode unit to decode fetched instructions. For example, the decode unit may decode the fetched instruction into a plurality of micro-operations. Processor core 2404 may include a scheduling unit to perform various operations associated with storing decoded instructions. For example, the scheduling unit may hold data from the decode unit until the instruction is ready for dispatch, e.g., until all source values for the decoded instruction become available. In one embodiment, the dispatch unit may dispatch and/or issue (or dispatch) decoded instructions to the execution units for execution.

After an instruction is decoded (e.g., by a decode unit) and dispatched (e.g., by a dispatch unit), the execution unit may execute the dispatched instruction. In one embodiment, the execution unit may include more than one execution unit (e.g., imaging computation unit, graphics computation unit, general purpose computation unit, etc.). The execution units may also perform various arithmetic operations, such as addition, subtraction, multiplication, and/or division, and may include one or more Arithmetic Logic Units (ALUs). In an embodiment, a coprocessor (not shown) may perform various arithmetic operations in conjunction with the execution unit.

Additionally, the execution units may execute instructions out-of-order. Thus, in one embodiment, processor core 2404 may be an out-of-order processor core. Processor core 2404 may also include a retirement unit. After completion of the commit of the executed instructions, the retirement unit may retire the executed instructions. In one embodiment, retirement of an executed instruction may result in processor state committing to completion based on execution of the instruction, physical registers used by the instruction being deallocated, and so on. Processor core 2404 may also include a bus unit to support communication between components of processor core 2404 and other components via one or more buses. The processor core 2404 may also include one or more registers to store data accessed by various components of the core 2404 (such as values related to a specified application priority and/or subsystem state (mode) associations).

In some embodiments, device 2400 includes connectivity circuitry 2431. For example, connectivity circuitry 2431 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and/or software components (e.g., drivers, protocol stacks), e.g., to allow device 2400 to communicate with external devices. Device 2400 can be separate from external devices, such as other computing devices, wireless access points or base stations, and so forth.

In an example, the connectivity circuitry 2431 can include a plurality of different types of connectivity. In general terms, the connectivity circuitry 2431 may include cellular connectivity circuitry, wireless connectivity circuitry, and so forth. The cellular connectivity circuitry of connectivity circuitry 2431 generally refers to cellular network connectivity provided by a wireless operator, such as via: GSM (global system for mobile communications) or variants or derivatives, CDMA (code division multiple access) or variants or derivatives, TDM (time division multiplexing) or variants or derivatives, third generation partnership project (3GPP) Universal Mobile Telecommunications System (UMTS) or variants or derivatives, 3GPP Long Term Evolution (LTE) system or variants or derivatives, 3GPP LTE-advanced (LTE-a) system or variants or derivatives, fifth generation (5G) wireless system or variants or derivatives, 5G mobile network system or variants or derivatives, 5G New Radio (NR) system or variants or derivatives, or other cellular service standards. The wireless connection continuity circuit (or wireless interface) of the connectivity circuit 2431 refers to non-cellular wireless connectivity and may include a personal area network (such as bluetooth, near field, etc.), a local area network (such as Wi-Fi), and/or a wide area network (such as WiMax), and/or other wireless communications. In an example, the connectivity circuitry 2431 may include a network interface, such as a wired or wireless interface, for example, such that the system embodiments may be incorporated into a wireless device, such as a mobile phone or personal digital assistant.

In some embodiments, device 2400 includes a control hub 2432, control hub 2432 representing hardware devices and/or software components involved in interaction with one or more I/O devices. For example, processor 2404 may communicate with one or more of the following via control hub 2432: a display 2422, one or more peripheral devices 2424, a storage device 2428, one or more other external devices 2429, and the like. Control hub 2432 may be a chipset, a Platform Control Hub (PCH), or the like.

For example, control hub 2432 illustrates one or more connection points for additional devices connected to device 2400 through which a user may interact with the system, for example. For example, a device that is attachable to device 2400 (e.g., device 2429) includes a microphone device, a speaker or stereo system, an audio device, a video system or other display device, a keyboard or keypad device, or other I/O devices for use with particular applications, such as a card reader or other device.

As mentioned above, the control hub 2432 may interact with an audio device, a display 2422, and the like. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of device 2400. Further, audio output may be provided instead of or in addition to display output. In another example, if the display 2422 includes a touch screen, the display 2422 also serves as an input device that may be managed, at least in part, by the control hub 2432. Additional buttons or switches may also be present on computing device 2400 to provide I/O functions managed by control hub 2432. In one embodiment, control hub 2432 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in device 2400. The input may be part of direct user interaction, as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, camera applying a flash, or other features).

In some embodiments, control hub 2432 may be coupled to various devices using any suitable communication protocol, such as PCIe (peripheral component interconnect express), USB (universal serial bus), Thunderbolt, High Definition Multimedia Interface (HDMI), firewire, and the like.

In some embodiments, display 2422 represents hardware (e.g., a display device) and software (e.g., drivers) components that provide a visual and/or tactile display to a user for interacting with device 2400. The display 2422 may include a display interface, a display screen, and/or hardware devices for providing a display to a user. In some embodiments, the display 2422 comprises a touchscreen (or touchpad) device that provides both output and input to a user. In an example, the display 2422 can be in direct communication with the processor 2404. The display 2422 can be one or more of an internal display device, such as in a mobile electronic device, or a notebook device, or an external display device attached via a display interface (e.g., displayport, etc.). In one embodiment, display 2422 may be a Head Mounted Display (HMD), such as a stereoscopic display device for Virtual Reality (VR) applications or Augmented Reality (AR) applications.

In some embodiments, although not shown in the figures, in addition to (or instead of) processor 2404, device 2400 may include a Graphics Processing Unit (GPU) with one or more graphics processing cores that may control one or more aspects of the display content on display 2422.

Control hub 2432 (or platform controller hub) may include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections, for example, to peripheral devices 2424.

It should be understood that device 2400 may be a peripheral device to other computing devices, and may have a peripheral device connected thereto. Device 2400 may have a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device 2400. Further, a docking connector may allow device 2400 to connect to certain peripheral devices that allow computing device 2400 to control content output for, for example, audiovisual or other systems.

In addition to proprietary docking connectors or other proprietary connection hardware, device 2400 may make peripheral connections via common or standard-based connectors. Common types may include Universal Serial Bus (USB) connectors, which may include any of a variety of different hardware interfaces, including minidisplayport (mdp) display ports, High Definition Multimedia Interface (HDMI), firewire, or other types.

In some embodiments, in addition to or instead of being directly coupled to processor 2404, connectivity circuitry 2431 may also be coupled to control hub 2432, for example. In some embodiments, in addition to or instead of being directly coupled to processor 2404, for example, display 2422 may be coupled to control hub 2432.

In some embodiments, device 2400 includes memory 2430, memory 2430 coupled to processor 2404 via memory interface 2434. Memory 2430 comprises a storage device for storing information in device 2400. The memory may include non-volatile (state does not change if power to the memory device is interrupted) and/or volatile (state is undetermined if power to the memory device is interrupted) storage. The memory device 2430 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to be used as process memory. In one embodiment, memory 2430 is operable as system memory for device 2400 to store data and instructions for use by one or more processors 2404 in executing applications or processes. Memory 2430 can store application data, user data, music, photos, files, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of device 2400.

Elements of the various embodiments and examples are also provided as a machine-readable medium (e.g., memory 2430) for storing computer-executable instructions (e.g., instructions to implement any other process discussed herein). The machine-readable medium (e.g., memory 2430) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, Phase Change Memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

In some embodiments, device 2400 includes a temperature measurement circuit 2440, for example, to measure the temperature of various components of device 2400. In an example, the temperature measurement circuit 2440 can be embedded in or coupled to or attached to various components whose temperatures are to be measured and monitored. For example, the temperature measurement circuit 2440 may measure the temperature of (or within) one or more of: cores 2408a, 2408b, 2408c, a voltage regulator 2414, a memory 2430, a motherboard of SOC 2401, and/or any suitable component of device 2400.

In some embodiments, device 2400 includes a power measurement circuit 2442, e.g., for measuring power consumed by one or more components of device 2400. In an example, the power measurement circuit 2442 can measure voltage and/or current in addition to or instead of measuring power. In an example, the power management circuit 2442 can be embedded in or coupled to or attached to various components whose power, voltage, and/or current consumption is to be measured and monitored. For example, power measurement circuit 2442 may measure power, current, and/or voltage supplied by one or more voltage regulators 2414, power supplied to SOC 2401, power supplied to device 2400, power consumed by processor 2404 (or any other component) of device 2400, and so forth.

In some embodiments, device 2400 includes one or more voltage regulator circuits, commonly referred to as Voltage Regulators (VRs) 2414. VR 2414 generates signals at appropriate voltage levels that may be supplied to operate any appropriate components of device 2400. For example only, VR 2414 is shown supplying signals to processor 2404 of device 2400. In some embodiments, VR 2414 receives one or more Voltage Identification (VID) signals and generates a voltage signal at an appropriate level based on these VID signals. Various types of VR may be used for VR 2414. For example, VR 2414 may include a "buck" VR, a "boost" VR, a combination of buck and boost VRs, a Low Dropout (LDO) regulator, a switching DC-DC regulator, and so forth. Step-down VRs are commonly used in power transfer applications where an input voltage needs to be converted to an output voltage at a ratio that is less than a unit element. Boost VRs are commonly used in power transfer applications where an input voltage needs to be converted to an output voltage at a rate greater than a unit element. In some embodiments, each processor core has its own VR, which is controlled by PCU 2410a/b and/or PMIC 2412. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs may be digital, analog, or a combination of digital or analog LDOs.

In some embodiments, device 2400 includes one or more clock generator circuits, generally referred to as clock generators 2416. Clock generator 2416 generates a clock signal at an appropriate frequency level, which may be supplied to any appropriate components of device 2400. For example only, clock generator 2416 is shown as supplying a clock signal to processor 2404 of device 2400. In some embodiments, the clock generator 2416 receives one or more Frequency Identification (FID) signals and generates a clock signal at an appropriate frequency based on these FID signals.

In some embodiments, device 2400 includes a battery 2418, which battery 2418 supplies power to the various components of device 2400. For example only, a battery 2418 is shown supplying power to the processor 2404. Although not shown in the figures, device 2400 may include a charging circuit, for example, to recharge a battery based on AC power received from an Alternating Current (AC) adapter.

In some embodiments, device 2400 includes a Power Control Unit (PCU)2410 (also referred to as a Power Management Unit (PMU), power controller, etc.). In an example, portions of PCU 2410 may be implemented by one or more processing cores 2408, and these portions of PCU 2410 are symbolically shown with a dashed box and labeled PCU 2410 a. In an example, some other portions of PCU 2410 may be implemented outside of processing core 2408, and these portions of PCU 2410 are symbolically shown with a dashed box and labeled PCU 2410 b. PCU 2410 may perform various power management operations for device 2400. PCU 2410 may include hardware interfaces, hardware circuits, connectors, registers, and the like, as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for device 2400.

In some embodiments, the device2400 includes a Power Management Integrated Circuit (PMIC)2412, for example, to implement various power management operations of the device 2400. In some embodiments, PMIC2412 is a Reconfigurable Power Management IC (RPMIC) and/or IMVP (Moving voltage positioning). In an example, the PMIC is within a separate IC chip from the processor 2404. The PMIC may enable various power management operations of device 2400. PMIC2412 may include hardware interfaces, hardware circuits, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to enable various power management operations of device 2400.

In one example, the device 2400 includes one or two PCUs 2410 or PMICs 2412. In an example, either PCU 2410 or PMIC2412 may not be present in device 2400, and thus, these components are shown with dashed lines.

Various power management operations of device 2400 may be performed by PCU 2410, by PMIC2412, or by a combination of PCU 2410 and PMIC 2412. For example, PCU 2410 and/or PMIC2412 may select power states (e.g., P-states) of various components of device 2400. For example, PCU 2410 and/or PMIC2412 may select power states of various components of device 2400 (e.g., according to ACPI (advanced configuration and power interface) specifications). For example only, the PCU 2410 and/or the PMIC2412 may cause various components of the device 2400 to transition to a sleep state, an active state, an appropriate C-state (e.g., a C0 state or another appropriate C-state, according to ACPI specifications), and so on. In an example, the PCU 2410 and/or the PMIC2412 may control a voltage output by the VR 2414 and/or a frequency of a clock signal output by a clock generator, such as by outputting a VID signal and/or a FID signal, respectively. In an example, the PCU 2410 and/or PMIC2412 may control battery charge usage, charging of the battery 2418, and features related to power saving operations.

The clock generator 2416 may include a Phase Locked Loop (PLL), Frequency Locked Loop (FLL), or any suitable clock source. In some embodiments, each core of processor 2404 has its own clock source. Thus, each core may operate at a frequency that is independent of the operating frequencies of the other cores. In some embodiments, PCU 2410 and/or PMIC2412 perform adaptive or dynamic frequency scaling or adjustment. For example, if a processor core is not operating at its maximum power consumption threshold or limit, the clock frequency of the core may increase. In some embodiments, the PCU 2410 and/or PMIC2412 determines an operating condition of each core of the processor, and opportunistically adjusts the frequency and/or supply voltage of the core when the PCU 2410 and/or PMIC2412 determines that the core is operating below a target performance level, where the core clock source (e.g., the PLL of the core) has not lost lock. For example, if a core draws less current from a supply rail than the total current allocated for that core or processor 2404, the PCU 2410 and/or PMIC2412 may temporarily increase the power draw of that core or processor 2404 (e.g., by increasing the clock frequency and/or the supply voltage level) so that the core or processor 2404 may execute at a higher performance level. Thus, the voltage and/or frequency of processor 2404 may be temporarily increased without violating product reliability.

In an example, PCU 2410 and/or PMIC2412 may perform power management operations, such as based at least in part on measurements received from power management circuit 2442, temperature measurement circuit 2440, a charge level of battery 2418, and/or any other suitable information that may be used for power management. To this end, the PMIC2412 is communicatively coupled to one or more sensors to sense/detect various values/changes of one or more factors that have an impact on the power/thermal behavior of the system/platform. Examples of one or more factors include current, voltage drop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, and the like. One or more of these sensors may be provided in physical proximity to (and/or in thermal contact/coupling with) one or more components or logical/IP blocks of the computing system. Further, in at least one embodiment, the sensor(s) may be directly coupled to the PCU 2410 and/or PMIC2412 to allow the PCU 2410 and/or PMIC2412 to manage processor core energy based at least in part on values detected by one or more of these sensors.

An example software stack of device 2400 is also shown (although not all elements of the software stack are shown). By way of example only, the processor 2404 may execute an application 2450, an operating system 2452, one or more Power Management (PM) specific applications (e.g., commonly referred to as PM application 2458), and the like. The PM application 2458 may also be executed by the PCU 2410 and/or the PMIC 2412. The OS 2452 can also include one or more PM applications 2456a, 2456b, 2456 c. The OS 2452 can also include various drivers 2454a, 2454b, 2454c, etc., some of which can be dedicated for power management purposes. In some embodiments, device 2400 may also include a basic input/output system (BIOS) 2420. The BIOS 2420 can communicate with the OS 2452 (e.g., via one or more drivers 2454), with the processor 2404, and so on.

For example, one or more of PM applications 2458, 2456, drivers 2454, BIOS 2420, etc. may be used to implement power management specific tasks, such as to control the voltage and/or frequency of various components of device 2400, to control the awake states, sleep states, and/or any other suitable power states of various components of device 2400, to control battery power usage, charging of battery 2418, features related to power saving operation, and so forth.

Reference in the specification to "one embodiment," "an implementation," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may", "might", "could", or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claims refer to "a" or "an" element, that does not mean there is only one of the element. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment in any event that the particular features, structures, functions, or characteristics associated with the first and second embodiments are not mutually exclusive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations to such embodiments will be apparent to those skilled in the art in light of the foregoing description. The embodiments of the present disclosure are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims.

Further, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the presented figures to simplify illustration and discussion and thereby not obscure the disclosure. Additionally, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that: the details regarding the implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such details should be within the purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

Embodiments are described with reference to various examples. These examples may be combined with other examples in any suitable manner.

Example 1: an apparatus, comprising: a first pass gate controllable by a first signal and a second signal, wherein the second signal is a complement of the first signal; a second pass gate controllable by a third signal and a fourth signal, wherein the fourth signal is a complement of the third signal; a third pass gate controllable by a fifth signal and a sixth signal, wherein the sixth signal is a complement of the fifth signal, wherein the first, second, and third pass gates are coupled to a node; and a network of devices coupled to the node, wherein the network of devices is controllable by at least three of the first, second, third, fourth, fifth, or sixth signals.

Example 2: the apparatus of example 1, wherein the network of devices comprises a pull-down network coupled to the node and ground.

Example 3: the apparatus of example 2, wherein the pull-down network comprises at least three transistors coupled in series between the node and the ground.

Example 4: the apparatus of example 3, wherein the three transistors are n-type transistors.

Example 5: the apparatus of example 1, wherein the network of devices comprises a pull-up network coupled to the node and a power supply node.

Example 6: the apparatus of example 5, wherein the pull-up network includes at least three transistors coupled in series between the node and the power supply node.

Example 7: the apparatus of example 6, wherein the three transistors are p-type transistors.

Example 8: the apparatus of example 1, wherein the network of devices comprises: a transistor coupled to the node and ground; and a combinational logic gate coupled to the gate of the transistor.

Example 9: the apparatus of example 1, wherein the network of devices comprises: a first transistor coupled to the node; a second transistor coupled in series with the first transistor; and a combinational logic gate coupled to the gate of the first or second transistor.

Example 10: the apparatus of example 1, comprising: a first inverter coupled to the first pass gate, wherein the first inverter is to be driven by a first input signal; a second inverter coupled to the second pass gate, wherein the second inverter is to be driven by a second input signal; a third inverter coupled to the third pass gate, wherein the third inverter is to be driven by a third input signal; and a fourth inverter coupled to the third pass gate, wherein the fourth inverter is to be driven by a fourth input signal.

Example 11: an apparatus, comprising: a first tristatable buffer or inverter controllable by a first signal and a second signal, wherein the second signal is complementary to the first signal; a second tristatable buffer or inverter controllable by a third signal and a fourth signal, wherein said fourth signal is the complement of said third signal; a third tri-stable buffer or inverter controllable by a fifth signal and a sixth signal, wherein the sixth signal is a complement of the fifth signal, wherein the first, second and third tri-stable buffers or inverters are coupled to a node; and a network of devices coupled to the node, wherein the network of devices is controllable by at least three of the first, second, third, fourth, fifth, or sixth signals.

Example 12: the apparatus of example 11, wherein the network of devices comprises a pull-down network coupled to the node and ground.

Example 13: the apparatus of example 12, wherein the pull-down network comprises at least three transistors coupled in series between the node and the ground.

Example 14: the apparatus of example 13, wherein the three transistors are n-type transistors.

Example 15: the apparatus of example 11, wherein the network of devices comprises a pull-up network coupled to the node and a power supply node.

Example 16: the apparatus of example 15, wherein the pull-up network comprises at least three transistors coupled in series between the node and the power supply node.

Example 17: the apparatus of example 16, wherein the three transistors are p-type transistors.

Example 18: the apparatus of example 11, wherein the network of devices comprises: a transistor coupled to the node and ground; and a combinational logic gate coupled to the gate of the transistor.

Example 19: the apparatus of example 11, wherein the network of devices comprises: a first transistor coupled to the node; a second transistor coupled in series with the first transistor; and a combinational logic gate coupled to the gate of the second transistor.

Example 20: a system, comprising: a memory; and a processor coupled to the memory, wherein the processor comprises a multiplexer, the multiplexer comprising: a first pass gate controllable by a first signal and a second signal, wherein the second signal is a complement of the first signal; a second pass gate controllable by a third signal and a fourth signal, wherein the fourth signal is a complement of the third signal; a third pass gate controllable by a fifth signal and a sixth signal, wherein the sixth signal is a complement of the fifth signal, wherein the first, second, and third pass gates are coupled to a node; and a network of devices coupled to the node, wherein the network of devices is controllable by at least three of the first, second, third, fourth, fifth, or sixth signals.

Example 21: the system of example 20, wherein the network of devices comprises one of: a pull-down network coupled to the node and ground; or a pull-up network coupled to the node and a power supply node.

The abstract is provided to enable the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.