阅读说明：本技术 阵列基板及其制作方法、以及显示面板 (Array substrate, manufacturing method thereof and display panel ) 是由 易志根 于 2021-08-24 设计创作，主要内容包括：本发明实施例公开一种阵列基板及其制作方法、以及显示面板。在一具体实施方式中,该制作方法包括：在基板上形成公共电极和第一缓冲层；在第一缓冲层上形成金属氧化物层,并对金属氧化物层进行图案化形成第一金属氧化物子层和第二金属氧化物子层；在第一金属氧化物子层上形成栅极,栅极在基板上的正投影部分覆盖第一金属氧化物子层在基板上的正投影；对第一金属氧化物子层和第二金属氧化物子层进行导体化,第一金属氧化物子层被栅极覆盖的部分作为沟道区,第二金属氧化物子层形成像素电极；形成覆盖栅极的层间绝缘层；在层间绝缘层上形成源漏极以形成薄膜晶体管。该实施方式通过一层金属氧化物层形成沟道区和像素电极,简化了工艺步骤。(The embodiment of the invention discloses an array substrate, a manufacturing method thereof and a display panel. In one embodiment, the method of making includes: forming a common electrode and a first buffer layer on a substrate; forming a metal oxide layer on the first buffer layer, and patterning the metal oxide layer to form a first metal oxide sub-layer and a second metal oxide sub-layer; forming a grid electrode on the first metal oxide sublayer, wherein the orthographic projection part of the grid electrode on the substrate covers the orthographic projection of the first metal oxide sublayer on the substrate; conducting a first metal oxide sublayer and a second metal oxide sublayer, wherein the part of the first metal oxide sublayer covered by the grid is used as a channel region, and the second metal oxide sublayer forms a pixel electrode; forming an interlayer insulating layer covering the gate electrode; and forming a source drain electrode on the interlayer insulating layer to form a thin film transistor. The embodiment forms the channel region and the pixel electrode by one metal oxide layer, and simplifies the process steps.)

1. A manufacturing method of an array substrate, wherein the array substrate comprises a plurality of sub-pixels arranged in an array and a thin film transistor for driving each sub-pixel, the manufacturing method is characterized by comprising the following steps:

forming a common electrode and a first buffer layer covering the common electrode on a substrate;

forming a metal oxide layer on the first buffer layer, and patterning the metal oxide layer to form a first metal oxide sub-layer and a second metal oxide sub-layer;

forming a gate insulating layer and a gate electrode covering the gate insulating layer on the first metal oxide sublayer, wherein the orthographic projection part of the gate electrode on the substrate covers the orthographic projection of the first metal oxide sublayer on the substrate;

conducting the first metal oxide sublayer and the second metal oxide sublayer, wherein the part of the first metal oxide sublayer covered by the gate insulating layer is used as a channel region, and the second metal oxide sublayer forms a pixel electrode;

forming an interlayer insulating layer covering the gate electrode;

and forming a source drain electrode on the interlayer insulating layer to form a thin film transistor.

2. The method of manufacturing according to claim 1, wherein the forming a common electrode and a first buffer layer covering the common electrode on a substrate further comprises:

forming a common electrode material layer on the substrate;

forming a first photoresist layer on the common electrode material layer, and patterning the first photoresist layer to form a second photoresist layer, wherein the second photoresist layer comprises an opening;

and etching the common electrode material layer based on the second photoresist layer to form the common electrode, wherein the common electrode comprises a first pore.

3. The method of manufacturing according to claim 2,

after the forming of the common electrode material layer on the substrate and before the forming of the first photoresist layer on the common electrode material layer, further comprising: forming a light shielding layer on the common electrode material layer;

the etching the common electrode material layer based on the second photoresist layer to form the common electrode further comprises:

etching the light shielding layer based on the second photoresist layer to form a light shielding sublayer, wherein the light shielding sublayer comprises a second pore;

and etching the common electrode material layer based on the second photoresist layer to form the common electrode, wherein the orthographic projection of the first aperture on the substrate covers the orthographic projection of the second aperture on the substrate.

4. The method of claim 3, wherein the second photoresist layer comprises a first region and a second region, the second region having a thickness less than a thickness of the first region,

after the etching the common electrode material layer based on the second photoresist layer to form the common electrode, the method further includes:

performing first ashing treatment on the second photoresist layer to remove the second region to form a second photoresist sublayer;

carrying out wet etching on the shading sublayer based on the second photoresist sublayer to form shading parts, wherein the shading parts comprise first shading parts, and the orthographic projection of the first shading parts on the substrate covers the orthographic projection of the channel region on the substrate; and

and performing second ashing treatment on the second photoresist sublayer to make the orthographic projection of the light shielding part on the substrate fall in the orthographic projection of the light shielding part on the substrate.

5. The method of manufacturing according to claim 3,

the opening is disposed in the first region, and the light-shielding portion further includes a second light-shielding portion having an orthographic projection on the substrate between an orthographic projection of the first aperture on the substrate and an orthographic projection of a pixel electrode to be formed on the substrate, or

The opening is disposed between the first region and the second region.

6. The method of manufacturing according to claim 1,

the first buffer layer comprises a first buffer sub-layer and a second buffer sub-layer formed on one side, far away from the substrate, of the first buffer sub-layer, the first buffer sub-layer is made of silicon nitride, the second buffer sub-layer is made of silicon dioxide, and/or

Forming a source drain on the interlayer insulating layer to form a thin film transistor further comprises:

forming a second buffer layer on the source and drain electrodes, patterning the second buffer layer to expose the pixel electrode to form a thin film transistor,

the second buffer layer comprises a third buffer sub-layer and a fourth buffer sub-layer formed on one side, far away from the substrate, of the third buffer sub-layer, the third buffer sub-layer is made of silicon dioxide, and the fourth buffer sub-layer is made of silicon nitride.

7. The method of claim 1, wherein forming a source and a drain on the interlayer insulating layer to form a thin film transistor further comprises:

and conducting the pixel electrode.

8. The manufacturing method according to any one of claims 1 to 7, wherein the metal oxide layer is made of indium gallium zinc oxide, and the common electrode material layer is made of indium oxide.

9. An array substrate comprises a plurality of sub-pixels arranged in an array and a thin film transistor for driving each sub-pixel,

the channel region of the thin film transistor is made of metal oxide, the pixel electrode is made of conductive metal oxide, and the channel region of the thin film transistor and the pixel electrode are arranged on the same layer.

10. A display panel comprising the array substrate according to claim 9.

Technical Field

The invention relates to the technical field of display. And more particularly, to an array substrate, a method of manufacturing the same, and a display panel.

Background

A Thin Film Transistor Liquid Crystal Display (TFT-LCD) device has the characteristics of small volume, low power consumption, no radiation, and the like. Fringe Field Switching (FFS) technology generates a Fringe electric field by using electrodes between pixels in the same plane, so that aligned liquid crystal molecules between the electrodes and right above the electrodes can generate rotation conversion in a plane direction (parallel to a substrate), and the light transmission efficiency of a liquid crystal layer is improved while the viewing angle is increased.

At present, in a manufacturing process of an FFS type TFT-LCD array substrate, a top gate self-aligned device structure is generally adopted, wherein a mask process is required for forming a light shielding layer, an oxide semiconductor layer, a gate insulating layer, a gate pattern, an interlayer insulating layer, a gate drain electrode, an active insulating layer, a common electrode, first and second buffer layers, and a pixel electrode, respectively, so that 9 mask processes are required in total, which makes a process of manufacturing the array substrate too complicated, resulting in high cost.

Disclosure of Invention

The present invention aims to provide a solution to at least one of the problems of the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention provides a manufacturing method of an array substrate, wherein the array substrate comprises a plurality of sub-pixels arranged in an array and a thin film transistor for driving each sub-pixel, and the method comprises the following steps:

forming a common electrode and a first buffer layer covering the common electrode on a substrate;

forming a metal oxide layer on the first buffer layer, and patterning the metal oxide layer to form a first metal oxide sub-layer and a second metal oxide sub-layer;

forming a grid electrode insulating layer and a grid electrode covering the grid electrode insulating layer on the first metal oxide sub-layer, wherein the orthographic projection part of the grid electrode on the substrate covers the orthographic projection of the first metal oxide sub-layer on the substrate;

conducting a first metal oxide sublayer and a second metal oxide sublayer, wherein the part of the first metal oxide sublayer covered by the grid is used as a channel region, and the second metal oxide sublayer forms a pixel electrode;

forming an interlayer insulating layer covering the gate electrode;

and forming a source drain electrode on the interlayer insulating layer to form a thin film transistor.

In some optional embodiments, forming the common electrode on the substrate and the first buffer layer covering the common electrode further include:

forming a common electrode material layer on a substrate;

forming a first photoresist layer on the common electrode material layer, and patterning the first photoresist layer to form a second photoresist layer, wherein the second photoresist layer comprises an opening;

and etching the common electrode material layer based on the second photoresist layer to form a common electrode, wherein the common electrode comprises a first pore.

In some of the alternative embodiments, the first and second,

after forming the common electrode material layer on the substrate and before forming the first photoresist layer on the common electrode material layer, the method further includes: forming a light-shielding layer on the common electrode material layer;

etching the common electrode material layer based on the second photoresist layer to form the common electrode further comprises:

etching the shading layer based on the second photoresist layer to form a shading sublayer, wherein the shading sublayer comprises a second pore;

and etching the common electrode material layer based on the second photoresist layer to form a common electrode, wherein the orthographic projection of the first hole on the substrate covers the orthographic projection of the second hole on the substrate.

In some alternative embodiments, the second photoresist layer includes a first region and a second region, the second region having a thickness less than the thickness of the first region,

after etching the common electrode material layer based on the second photoresist layer to form the common electrode, the method further includes:

performing first ashing treatment on the second photoresist layer to remove the second region to form a second photoresist sublayer;

wet etching is carried out on the shading sublayer on the basis of the second photoresist sublayer to form shading parts, wherein the shading parts comprise first shading parts, and the orthographic projection of the first shading parts on the substrate covers the orthographic projection of the channel region on the substrate; and

and performing secondary ashing treatment on the second photoresist sublayer to make the orthographic projection of the light shielding part on the substrate fall in the orthographic projection of the light shielding part on the substrate.

In some of the alternative embodiments, the first and second,

the opening is disposed in the first region, and the light-shielding portion further includes a second light-shielding portion having an orthographic projection on the substrate between an orthographic projection of the first aperture on the substrate and an orthographic projection of the pixel electrode to be formed on the substrate, or

The opening is disposed between the first region and the second region.

In some of the alternative embodiments, the first and second,

the first buffer layer comprises a first buffer sub-layer and a second buffer sub-layer formed on one side of the first buffer sub-layer far away from the substrate, the first buffer sub-layer is made of silicon nitride, the second buffer sub-layer is made of silicon dioxide, and/or

Forming a source drain on the interlayer insulating layer to form a thin film transistor further includes:

forming a second buffer layer on the source and drain electrodes, patterning the second buffer layer to expose the pixel electrode to form a thin film transistor,

the second buffer layer comprises a third buffer sub-layer and a fourth buffer sub-layer formed on the side, far away from the substrate, of the third buffer sub-layer, the third buffer sub-layer is made of silicon dioxide, and the fourth buffer sub-layer is made of silicon nitride.

In some optional embodiments, forming a source drain on the interlayer insulating layer to form the thin film transistor further includes:

the pixel electrode is made conductive.

In some alternative embodiments, the metal oxide layer is made of indium gallium zinc oxide, and the common electrode material layer is made of indium oxide.

The second aspect of the present invention provides an array substrate, comprising a plurality of sub-pixels arranged in an array and a thin film transistor driving each sub-pixel,

the channel region of the thin film transistor is made of metal oxide, the pixel electrode is made of conductive metal oxide, and the channel region of the thin film transistor and the pixel electrode are arranged on the same layer.

A third aspect of the invention provides a display panel comprising the array substrate described above.

The invention has the following beneficial effects:

aiming at the existing problems, the invention sets an array substrate, a manufacturing method thereof and a display panel, forms a first metal oxide sub-layer and a second metal oxide sub-layer by patterning a metal oxide layer, conducts the first metal oxide sub-layer and the second metal oxide sub-layer to take the part which is shielded by a grid and is not conducted in the first metal oxide sub-layer as a channel region, and takes the second metal oxide sub-layer which is conducted as a pixel electrode, so that the channel region and the pixel electrode are formed by one-time patterning of one metal oxide layer, the process steps are simplified, the process complexity is reduced, the production cost is reduced, the market competitiveness of the product is improved, and the array substrate has a wide application prospect.

Drawings

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

Fig. 1 is a flowchart illustrating a method of fabricating an array substrate according to an embodiment of the present invention;

fig. 2 to 5 are cross-sectional views illustrating a flow of a method of fabricating an array substrate according to an embodiment of the present invention;

fig. 6 is a schematic top view illustrating a common electrode formed in a method of fabricating an array substrate according to an embodiment of the present invention; and

fig. 7 to 17 are cross-sectional views illustrating a flow of a method of fabricating an array substrate according to an embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the present invention, the present invention will be further described with reference to the following examples and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.

It should be noted that, when the description "has", "includes", "including", etc. in the present invention are all open-ended, that is, when the description module "has", "includes" or "includes" the first element, the second element and/or the third element, it means that the module includes other elements in addition to the first element, the second element and/or the third element. In addition, the ordinal numbers such as "first", "second", and "third" in the present invention are not intended to limit the specific sequences, but only to distinguish the respective parts.

The terms "on … …", "formed on … …" and "disposed on … …" as used herein may mean that one layer is formed or disposed directly on another layer or that one layer is formed or disposed indirectly on another layer, i.e., there is another layer between the two layers.

In addition, in the present invention, the term "disposed on the same layer" is used to mean that two layers, components, members, elements or portions may be formed by the same manufacturing process (e.g., patterning process, etc.), and the two layers, components, members, elements or portions are generally formed of the same material. For example, two or more functional layers are arranged in the same layer, which means that the functional layers arranged in the same layer can be formed by using the same material layer and using the same manufacturing process, so that the manufacturing process of the display substrate can be simplified.

In view of the above problems, referring to fig. 1, an embodiment of the present invention provides a method for manufacturing an array substrate, where the array substrate includes a plurality of sub-pixels arranged in an array and a thin film transistor driving each sub-pixel, the method including:

s1, forming a common electrode and a first buffer layer covering the common electrode on the substrate;

s2, forming a metal oxide layer on the first buffer layer, and patterning the metal oxide layer to form a first metal oxide sub-layer and a second metal oxide sub-layer;

s3, forming a grid electrode insulating layer and a grid electrode covering the grid electrode insulating layer on the first metal oxide sub-layer, wherein the orthographic projection part of the grid electrode on the substrate covers the orthographic projection of the first metal oxide sub-layer on the substrate;

s4, conducting the first metal oxide sub-layer and the second metal oxide sub-layer, wherein the part of the first metal oxide sub-layer covered by the grid is used as a channel region, and the second metal oxide sub-layer forms a pixel electrode;

s5, forming an interlayer insulating layer covering the grid;

and S6, forming a source drain electrode on the interlayer insulating layer to form the thin film transistor.

In the embodiment, the first metal oxide sublayer and the second metal oxide sublayer are formed by patterning the metal oxide layer, the first metal oxide sublayer and the second metal oxide sublayer are conducted with conductimerization, the portion, which is shielded by the grid electrode and is not conducted, of the first metal oxide sublayer is used as the channel region, and the second metal oxide sublayer conducted with the conductimerization is used as the pixel electrode, so that the channel region and the pixel electrode are formed by patterning the metal oxide layer once, the process steps are simplified, the process complexity is reduced, the production cost is reduced, the market competitiveness of the product is improved, and the method has a wide application prospect.

The method for manufacturing the array substrate according to the embodiment of the present invention is described in detail by specific examples with reference to fig. 2 to 17.

In step S1, the common electrode 101 and the first buffer layer 104 covering the common electrode 101 are formed on the substrate 100.

Specifically, as shown in fig. 2, in step S11, a common electrode material layer 101-1 is formed on the provided substrate 100. For example, the substrate 100 may be a glass substrate, and the material of the common electrode material layer 101-1 may be Indium Tin Oxide (ITO). This is, of course, merely exemplary and the invention is not intended to be limited.

In step S12, forming a first photoresist layer on the common electrode material layer, and patterning the first photoresist layer to form a second photoresist layer, where the second photoresist layer includes an opening; in step S13, the common electrode material layer is etched based on the second photoresist layer to form a common electrode, and the common electrode includes a first aperture. The position of the opening in the second photoresist layer corresponds to the position of the first aperture formed in the common electrode, that is, the first aperture is included in the formed common electrode by using the opening in the second photoresist layer.

In consideration of the fact that a metal oxide of a channel region of a thin film transistor to be formed, for example, gallium indium zinc oxide (IGZO) is sensitive to light, in the present example, a light shielding portion needs to be formed on the common electrode. The specific method steps in this example are described in further detail below with reference to fig. 2-7.

Specifically, in this example, referring to fig. 2, after the common electrode material layer 101-1 is formed on the substrate, the light-shielding layer 102-1 is formed on the common electrode material layer 101-1. The material of the light shielding layer 102-1 may be an opaque metal, such as copper (Cu), but is not limited thereto.

As shown in fig. 3, a first photoresist layer is formed on the light-shielding layer 102-1, and a second photoresist layer 103 is formed by patterning the first photoresist layer. The material of the first photoresist layer 103 may be organic planarization layer photoresist (JAS). As shown in fig. 3, the second photoresist layer 103 includes an opening at a position corresponding to a position of the first aperture in the pixel electrode to be formed. Further, in this example, the second photoresist layer 103 further includes a first region and a second region, the second region having a thickness smaller than that of the first region, the first region being used for forming the light shielding portion in the subsequent step.

The step S13 of etching the common electrode material layer based on the second photoresist layer to form the common electrode specifically includes the following steps in this example.

In step S131, after the second photoresist layer 103 is formed, the light shielding layer 102-1 is etched based on the second photoresist layer 103 to form a light shielding sublayer. Preferably, the etching method may be wet etching. For example, when the material of the light-shielding layer 102-1 is Cu, the light-shielding layer 102-1 is wet-etched using an organic acid that etches Cu, thereby forming the light-shielding sublayer 102-2 as shown in fig. 4. A second aperture is formed in the light shielding sublayer 102-2 at a position corresponding to the opening of the second photoresist layer 103.

Referring to fig. 5, the common electrode 101 is formed by etching the common electrode material layer 101-1 based on the second photoresist layer 103, and the common electrode 101 includes a first aperture, and an orthographic projection of the first aperture on the substrate 100 covers an orthographic projection of the second aperture on the substrate. Preferably, the etching method may be wet etching. For example, when the material of the common electrode material layer 101-1 is ITO, the common electrode 101 is formed by wet etching the common electrode material layer 101-1 with an organic acid for etching ITO.

As will be understood by those skilled in the art, the common electrode is formed as a single integral block corresponding to all the sub-pixels arranged in the array substrate, and is therefore referred to as a common electrode. In an embodiment of the invention, the first aperture defines a border region of the thin film transistor. The first aperture separates the thin film transistor to be formed from the pixel electrode of the sub-pixel and the common electrode below the pixel electrode, thereby reducing the coupling capacitance of the source and drain electrodes with the pixel electrode and the corresponding common electrode.

Fig. 6 shows a schematic top view of the common electrode 101, in which a large dashed-line frame shows a boundary of a pixel electrode corresponding region, a small dashed-line frame shows a boundary of a thin film transistor corresponding region, a small solid-line frame shows a boundary of a first aperture of the common electrode, and a top view of the first aperture of the common electrode 101 is shown between a solid line of the small solid-line frame and a dashed line of the small dashed-line frame. Of course, those skilled in the art will appreciate that this is merely illustrative and is not intended to limit the specific shape and location of the thin film transistor, and that the thin film transistor may have other shapes in specific embodiments as long as the function of spacing the thin film transistor from the pixel electrode of the sub-pixel and the common electrode under the pixel electrode is satisfied.

Since the light shielding portion is to be formed in this example, after the common electrode 101 is formed, as shown in fig. 7, the second photoresist sublayer 103-1 is formed by performing the first ashing process on the second photoresist layer 103 to remove the second region. Referring to fig. 8, the light shielding part 102 is formed by wet etching the light shielding sub-layer 102-2 based on the second photoresist sub-layer 103-1, and the light shielding part 102 includes a first light shielding part, and an orthographic projection of the first light shielding part on the substrate 100 covers an orthographic projection of a channel region of a thin film transistor to be formed on the substrate. Specifically, when the material of the light-shielding layer 102-1 is Cu, the light-shielding sublayer 102-2 may be wet-etched by using an organic acid for etching Cu; after etching, baking can be performed to solidify the second photoresist sublayer 103-1, and simultaneously crystallize the common electrode, so as to stabilize the structure of the common electrode.

As can be seen, the second region can be removed by performing ashing treatment on the second photoresist layer 103, so that the photoresist remaining in the second photoresist sublayer 103-1 is used as a barrier to etch away the light-shielding material to be removed. Those skilled in the art will understand that the size of the second region can be set reasonably according to the undercut amount of the wet etching and the retraction property of the ashing, so that the formed light shielding portion 102 can form a good light shielding effect on the channel region of the thin film transistor to be formed.

In the embodiment, the common electrode is formed by etching the light shielding layer and the common electrode material layer by using the second photoresist layer as the shielding wet method, and the light shielding part is formed by etching the light shielding layer by using the second photoresist layer as the shielding wet method, so that the common electrode material and the light shielding part can be formed only by patterning the first photoresist layer once, two masks are reduced, and the process steps are simplified.

In addition, in the present example, in the second photoresist layer 103, the opening is provided in the first region, and the formed light shielding portion 102 is divided into two parts, that is, the light shielding portion 102 includes a first light shielding portion corresponding to the channel region to be formed and a second light shielding portion whose orthographic projection on the substrate 100 is located between the orthographic projection of the first aperture on the substrate 100 and the orthographic projection of the pixel electrode to be formed on the substrate. With this arrangement, the second light-shielding portion can reduce the coupling capacitance between the source and drain of the thin film transistor and the common electrode 101. It will be appreciated by those skilled in the art that the present invention is not so limited and that the opening may be provided between the first region and the second region without regard to reducing the coupling capacitance.

Further, in the present example, since the wet-etched light shielding portion 102 is smaller than the second photoresist sublayer 103-1 covering the same, when the size is small, the subsequently formed structural layer is prone to cause undercut fracture. Therefore, referring to fig. 9, after the light shielding portion 102 is formed, the second photoresist sublayer 103-1 is subjected to the second ashing process to shrink the second photoresist sublayer so that the orthographic projection of the light shielding portion 102 on the substrate 100 falls within the orthographic projection of the light shielding portion 102 on the substrate 100, thereby avoiding the undercut fracture problem.

In the embodiment of the invention, the residual photoresist 103-3 does not need to be removed, and the residual photoresist 103-3 is remained, so that the coupling capacitance between the source and drain electrodes and the common electrode can be further reduced.

Thereafter, as shown in fig. 10, a first buffer layer 104 is formed on the remaining photoresist 103-3. Optionally, the first buffer layer 104 includes a first buffer sub-layer and a second buffer sub-layer formed on a side of the first buffer sub-layer away from the substrate. Preferably, the material of the first buffer sub-layer is silicon nitride (SiNx), and the material of the second buffer sub-layer is silicon dioxide (SiO)₂) Since SiNx is compared to SiO₂Alkali ions in the substrate can be better blocked, and the alkali ions are prevented from being diffused into the metal oxide to have adverse effects on the electrical characteristics of the metal oxide.

Next, referring to fig. 11, in step S2, a metal oxide layer is formed on the first buffer layer 104, and the metal oxide layer is patterned to form a first metal oxide sub-layer and a second metal oxide sub-layer. Wherein, the material of the metal oxide layer may be IGZO.

In step S3, referring to fig. 12, a gate insulating layer 107 and a gate electrode 106 covering the gate insulating layer are formed on the first metal oxide sublayer. Specifically, a gate insulating layer 107 is formed on the first metal oxide sublayer, and a gate electrode 106 is formed on the gate insulating layer 107, the gate electrode 106 covering the gate insulating layer 107. The material of the gate electrode comprises metal or alloy material such as aluminum, titanium, cobalt and the like. The gate insulating layer may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Wherein, the orthographic projection of the gate 106 on the substrate 100 covers the orthographic projection of the first metal oxide sublayer on the substrate.

In step S4, referring to fig. 13, the first metal oxide sublayer and the second metal oxide sublayer are made conductive, and a portion of the first metal oxide sublayer covered with the gate serves as a channel region. That is, the region of the first metal oxide sublayer covered by the gate electrode 106 is not made conductive, is not yet made semiconductive, serves as a channel region, and is made conductive because it is not blocked, and serves as an auxiliary metal in contact with the source and drain electrodes; the second metal oxide sub-layer forms the pixel electrode 105. It should be noted that fig. 13 only shows one pixel electrode 105 and a corresponding thin film transistor portion to be formed in the cross-sectional view, where the pixel electrode 105 shows a plurality of portions in the figure because the pixel electrode is a hollow pattern, and the cross-sectional view is cut into a plurality of interrupted portions, and the hollow pattern may be in a shape of a fish scale, a horse, and the like, and the application is not limited in particular.

In step S5, referring to fig. 14, an interlayer insulating layer 108 covering the gate 106 is formed, the interlayer insulating layer 108 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the interlayer insulating layer material layer may be formed by depositing on the gate and patterning to expose a region corresponding to the auxiliary metal in the first metal oxide sublayer.

In step S6, referring to fig. 14, source and drain electrodes 109 are formed on the interlayer insulating layer 108 to form a thin film transistor. The material of the source/drain 109 may be one of Ag, Al, Mo, and other metals or alloys thereof, but the present invention is not intended to be limited thereto.

Alternatively, as shown in fig. 15, in the step of forming the source and drain electrodes 109 to form the thin film transistor, a second buffer layer 110 may be further formed on the formed source and drain electrodes 109, and the second buffer layer is patterned to expose the pixel electrode 105 to form the thin film transistor. The second buffer layer 110 includes a third buffer sub-layer and a fourth buffer sub-layer formed on a side of the third buffer sub-layer away from the substrate, and the third buffer sub-layer is made of SiO₂And the material of the fourth buffer sublayer is SiNx. Since SiNx is compared to SiO₂Has more water resistance compared with SiO₂The top layer can prevent the erosion of the device caused by external water vapor,the performance of the thin film transistor is ensured.

It should be noted that, as shown in fig. 16, if the inter-layer insulating layer is not patterned to expose the pixel electrode 105 when the second buffer layer is formed, a step of patterning the second buffer layer to expose the pixel electrode 105 to form the thin film transistor also implicitly includes a step of patterning the inter-layer insulating layer to expose the pixel electrode 105, and details thereof are not repeated herein.

Further alternatively, as shown in fig. 17, forming a source drain on the interlayer insulating layer 108 to form a thin film transistor further includes: when the pixel electrode 105 is made conductive, that is, the pixel electrode 105 is made secondary conductive, the pixel electrode 105-2 made secondary conductive can have a further improved transmittance and a further reduced resistivity, and has more excellent metal characteristics.

In the embodiment of the invention, the channel region and the pixel electrode are formed by forming the metal oxide sub-layers of the first metal oxide sub-layer and the second oxide sub-layer by using the same layer of metal oxide material, forming the gate on the first metal oxide sub-layer, and conducting the first metal oxide sub-layer and the second metal oxide sub-layer by using the gate as a barrier. In the invention, the channel region and the pixel electrode can be formed only by patterning once, thereby reducing the mask patterning process, simplifying the process steps and reducing the process complexity, thereby reducing the production cost, improving the market competitiveness of the product and having wide application prospect.

In addition, the number of the mask plates is further reduced by forming the common electrode in a gradual wet etching mode by taking the second photoresist layer as a barrier and utilizing ashing treatment and wet etching to form a light shielding part when needed. For the example where the light shielding portion needs to be formed, two masks can be reduced compared to the prior art in which a dry etching method is used. Thereby further simplifying the process steps and reducing the process complexity, thereby reducing the production cost and improving the market competitiveness of the product.

The embodiment of the invention also provides an array substrate corresponding to the manufacturing method of the array substrate, the array substrate is manufactured by the manufacturing method, the array substrate comprises a plurality of sub-pixels arranged in an array and a thin film transistor for driving each sub-pixel, a channel region of the thin film transistor is made of metal oxide, a pixel electrode is made of conductive metal oxide, and the channel region of the thin film transistor and the pixel electrode are arranged on the same layer.

In the embodiment, the number of masks can be reduced, the process steps can be simplified, and the process complexity can be reduced by the structure, so that the production cost can be reduced, the market competitiveness of products can be improved, and the wide application prospect can be realized.

Corresponding to the array substrate, an embodiment of the invention further provides a display panel, including the array substrate described above.

Since the array substrate included in the display panel provided in the embodiments of the present application corresponds to the array substrates provided in the above-mentioned several embodiments, the foregoing embodiments are also applicable to the embodiments, and detailed description is omitted in the embodiments.

In this embodiment, the display panel may be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a vehicle-mounted display, a digital photo frame, or a navigator, and the display device may reduce the production cost and have stronger market competitiveness by loading the display panel.

Aiming at the existing problems, the invention sets an array substrate, a manufacturing method thereof and a display panel, forms a first metal oxide sub-layer and a second metal oxide sub-layer by patterning a metal oxide layer, conducts the first metal oxide sub-layer and the second metal oxide sub-layer to take the part which is shielded by a grid and is not conducted in the first metal oxide sub-layer as a channel region, and takes the second metal oxide sub-layer which is conducted as a pixel electrode, so that the channel region and the pixel electrode are formed by one-time patterning of one metal oxide layer, the process steps are simplified, the process complexity is reduced, the production cost is reduced, the market competitiveness of the product is improved, and the array substrate has a wide application prospect.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations and modifications can be made on the basis of the above description, and all embodiments cannot be exhaustive, and all obvious variations and modifications belonging to the technical scheme of the present invention are within the protection scope of the present invention.