阅读说明：本技术 三维存储器及其制备方法 (Three-dimensional memory and preparation method thereof ) 是由 陈亮 于 2021-09-07 设计创作，主要内容包括：本申请提供了一种三维存储器及其制备方法。该三维存储器包括：第一半导体器件,包括：衬底；多个外围器件,外围器件的一部分位于衬底的阱中；半导体层,与衬底相邻设置；多个存储串结构,位于半导体层上,并与半导体层电耦合；以及深沟槽隔离结构,包括：第一部分,贯穿衬底和/或半导体层,以使半导体层和衬底之间电隔离；第二部分,贯穿衬底并围绕阱设置,以使外围器件之间电隔离。本申请提供的三维存储器及其制备方法,能够简化隔离结构及其制备工艺,降低制造成本,提高外围器件的性能,可避免外围器件之间的穿通问题。此外,会削弱甚至避免外围器件和多个存储串结构之间的相互影响。(The application provides a three-dimensional memory and a preparation method thereof. The three-dimensional memory includes: a first semiconductor device comprising: a substrate; a plurality of peripheral devices, a portion of the peripheral devices being located in the well of the substrate; a semiconductor layer disposed adjacent to the substrate; a plurality of memory string structures on and electrically coupled to the semiconductor layer; and a deep trench isolation structure comprising: a first portion extending through the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; and a second portion extending through the substrate and disposed around the well to electrically isolate the peripheral devices. The three-dimensional memory and the preparation method thereof can simplify the isolation structure and the preparation process thereof, reduce the manufacturing cost, improve the performance of peripheral devices and avoid the problem of punch-through between the peripheral devices. Furthermore, interactions between peripheral devices and multiple memory string structures may be weakened or even avoided.)

1. A three-dimensional memory, comprising:

a first semiconductor device comprising:

a substrate;

a plurality of peripheral devices, a portion of the peripheral devices being located in a well of the substrate;

a semiconductor layer disposed adjacent to the substrate;

a plurality of memory string structures on and electrically coupled to the semiconductor layer; and

a deep trench isolation structure comprising:

a first portion extending through the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate;

a second portion extending through the substrate and disposed around the well to electrically isolate the peripheral devices.

2. The three-dimensional memory according to claim 1, wherein the peripheral device comprises a high voltage MOS device.

3. The three-dimensional memory according to claim 1, wherein the substrate comprises a first side on which the plurality of peripheral devices are formed, and a second side opposite the first side, wherein the deep trench isolation structure penetrates the substrate and/or the semiconductor layer from the second side.

4. The three-dimensional memory according to claim 3, further comprising:

and the back-end-of-line interconnection layer is positioned on the second side of the substrate, wherein the deep trench isolation structure sequentially penetrates through the back-end-of-line interconnection layer and the substrate and/or the semiconductor layer from the second side.

5. The three-dimensional memory according to any one of claims 1 to 4, further comprising:

a shallow trench isolation structure located between the well and the deep trench isolation structure, extending in the substrate and through a portion of the substrate.

6. The three-dimensional memory according to claim 5, wherein the shallow trench isolation structure extends from the first side to the second side and through a portion of the substrate.

7. The three-dimensional memory according to claim 5, wherein the shallow trench isolation structure and the deep trench isolation structure have a predetermined distance therebetween.

8. The three-dimensional memory according to claim 5, wherein a critical dimension of the shallow trench isolation structure is smaller than a critical dimension of the deep trench isolation structure.

9. The three-dimensional memory according to claim 1, further comprising:

and the second semiconductor device is positioned on one side far away from the substrate and is in bonding connection with the first semiconductor device, wherein the second semiconductor device comprises a plurality of low-voltage MOS devices and/or ultra-low-voltage MOS devices.

10. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

forming a plurality of peripheral devices in a first region of a substrate, a portion of the peripheral devices being located in a well of the substrate;

forming a plurality of memory string structures in a second region of the substrate;

removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures; and

forming a deep trench isolation structure, wherein the deep trench isolation structure comprises: a first portion extending through the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; and a second portion extending through the substrate and disposed around the well to electrically isolate the peripheral devices.

11. The method of claim 10, wherein the step of removing the portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures comprises: removing a portion of the substrate corresponding to the first region to expose the well, wherein a thickness of the semiconductor layer is the same as a thickness of the well.

12. The method of claim 10, wherein the peripheral device comprises a high voltage MOS device.

13. The method of claim 10, wherein the substrate includes a first side on which the plurality of peripheral devices are formed, and a second side opposite the first side, wherein forming a deep trench isolation structure comprises:

forming a first trench through the substrate and/or the semiconductor layer from the second side; and

and filling a dielectric material in the first trench to form the deep trench isolation structure.

14. The method of manufacturing according to claim 13, wherein the step of forming a first trench penetrating the substrate and/or the semiconductor layer from the second side includes:

forming a back-end-of-line interconnect layer on a second side of the substrate; and

forming the first trench sequentially penetrating the beol interconnect layer and the substrate and/or the semiconductor layer from the second side.

15. The method of manufacturing according to any one of claims 10 to 14, wherein, prior to the step of forming the deep trench isolation structure, the method further comprises:

forming a shallow trench isolation structure, wherein the shallow trench isolation structure is located between the well and the deep trench isolation structure, extends in the substrate and penetrates a portion of the substrate.

16. The method of claim 15, wherein the substrate includes a first side on which the plurality of peripheral devices are formed, and a second side opposite the first side, and wherein forming the shallow trench isolation structure comprises:

forming a second trench extending from the first side to the second side and through a portion of the substrate; and

and filling a dielectric material in the second trench to form the shallow trench isolation structure.

17. The method of manufacturing of claim 10, wherein the memory string structure includes an outer wall structure of an outside-in memory layer and a channel layer, and the memory string structure extends into the substrate, wherein removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures comprises:

removing a portion of a memory layer of the memory string structure extending into the substrate to expose the channel layer; and

forming the semiconductor layer overlying the channel layer.

18. The method of claim 15, wherein the shallow trench isolation structure and the deep trench isolation structure have a predetermined distance therebetween.

19. The method of claim 15, wherein a critical dimension of the shallow trench isolation structure is smaller than a critical dimension of the deep trench isolation structure.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a three-dimensional memory and a method for fabricating the same.

Background

In the Xtacking architecture based three-dimensional memory (3D NAND), peripheral circuits responsible for data I/O and memory cell operations are formed on the same substrate, while a memory string structure is formed on another substrate. After the two semiconductor structures are respectively prepared, the two semiconductor structures are connected in a bonding mode, so that the memory string structure and the peripheral circuit are connected.

However, as the number of stacked layers of the 3D NAND technology increases, the size of a semiconductor structure for forming a memory string structure is reduced with the same memory capacity. Accordingly, the semiconductor structure having the peripheral circuit bonded to the semiconductor structure having the memory string structure needs to be reduced, which may affect the layout formation of the peripheral circuit, and thus the circuit-connection performance of the peripheral circuit to the memory string structure.

In addition, some peripheral circuits (e.g., bit line drivers of page buffers) require the use of high voltages to support storage functions, such as erasing and programming memory cells. However, as the size of the peripheral circuit chip is reduced, the isolation between the peripheral devices becomes complicated, which is not favorable for achieving the desired isolation effect between the peripheral devices and/or between the peripheral devices and the memory string structure.

Disclosure of Invention

The present application provides a three-dimensional memory, comprising: a first semiconductor device comprising: a substrate; a plurality of peripheral devices, a portion of the peripheral devices being located in the well of the substrate; a semiconductor layer disposed adjacent to the substrate; a plurality of memory string structures on and electrically coupled to the semiconductor layer; and a deep trench isolation structure comprising: a first portion extending through the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; and a second portion extending through the substrate and disposed around the well to electrically isolate the peripheral devices.

In some embodiments, the peripheral device comprises a high voltage MOS device.

In some embodiments, the substrate includes a first side on which a plurality of peripheral devices are formed, and a second side opposite the first side, wherein the deep trench isolation structure penetrates the substrate and/or the semiconductor layer from the second side.

In some embodiments, the three-dimensional memory further comprises: and the back-end-of-line interconnection layer is positioned on the second side of the substrate, wherein the deep trench isolation structure sequentially penetrates through the back-end-of-line interconnection layer and the substrate and/or the semiconductor layer from the second side.

In some embodiments, the three-dimensional memory further comprises: and the shallow trench isolation structure is positioned between the trap and the deep trench isolation structure, extends in the substrate and penetrates through part of the substrate.

In some embodiments, the shallow trench isolation structure extends from the first side to the second side and through a portion of the substrate.

In some embodiments, the shallow trench isolation structure and the deep trench isolation structure have a predetermined distance therebetween.

In some embodiments, the critical dimension of the shallow trench isolation structure is smaller than the critical dimension of the deep trench isolation structure.

In some embodiments, a second semiconductor device is located on a side away from the substrate and is in bonding connection with the first semiconductor device, wherein the second semiconductor device comprises a plurality of low-voltage MOS devices and/or ultra-low-voltage MOS devices.

The application also provides a preparation method of the three-dimensional memory. The preparation method comprises the following steps: forming a plurality of peripheral devices in a first region of a substrate, a portion of the peripheral devices being located in a well of the substrate; forming a plurality of memory structures in a second region of the substrate; removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures; and forming a deep trench isolation structure, wherein the deep trench isolation structure comprises: a first portion extending through the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; and a second portion extending through the substrate and disposed around the well to electrically isolate the peripheral devices.

In some embodiments, the removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures includes: and removing a portion of the substrate corresponding to the first region to expose the well, wherein the semiconductor layer has the same thickness as the well.

In some embodiments, the peripheral device comprises a high voltage MOS device.

In some embodiments, the substrate includes a first side on which a plurality of peripheral devices are formed, and a second side opposite the first side, wherein the step of forming the deep trench isolation structure includes: forming a first trench through the substrate and/or the semiconductor layer from the second side; and filling a dielectric material in the first trench to form a deep trench isolation structure.

In some embodiments, the step of forming a first trench through the substrate and/or the semiconductor layer from the second side comprises: forming a back-end-of-line interconnect layer on a second side of the substrate; and forming a first trench sequentially penetrating the beol interconnect layer and the substrate and/or the semiconductor layer from the second side.

In some embodiments, before the step of forming the deep trench isolation structure, the method further comprises: and forming a shallow trench isolation structure, wherein the shallow trench isolation structure is positioned between the well and the deep trench isolation structure, extends in the substrate and penetrates through part of the substrate.

In some embodiments, the substrate includes a first side on which a plurality of peripheral devices are formed, and a second side opposite the first side, wherein the step of forming the shallow trench isolation structure includes: forming a second trench extending from the first side to the second side and through a portion of the substrate; and filling dielectric material in the second trench to form a shallow trench isolation structure.

In some embodiments, the memory string structure includes an outer wall structure of the memory layer and the channel layer from the outside inward, and the memory string structure extends into the substrate, wherein the step of removing a portion of the substrate corresponding to the second region and forming the semiconductor layer electrically coupled to the plurality of memory string structures includes: removing a portion of a memory layer of the memory string structure extending into the substrate to expose the channel layer; and forming a semiconductor layer covering the channel layer.

In some embodiments, the shallow trench isolation structure and the deep trench isolation structure have a predetermined distance therebetween.

In some embodiments, the critical dimension of the shallow trench isolation structure is smaller than the critical dimension of the deep trench isolation structure.

According to the three-dimensional memory and the preparation method thereof, the deep trench isolation structures are used for providing electrical isolation among the plurality of peripheral devices and between the peripheral devices and the plurality of memory string structures, so that the formation of isolation structures such as a deep N well and a high-doping-concentration region can be avoided, the isolation structures and the preparation process thereof can be simplified, and the manufacturing cost can be reduced. Meanwhile, the substrate depth required by the peripheral device can be reduced, so that the performance of the peripheral device is improved. The deep trench isolation structure divides the peripheral devices into relatively independent devices, so that the problem of punch-through among the peripheral devices can be avoided. In addition, since the deep trench isolation structure has a relatively good electrical isolation effect, the mutual influence between the peripheral device and the memory string structure can be weakened or even avoided.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the present application;

FIG. 2 is a schematic top view of a portion of a three-dimensional memory according to an embodiment of the present application;

FIG. 3 is a cross-sectional view of a peripheral device of a conventional three-dimensional memory;

FIG. 4 is a cross-sectional schematic view of a three-dimensional memory according to another embodiment of the present application;

FIG. 5 is a schematic top view of a portion of a three-dimensional memory according to another embodiment of the present application;

FIG. 6 is a partial enlarged view of the three-dimensional memory shown in FIG. 4;

FIG. 7 is a flow chart of a method of fabricating a three-dimensional memory according to an embodiment of the present application; and

fig. 8A to 8E are schematic process cross-sectional views illustrating a method of fabricating a three-dimensional memory according to an embodiment of the present disclosure.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying or overlying structure or can have a smaller extent than the underlying or overlying structure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, above, and/or below. The layer can comprise a plurality of layers.

Fig. 1 is a schematic cross-sectional view of a three-dimensional memory 10 according to an embodiment of the present application. Fig. 2 is a schematic top view of a portion of a three-dimensional memory 10 according to an embodiment of the present application. Among them, the peripheral devices 120-2 and 120-3 shown in fig. 1 may be a cross-sectional structure along a section line BB' in fig. 2. As shown in fig. 1 and 2, the three-dimensional memory 10 includes: the memory device includes a substrate 110, a semiconductor layer 136, a plurality of peripheral devices 120, a plurality of memory string structures 131, and a deep trench isolation structure 140. A portion of the peripheral device 120 is located in the well 121 of the substrate 110. Semiconductor layer 136 may be disposed adjacent substrate 110. A plurality of memory string structures 131 are located on the semiconductor layer 136 and electrically coupled to the semiconductor layer 136. The deep trench isolation structure 140 includes a first portion 141 and a second portion 142, wherein the first portion 141 penetrates the substrate 110 and/or the semiconductor layer 136 to electrically isolate the semiconductor layer 136 from the substrate 110. The second portion 142 extends through the substrate 110 and is disposed around the well 121 to electrically isolate the plurality of peripheral devices 120 from each other.

Substrate 110 may include silicon (e.g., single crystal silicon, polycrystalline silicon, doped silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, group III-V compound semiconductors, and any other suitable material.

At least portions of the plurality of peripheral devices 120 (e.g., 120-1, 120-2, 120-3, 120-4, 120-5) are located in a well 121 of the substrate 110. The peripheral devices 120 may include any suitable semiconductor device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Bipolar Junction Transistor (BJT), a diode, a resistor, an inductor, a capacitor, and the like. In semiconductor devices, P-type MOSFETs and/or N-type MOSFETs (i.e., CMOS) are widely implemented in logic circuit designs, and are used in this application as examples of peripheral devices 120.

In some embodiments, where peripheral device 120 is a P-type MOSFET and/or an N-type MOSFET, the P-type MOSFET is located in an N-type doped well of substrate 110, the N-type MOSFET is located in a P-type doped well of substrate 110, and the N-type doped well and the P-type doped well may be referred to as N-well 121-2 and P-well 121-3, respectively. The dopant profile and concentration of the well 121 affects the device characteristics of the peripheral device 120. For MOSFET devices with low threshold voltage (Vth), well 121 is doped at a lower concentration to form a low voltage P-well or a low voltage N-well. For MOSFET devices with high threshold voltages, well 121 is doped at a higher concentration to form a high voltage P-well or a high voltage N-well to form a high voltage P-type MOSFET in the high voltage N-well and a high voltage N-type MOSFET in the high voltage P-well.

In some embodiments, the N-well 121-2 may be formed in the substrate 110 using N-type dopants such As phosphorus (P), arsenic (As), antimony (Sb), or any combination thereof. Similarly, a P-type dopant, such as boron (B), may be used to form P-well 121-3 in substrate 110. In addition, the doping of the dopant may be achieved by processes such as ion implantation and activation annealing.

In some embodiments, the P-type MOSFET and/or the N-type MOSFET may include a gate stack 122 (e.g., 122-2). The gate stack 122 is located above the substrate 110 with the N-well 121-1 and/or the P-well 121-2 away from the substrate 110. Gate stack 122 may include a gate dielectric layer and a gate conductive layer sequentially arranged in a direction away from substrate 110. The material of the gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, and lanthanum oxide. The material of the gate conductive layer may include a metal material such as tungsten, cobalt, nickel, copper, or aluminum. Alternatively, the material of the gate conductive layer may further include a polycrystalline semiconductor material such as polysilicon, poly germanium, poly silicon germanium, a conductive material such as titanium nitride, tantalum nitride, and any other suitable material. Alternatively, the polycrystalline semiconductor may be combined with any suitable type of dopant, such as boron, phosphorus, arsenic, and the like. Further, the process method of forming the gate dielectric layer and the gate conductive layer may include Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), sputtering, thermal oxidation/nitridation or any combination thereof.

In some embodiments, the P-type MOSFET and/or the N-type MOSFET may include isolation spacers 123. The isolation sidewall 123 is disposed around the gate stack layer 122 and exposes a surface of the gate stack layer 122 away from the substrate 110. The material of the isolation spacers 123 may comprise silicon oxide, silicon nitride, silicon oxynitride or any combination of dielectric materials. And the dielectric material may be applied over the gate stack 122 using methods such as CVD, PVD, ALD, sputtering, or combinations thereof. Further, an anisotropic dry etching process such as Reactive Ion Etching (RIE) may be used to remove a portion of the dielectric material on the surface of the gate stack layer 122 away from the substrate 110, so as to expose the surface of the gate stack layer 122 away from the substrate 110, so as to form the isolation sidewall 123.

In some embodiments, the peripheral device 120 further includes source/drains 124 located on both sides of the gate stack 122 and in the well 121. The source/drain 124 is doped with a high concentration of dopant. For an N-type MOSFET, the dopant of source/drain 124 may include an N-type dopant such as phosphorus, arsenic, antimony, or any combination thereof. For a P-type MOSFET, the dopant of source/drain 124 may comprise a P-type dopant such as boron. Furthermore, the dopant incorporation can be achieved by processes such as ion implantation and activation annealing, or by in-situ doping during the epitaxial layer preparation of the MOSFET active region. The source/drains 124 of the peripheral devices 120 may be the same material as the substrate 110. Alternatively, the material of the source/drain 124 of the peripheral device 120 may be different from the material of the substrate 110 to improve the electrical performance of the peripheral device 120.

In some embodiments, the peripheral device 120 (e.g., a high voltage N-type MOSFET and/or a high voltage P-type MOSFET) may have a Lightly Doped Drain (LDD) region 125 between the drain 124 and the gate stack 122. The lightly doped drain region 125 can reduce the peak electric field when a high voltage is applied to the drain 124, thereby achieving the purpose of weakening the hot carrier injection effect.

It should be understood that the peripheral device 120 is not limited to a MOSFET. The structures of other peripheral devices (e.g., diodes, resistors, inductors, BJTs, etc.) may be formed simultaneously during the process of making the MOSFET by different mask designs and layouts.

In some embodiments, the plurality of peripheral devices 120 may be used to form any digital, analog, and/or mixed signal circuit for peripheral circuit operations. The peripheral circuits may, for example, perform row/column decoding, timing and control, read, write, and erase data of the memory cells, and so on.

Semiconductor layer 136 is disposed adjacent substrate 110. In some embodiments, at least one of the two opposing surfaces of the semiconductor layer 136 is disposed flush with at least one of the two opposing surfaces of the substrate 110. Alternatively, in the embodiment of the present application, the thicknesses of the semiconductor layer 136 and the substrate 110 are the same, so that two opposite surfaces of the semiconductor layer 136 are disposed flush with two opposite surfaces of the substrate 110, respectively. In some embodiments, the semiconductor layer 136 may be formed as part of the semiconductor material substrate 110 and subjected to, for example, a doping process. Alternatively, the semiconductor layer 136 may be formed in a different process step than the substrate 110, which is not specifically limited herein.

In some example embodiments, the semiconductor layer 136 may include a semiconductor material having an N-type dopant with a uniform doping concentration, such as single crystal silicon, polycrystalline silicon, amorphous silicon, and the like. The N-type dopant may include, for example, phosphorus, arsenic, antimony, or any combination thereof, and the doping of the dopant may be accomplished using ion implantation and activation annealing, among other processes.

The plurality of memory string structures 131 may constitute an array of memory string structures. Each memory string structure 131 may be located above the semiconductor layer 136 and extend into the semiconductor layer 136, and a portion of the memory string structure 131 extending into the semiconductor layer 136 may be electrically coupled with the semiconductor layer 136. In some embodiments, as shown in fig. 1, the three-dimensional memory 10 may include a stacked structure 132 on a semiconductor layer 136. The stacked structure 132 may include dielectric layers 133 and conductive layers 134 alternately stacked in a direction perpendicular to the semiconductor layer 136. And the memory string structure 131 is formed in the stack structure 132.

In some embodiments, the dielectric layer 133 in the stacked structure 132 may be made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The conductive layer 134 in the stack 132 may be made of a conductive material such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. And the dielectric layer 133 and the conductive layer 134 may be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The number of stacked dielectric layers 133 and conductive layers 134 may be 8, 32, 64, 128, etc., and the greater the number of stacked dielectric layers 133 and conductive layers 134, the higher the integration of the memory cell. Conductive layer 134 can serve as a word line for the memory cells in memory string structure 131.

In some embodiments, a plurality of memory string structures 131 (e.g., 131-1, 131-2, 131-3, 131-4) may be arranged two-dimensionally in a plane parallel to semiconductor layer 136. Each memory string structure 131 may include a plurality of memory cells arranged in one dimension in a direction perpendicular to the semiconductor layer 136, such that the memory cells are arranged in three dimensions in a space corresponding to the semiconductor layer 136. The memory string structure 131 is disposed through the stacked structure 132 and extends in a direction of the semiconductor layer 136. The memory string structure 131 may have a general shape of a cylinder, a cone, a rectangular parallelepiped, and may include an outer wall structure of the memory layer 1311 and the channel layer 1312 arranged in this order from the outside to the inside. Alternatively, the portion of the memory string structure 131 where the channel layer 1312 extends to the semiconductor layer 136 may be in contact with the semiconductor layer 136 to generate electrical coupling. Alternatively, the channel layer 1312 and the semiconductor layer 136 may be electrically coupled by an epitaxial layer (not shown) of the memory string structure 131 near the semiconductor layer 136.

It should be appreciated that where the plurality of memory string structures 131 are electrically coupled in common with the semiconductor layer 136, the N-type doped semiconductor layer 136 can be used to enable performing a GIDL erase operation for memory cells in the plurality of memory string structures 131. It is noted that semiconductor layer 136 may also comprise a semiconductor material having a uniform doping concentration of a P-type dopant. The P-type doped semiconductor layer 136 can be used to enable performing P-well bulk erase operations for memory cells in the plurality of memory string structures 131.

In some embodiments, the storage layer 1311 may be a composite layer structure of a blocking layer, a charge trapping layer, and a tunneling layer. The materials of the blocking layer, the charge trapping layer and the tunneling layer may be silicon oxide, silicon nitride and silicon oxide in sequence, thereby forming the memory layer 1311 having an ONO structure. The material of the channel layer 1312 may be a semiconductor material such as amorphous silicon, polycrystalline silicon, or single crystal silicon. The memory string structure 131 may be formed through a photolithography and etching process and a thin film deposition process.

It is understood that the portions of the memory layer 1311 and the channel layer 1312 corresponding to each conductive layer 134 in the memory string structure 131 and the conductive layer 134 together form a memory cell. The conductive layer may correspond to a control terminal of the memory cell. A plurality of memory cells in the memory string structure 131 are arranged in series in a direction perpendicular to the semiconductor layer 136 and share the channel layer 1312.

In some embodiments, the memory string structure 131 may further include a channel plug 135 located at an end of the memory string structure 131 remote from the semiconductor layer 136. The channel plug 135 may be made of the same semiconductor material as the channel layer 1312 and be in contact with the channel layer 1312. The channel plug 135 may function as a drain of the memory string structure 131.

In some embodiments, the step structure is disposed at an edge region of the stacked structure 132, and may be formed by performing a plurality of "trim-etch" cycles on the plurality of dielectric layers 133 and the plurality of conductive layers 134, which are alternately stacked. Wherein the exposed conductive layer 134 of the stepped structure in a direction parallel to the semiconductor layer 136 may serve as an electrical connection contact area for a conductive via (not shown). Since the conductive layer 134 can be used as a word line of a memory cell in the memory string structure 131, the conductive layer 134 can be connected to a plurality of peripheral devices in a peripheral circuit through a conductive channel to control the memory cell to perform functions of storing and reading data.

As shown in fig. 1 and 2, the deep trench isolation structure 140 includes a first portion 141 and a second portion 142. The first portion 141 may extend through the substrate 110 and/or the semiconductor layer 136 in the vicinity of the interface of the substrate 110 and the semiconductor layer 136 to electrically isolate the semiconductor layer 136 from the substrate 110. Since the first portion 141 of the deep trench isolation structure 140 completely penetrates through the substrate 110 and/or the semiconductor layer 136, interactions between peripheral devices and memory cells in the memory string structure 131 during, for example, an erase operation performed by the semiconductor layer 136 can be avoided, so that a three-dimensional memory formed using the memory string structure and peripheral device arrangement described above can be made compatible with GIDL and/or P-well bulk erase operations. Similarly, the second portion 142 extends completely through the substrate 100 and is disposed around the well 121 to create electrical isolation between the plurality of peripheral devices 120.

In some embodiments, the deep trench isolation structures 140 may be formed by patterning the substrate 110 and/or the semiconductor layer 136 by photolithography and etching processes, filling with an insulating material, and a mechanical chemical polishing (CMP) process. The insulating material for the deep trench isolation structure 140 may include silicon oxide, silicon nitride, silicon oxynitride, low temperature oxide, high temperature oxide, or any combination thereof. And the insulating material may be filled using a process such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation or any combination thereof.

Fig. 3 is a cross-sectional view of a peripheral device of a conventional three-dimensional memory. As shown in fig. 3. In the prior art, in the case of using a P-type substrate 1 as a carrier for forming a peripheral device 3, a Shallow Trench Isolation (STI)2 is generally used to achieve electrical isolation of the peripheral device 3 on the P-type substrate 1. For example, in case the peripheral device 3 is a high voltage N-type MOSFET, in order to provide electrical isolation of the peripheral device 3 from the P-type substrate 1, a deep N-well 6 may be formed below the high voltage P-well 4, such that PN junctions are formed between the high voltage P-well 4 and the deep N-well 6 and between the deep N-well 6 and the P-type substrate 1. The depth of the shallow trench isolation structure 2 is usually 3000-4000A, and the shallow trench isolation structure extends into the high voltage P-well 4 in the direction of the P-type substrate 1, in order to provide electrical isolation between adjacent peripheral devices 3, the concentration of dopant ions can be increased in a region 5 of the high voltage P-well 4 below the shallow trench isolation structure 2 between the adjacent peripheral devices 3, so as to increase the leakage voltage between the adjacent peripheral devices 3, and thus complete electrical isolation between the adjacent peripheral devices 3 is realized.

However, in the prior art, the isolation technology is used to solve the technical problem of complete isolation between peripheral devices, and the complexity of peripheral device fabrication is increased due to the need to cooperate with various isolation structures such as deep N-wells, shallow trench isolation structures, and regions with high doping concentration. Meanwhile, the number and types of masks used to form structures such as deep N-wells, shallow trench isolation structures, and high doping concentration regions may be increased, thereby increasing manufacturing costs. In addition, due to the addition of the deep N-well structure, the substrate depth required by the peripheral device is increased, which affects the performance of the finally formed peripheral device. On the other hand, in the case where the substrate for forming the peripheral device is brought into contact with the semiconductor layer for forming the memory string structure, the isolation effect of the shallow trench isolation structure also causes the peripheral device and the memory cell in the memory string structure to affect each other when, for example, an erase operation is performed.

According to the three-dimensional memory, the deep trench isolation structure is used for providing electrical isolation among the plurality of peripheral devices and the plurality of memory string structures, so that the formation of structures such as a deep N well and a high-doping-concentration region can be avoided, the isolation structure and the preparation process thereof can be simplified, and the manufacturing cost can be reduced. Meanwhile, the substrate depth required by the peripheral device can be reduced, so that the performance of the peripheral device is improved. The deep trench isolation structure divides each peripheral device into relatively independent devices, so that the punch-through problem (punch-through) between the peripheral devices can be avoided. In addition, since the deep trench isolation structure has relatively good isolation effect, the mutual influence between the peripheral device and the plurality of memory string structures can be weakened or even avoided.

In some embodiments, as shown in fig. 1 and 2, the deep trench isolation structure 140 may extend from a second side of the substrate 110 and/or the semiconductor layer 136, where the peripheral device 120 is not formed, to an opposite first side, and through the substrate 110 and/or the semiconductor layer 136. In this embodiment, the deep trench isolation structure 140 can be referred to as a "Backside Deep Trench Isolation (BDTI) structure" because the deep trench isolation structure is formed extending from the backside (second side) of the substrate 110 to the first side. The critical dimension of the deep trench isolation structure 140 at the first surface 101 may be smaller than the critical dimension at the second surface 102, so that the separation distance between adjacent peripheral devices can be reduced on the premise of realizing complete isolation of the adjacent peripheral devices, thereby increasing the integration level of the peripheral devices.

In some embodiments, the three-dimensional memory 10 may further include a back-end-of-line interconnect (BEOL) layer 160. The beol interconnect layer 160 is on a second side of the substrate 110 and/or the semiconductor 136 and is in contact with the second surface 102. Back-end-of-line interconnect layer 160 is used to implement pad-out to route electrical signals of peripheral device 120 and/or memory string structure 131. The back-end-of-line interconnect layer 160 may include through contacts (not shown) electrically connected to at least a portion of the peripheral devices 120 and/or the memory string structure 131, and dielectric isolation between the through contacts. Wherein the material of the through contact may comprise a conductive material of tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. The material of the dielectric isolation may comprise a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. Optionally, the deep trench isolation structure 140 may extend through the dielectric isolation structure in the back-end-of-line interconnect layer 160 from the second side of the substrate 110 and/or the semiconductor layer 136 and be formed simultaneously with the through contact, thereby making the process for preparing the deep trench isolation structure compatible with the process for preparing the back-end-of-line interconnect layer 160. It is to be understood that the above description is of the structure of the first semiconductor device 100 in the three-dimensional memory 10. In some embodiments, the three-dimensional memory 10 may further include a second semiconductor device 200. The second semiconductor device 200 is located on a side remote from the substrate 110 and is bonded to the first semiconductor device 100. The second semiconductor device 200 may include a plurality of peripheral devices formed therein. The plurality of peripheral devices in the second semiconductor device 200 may be combined with the plurality of peripheral devices in the first semiconductor device 100 to form a digital, analog, and/or digital-analog hybrid circuit module that implements various functions. Illustratively, the circuit module may include a page buffer, an address decoder, and a read amplifier. Alternatively, the first semiconductor device 100 may be used to form a high voltage MOS device and the second semiconductor device 200 may be used to form a low voltage MOS device and/or an ultra low voltage MOS device. The arrangement mode is favorable for the process compatibility of the high-voltage MOS device and the storage string structure in the preparation process.

Fig. 4 is a cross-sectional schematic view of a three-dimensional memory 10' according to another embodiment of the present application. FIG. 5 is a schematic top view of a portion of a three-dimensional memory 10' according to another embodiment of the present application. Among them, the peripheral devices 120-2 and 120-3 shown in fig. 4 may be a cross-sectional structure along a section line BB' in fig. 5. As shown in fig. 4 and 5, in this embodiment, the three-dimensional memory 10' further includes a shallow trench isolation structure 150, as compared to the three-dimensional memory 10. Since other structures in the three-dimensional memory 10' are identical to those of the three-dimensional memory 10, and the same reference numerals are used to refer to the same structures, the description of the present application is omitted.

In some embodiments, the shallow trench isolation structure 150 may be located between the well 121 and the deep trench isolation structure 141 and disposed around the well 121. The shallow trench isolation structure 150 extends in the substrate 110 and through a portion of the substrate 110. The shallow trench isolation structure 150 is disposed around the well 121 (active region) of the peripheral device 120, and is used to optimize the fillet in the process of forming the active region of the peripheral device 120, so as to prevent the peripheral device 120 from affecting the performance of the peripheral device due to the fillet of the active region. The shallow trench isolation structure 150 may be formed by patterning the substrate 110 through photolithography and etching processes, filling an insulating material, and a mechanochemical polishing process. The insulating material for the shallow trench isolation structure 150 may include silicon oxide, silicon nitride, silicon oxynitride, low temperature oxide, high temperature oxide, or any combination thereof. And the insulating material may be filled using a process such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation or any combination thereof. The shallow trench isolation 150 has a critical dimension gradually decreasing in a direction away from the first surface 101.

In some embodiments, the shallow trench isolation structure 150 may be formed extending from the first side of the substrate 110 on which the peripheral device 120 is formed to the second side. It is noted that, in this embodiment, since the shallow trench isolation structure 150 is used to optimize the corner rounding during the process of forming the active region of the peripheral device 120, the depth of the shallow trench isolation structure 150 extending from the first side to the second side is smaller than the depth of the conventional shallow trench isolation structure 3000-4000A. Optionally, in the embodiment of the present application, the depth of the shallow trench isolation structure 150 is about 1000A. In addition, the shallow trench isolation structure 150 may be formed simultaneously during the process of forming the peripheral device 120.

Fig. 6 is a partially enlarged view of the three-dimensional memory 10' shown in fig. 4. As shown in fig. 6, in some embodiments, there is a predetermined distance l, e.g., less than 150nm, between the shallow trench isolation structure 150 and the deep trench isolation structure 140 at the first surface 101. The shallow trench isolation structure and the deep trench isolation structure are spaced at a preset distance, so that the shallow trench isolation structure and the subsequently formed deep trench isolation structure can be prevented from being influenced mutually.

In some embodiments, as shown in fig. 6, the critical dimension s of the shallow trench isolation structure 150 at the first surface 101 is smaller than the critical dimension d of the deep trench isolation structure 140. Illustratively, the critical dimension s of the shallow trench isolation structure 150 may be 50nm, and the critical dimension d of the deep trench isolation structure 140 may be 200 nm. The key size of the shallow trench isolation structure is smaller than that of the deep trench isolation structure, so that a sufficient process window can be provided for the subsequently formed deep trench isolation structure, and the shallow trench isolation structure and the deep trench isolation structure are prevented from being influenced with each other.

Fig. 7 is a flowchart of a method 1000 of fabricating a three-dimensional memory according to an embodiment of the present application. Fig. 8A to 8E are schematic process cross-sectional views illustrating a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present disclosure. Method 1000 of fabricating a three-dimensional memory is used to form a three-dimensional memory of any of the implementations described above. As shown in fig. 7, the preparation method 1000 may include steps S110 to S140. It should be understood that the steps shown in method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 7.

A plurality of peripheral devices are formed in a first region of a substrate in step S110, a portion of the peripheral devices being located in wells of the substrate, as shown in fig. 8A, the substrate 110 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium, silicon-on-insulator, germanium-on-insulator, gallium arsenide, gallium nitride, silicon carbide, glass, III-V compound semiconductor, or any combination thereof.

In some embodiments, the process thereof is described in detail with reference to forming P-type and/or N-type MOSFETs as an example. Ion implantation and activation annealing processes may be used to incorporate N-type dopants, such as phosphorus, arsenic, antimony, or any combination thereof, into the N-well 121-2 formed in the substrate 110 and/or P-type dopants, such as boron, into the P-well 121-3 formed in the substrate 110.

In some embodiments, the substrate 110 may be patterned, filled with an insulating material, and subjected to a mechanochemical polishing process using a photolithography and etching process to form a shallow trench isolation structure 150 surrounding the well 141 (active region) of the peripheral device 120 on the substrate 110. The material of the shallow trench isolation structure 150 may include a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, low temperature oxide, high temperature oxide, and any combination thereof.

In some embodiments, the MOSFET structure, such as the gate stack layer 122, the isolation sidewall 123, the source/drain 124, and the lightly doped drain region 125, may be formed by photolithography and etching processes, thin film deposition processes such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation, and doping processes such as ion implantation. Since the structure and formation process of the peripheral device 120 are described in detail above, the present application is not repeated herein.

It should be understood that the peripheral device 120 is not limited to a MOSFET. The structures of other peripheral devices (e.g., diodes, resistors, inductors, BJTs, etc.) may be formed simultaneously during the process of making the MOSFET by different mask designs and layouts.

A plurality of memory string structures are formed in a second region of the substrate in step S120. As shown in fig. 8B, in some embodiments, this step may further include: the stacked-layer structure 132 is formed on the second area a2 of the substrate 110. Specifically, the dielectric layers 133 and the sacrificial layers (not shown) that are alternately stacked may be formed using a thin film deposition process such as CVD, PVD, ALD, sputtering, and any combination thereof. Dielectric layer 133 and the sacrificial layer may have different etch selectivity and the sacrificial layer may be removed and replaced with a conductive material during subsequent processing to form conductive layer 134. Illustratively, the material of the dielectric layer 133 may include silicon oxide, and the material of the sacrificial layer may include silicon nitride. It should be understood that although the present application employs an implementation in which the sacrificial layer is subsequently replaced with a conductive material to form a conductive layer, the implementation in which the conductive layer is formed in the present application is not limited thereto, and may also be implemented, for example, in a manner in which dielectric layers and conductive layers are directly alternately stacked.

In some embodiments, a step structure may be formed at an edge region of the stacked structure 132 corresponding to the second region a2 by performing a plurality of "trim-etch" cycles to the plurality of dielectric layers 133 and the plurality of sacrificial layers, which are alternately stacked.

In some embodiments, the plurality of memory string structures 131 may be formed within the stacked structure 132 using, for example, a dry or wet etching process and a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Specifically, openings extending into substrate 110 may be formed within stacked structure 132 using, for example, a dry or wet etch process. Further, a memory layer 1311 including a blocking layer, a charge trapping layer, and a tunneling layer, and a channel layer 1312 may be sequentially formed in the opening using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Illustratively, the materials of the blocking layer, the charge trapping layer, and the tunneling layer within the memory layer 1311 may include silicon oxide, silicon nitride, and silicon oxide, in that order. The material of the channel layer 1312 may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon, and any combination thereof.

In some embodiments, a gate gap extending into the substrate 110 may be formed within the stacked structure 132 using, for example, a dry or wet etch process, and the gate gap may extend in the x-direction of the substrate 110. Further, all of the sacrificial layer may be removed using, for example, a wet etching process to form a plurality of sacrificial gaps, using the gate slits as a passage for an etchant. Further, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be employed to form conductive layer 134 within the sacrificial gap. Alternatively, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form the isolation layer in the gate gap before refilling the conductive material such as tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide, or any combination thereof, to form the gate gap structure 137, which is a common source electrical connection structure for the plurality of memory string structures 131. Wherein the material of the isolation layer may include a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

It is understood that the above-described process steps may be a method of forming the first semiconductor device 100. The second semiconductor device 200 may be formed using any known process and may be processed in parallel with the first semiconductor device 100 to improve production efficiency. Since the structure of the second semiconductor device 200 is described above, the present application is not described in detail herein. The following steps may be subsequent processing of the first semiconductor device 100 after the first semiconductor device 100 and the second semiconductor device 200 are bonded.

In step S130, a portion of the substrate corresponding to the second region is removed, and a semiconductor layer electrically coupled to the plurality of memory string structures is formed, a portion of the substrate 110 corresponding to the second region a2 may be removed from a side of the substrate 110 where the memory string structures 131 are not formed, using, for example, a dry or wet etching process, to expose the memory string structures 131 extending into the substrate 110. Further, the same process may be employed to remove the memory layer 1311 of the exposed portion of the memory string structure 131 to further expose the functional layer 1312 of the memory string structure 131. Further, the semiconductor layer 136 may be formed within the second region a2 where the substrate 110 is not removed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to cover the memory string structure 131 and to contact the channel layer 1312 and the semiconductor layer 136 of the memory string structure 131. Semiconductor layer 136 may be of the same or different semiconductor material as substrate 110, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, and the like. Semiconductor layer 136 may be used to form a plurality of memory string structures 131 to perform assisted body biasing for GIDL and/or P-well erase operations.

In some embodiments, after forming semiconductor layer 136, semiconductor layer 136 and substrate 110 may be thinned using a CMP process. Optionally, substrate 110 and semiconductor layer 136 may be thinned to the thickness of well 121. In other words, after thinning the substrate 110 and the semiconductor layer 136, the substrate 110 can be made to correspond to the well 121 in the thickness direction.

Alternatively, as shown in fig. 8C, in step S130, during the process of removing a portion of the substrate 110 corresponding to the second region a2 from the side of the substrate 110' where the memory string structure 131 is not formed to expose the memory string structure 131 extending into the substrate 110, a portion of the substrate 110 corresponding to the first region a1 may be removed using the same process method to expose the well 121. In other words, the process of removing a portion of the substrate 110 corresponding to the first region a1 may make the thickness of the portion of the substrate 110 corresponding to the first region a1 the same as the thickness of the well 121. Further, as shown in fig. 8D, during the process of forming the semiconductor layer 136 in the second region a2 where the substrate 110 is not removed to cover the memory string structure 131 and to contact the channel layer 1312 of the memory string structure 131 and the semiconductor layer 136, the thickness of the semiconductor layer 136 and the well 121 may be made the same by the process parameters, that is, the thickness of the remaining portion of the substrate 110 corresponding to the first region a 1.

Forming a deep trench isolation structure in step S140, wherein the deep trench isolation structure comprises: a first portion extending through the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; a second portion extending through the substrate and surrounding the well to electrically isolate peripheral devices, as shown in fig. 8E, which may include, in some embodiments: the beol interconnect layer 160 is formed first. Specifically, the semiconductor structure formed after the above process may be turned over to perform subsequent processing on the backside of the substrate 110. A dielectric fill layer may be formed on the second side of the substrate 110 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and the material of the dielectric fill layer may include a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. Further, a photolithography and etching process and a thin film deposition process may be used to form through contacts electrically connected to at least a portion of the peripheral devices 120 and/or the plurality of memory string structures 131. The material of the through contact may comprise a conductive material of tungsten, cobalt, copper, aluminum, silicide, or any combination thereof.

Further, the same process may be used to form the deep trench isolation structure 140 extending from the second side of the substrate 110 to the opposite first side and sequentially penetrating the beol interconnect layer 160 and the substrate 110 and/or the semiconductor layer 136 while forming the through contact. Since the deep trench isolation structure 140 is formed extending from the back (second side) of the substrate 110 toward the first side, the deep trench isolation structure can be referred to as a "back deep trench isolation structure". Specifically, the deep trench isolation structure 140 may penetrate through the dielectric isolation in the beol interconnect layer 160 from the second side of the substrate 110 and be formed simultaneously with the penetrating contact, thereby making the fabrication process of the deep trench isolation structure 140 compatible with the fabrication process of the beol interconnect layer 160. In addition, the critical dimension of the deep trench isolation structure 140 at the first surface 101 may be smaller than the critical dimension at the second surface 102, so that the spacing distance between adjacent peripheral devices can be reduced on the premise of realizing complete isolation of the adjacent peripheral devices, thereby increasing the integration level of the peripheral devices and facilitating the miniaturization of the three-dimensional memory. According to the preparation method of the three-dimensional memory, the deep trench isolation structure is used for providing electrical isolation among the plurality of peripheral devices and between the peripheral devices and the memory string structure, so that the formation of structures such as a deep N well and a high-doping-concentration region can be avoided, the isolation structure and the preparation process thereof can be simplified, and the manufacturing cost can be reduced. Meanwhile, the substrate depth required by the peripheral device can be reduced, so that the performance of the peripheral device is improved. The deep trench isolation structure divides the peripheral devices into relatively independent devices, so that the problem of punch-through among the peripheral devices can be avoided. In addition, since the deep trench isolation structure has a relatively good isolation effect, the mutual influence between the peripheral device and the memory string structure can be weakened or even avoided.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.