阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 雒曲 谢文浩 于 2020-05-18 设计创作，主要内容包括：本发明提供一种半导体结构及其形成方法。方法包括：提供半导体衬底,半导体衬底具有多个独立的有源区,有源区通过浅沟槽隔离区隔离；刻蚀有源区及浅沟槽隔离区以形成沟槽,沟槽包括第一沟槽和第二沟槽,第一沟槽位于有源区中,第二沟槽位于浅沟槽隔离区中,第一沟槽的宽度大于第二沟槽的宽度；在沟槽中形成字线,字线包括第一字线和第二字线,第一字线位于第一沟槽中,第二字线位于第二沟槽中,第一字线的宽度大于第二字线的宽度。第二字线与其相邻的有源区之间的浅沟槽隔离区的厚度足够大,在第二字线通电工作时,第二字线在有源区感应的反型层的厚度很小或者没有,不足以形成寄生晶体管结构,不会形成漏电流,大大提高了半导体器件的存储性能。(The invention provides a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of independent active regions, and the active regions are isolated through shallow trench isolation regions; etching the active region and the shallow trench isolation region to form a trench, wherein the trench comprises a first trench and a second trench, the first trench is positioned in the active region, the second trench is positioned in the shallow trench isolation region, and the width of the first trench is greater than that of the second trench; and forming word lines in the grooves, wherein the word lines comprise a first word line and a second word line, the first word line is positioned in the first groove, the second word line is positioned in the second groove, and the width of the first word line is greater than that of the second word line. The thickness of the shallow trench isolation region between the second word line and the adjacent active region is large enough, when the second word line is electrified to work, the thickness of an inversion layer induced by the second word line in the active region is small or not enough to form a parasitic transistor structure, leakage current cannot be formed, and the storage performance of the semiconductor device is greatly improved.)

1. A method for forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of independent active regions which are isolated by shallow trench isolation regions;

etching the active region and the shallow trench isolation region to form a trench, wherein the trench comprises a first trench and a second trench, the first trench is located in the active region, the second trench is located in the shallow trench isolation region, and the width of the first trench is greater than that of the second trench;

forming word lines in the trenches, the word lines including a first word line and a second word line, the first word line being located in the first trench, the second word line being located in the second trench, the first word line having a width greater than a width of the second word line.

2. The method as claimed in claim 1, wherein in the step of etching the active region and the shallow trench isolation region to form the trench, an etching rate of an etching substance to the shallow trench isolation region is lower than an etching rate to the active region, so that a width of the first trench is greater than a width of the second trench.

3. The method of claim 2, wherein the shallow trench isolation region is a silicon dioxide isolation region, the active region is a silicon active region, and the etching the active region and the shallow trench isolation region to form the trench comprises:

forming a mask layer and a light resistance layer on the semiconductor substrate;

patterning the photoresist layer to form a window;

etching the mask layer along the window to expose the silicon active region and the silicon dioxide isolation region;

by Cl₂、HBr、CF₄And CHF₃As a gas source, etching the active region and the silicon dioxide isolation region for the first time by adopting a plasma process for a plurality of times;

using CF₄And CHF₃And as an air source, etching the active region and the shallow trench isolation region for a plurality of times by adopting a plasma process to form the first trench and the second trench.

4. The method according to claim 1, wherein a depth of the first trench is smaller than a depth of the second trench, and a distance from a bottom of the first word line to the surface of the semiconductor substrate is smaller than a distance from a bottom of the second word line to the surface of the semiconductor substrate.

5. The method as claimed in claim 1, further comprising, before the step of etching the active region and the shallow trench isolation region to form the trench: forming a sacrificial layer on the surface of the semiconductor substrate, wherein the sacrificial layer covers the active region and the shallow trench isolation region; and in the step of etching the active region and the shallow trench isolation region to form the trench, etching the sacrificial layer, the active region and the shallow trench isolation region to form the trench.

6. The method of claim 1, wherein the step of forming a word line in the trench further comprises:

sequentially forming a dielectric layer, an adhesion layer and a conductive layer in the groove, wherein the dielectric layer at least covers the inner surface of the groove, the adhesion layer at least covers the dielectric layer, and the conductive layer at least fills the groove;

and removing part of the adhesion layer and the conductive layer to form a word line, wherein the upper surface of the word line is lower than the surface of the substrate.

7. The method as claimed in claim 6, wherein a protective layer is filled after the step of forming the word line in the trench, the protective layer at least covering the word line.

8. A semiconductor structure formed using the semiconductor structure forming method according to any one of claims 1 to 7, wherein the semiconductor structure comprises:

a semiconductor substrate having a plurality of independent active regions, the active regions being isolated by shallow trench isolation regions;

the word line comprises a first word line and a second word line, the first word line is located in the active area, the second word line is located in the shallow trench isolation area, and the width of the first word line is larger than that of the second word line.

9. The semiconductor structure of claim 8, wherein a difference between a width of the first word line and a width of the second word line is 4-10 nm.

10. The semiconductor structure of claim 8, wherein the width of the first word line is 20-30nm, and the width of the second word line is 17-25 nm.

11. The semiconductor structure of claim 8, wherein a distance from a bottom of the first word line to the surface of the semiconductor substrate is less than a distance from a bottom of the second word line to the surface of the semiconductor substrate.

12. The semiconductor structure of claim 11, wherein a distance from a bottom of the first word line to the surface of the semiconductor substrate is 140 to 165nm, and a distance from a bottom of the second word line to the surface of the semiconductor substrate is 175 to 190 nm.

13. The semiconductor structure of claim 11, wherein the word line upper surface is lower than a surface of the semiconductor substrate.

14. The semiconductor structure of claim 13, wherein a distance from the upper surface of the word line to the surface of the semiconductor substrate is 60 to 75 nm.

15. The semiconductor structure of claim 8, wherein the word line comprises a dielectric layer, an adhesion layer, and a conductive layer disposed in sequence.

16. The semiconductor structure of claim 15, wherein an upper surface of the adhesion layer is lower than an upper surface of the conductive layer.

17. The semiconductor structure of claim 8, further comprising a protective layer covering at least the word line.

18. The semiconductor structure as claimed in claim 8, wherein the depth of the first word line is 65-105nm, and the depth of the second word line is 100-130 nm; the width of the first word line is 20-30nm, and the width of the second word line is 17-25 nm.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof.

Background

Semiconductor devices are increasingly used in integrated circuits, for example, dynamic random access memories are a type of semiconductor memory widely used in integrated circuits. As the feature size of semiconductor integrated circuit devices is continuously reduced, the semiconductor devices are also continuously developed to a high integration level, thereby providing more serious challenges to the semiconductor manufacturing technology.

As the integration degree of the semiconductor device is continuously increased, the semiconductor device may generate a leakage current, which may affect the memory performance of the semiconductor device.

Therefore, how to effectively reduce the leakage current and improve the memory performance of the semiconductor device is a technical problem to be solved urgently.

Disclosure of Invention

The present invention provides a semiconductor structure and a method for forming the same, which can reduce the leakage current of the semiconductor structure and improve the memory performance of the semiconductor device.

In order to solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of independent active regions which are isolated by shallow trench isolation regions; etching the active region and the shallow trench isolation region to form a trench, wherein the trench comprises a first trench and a second trench, the first trench is located in the active region, the second trench is located in the shallow trench isolation region, and the width of the first trench is greater than that of the second trench; forming word lines in the trenches, the word lines including a first word line and a second word line, the first word line being located in the first trench, the second word line being located in the second trench, the first word line having a width greater than a width of the second word line.

Further, in the step of etching the active region and the shallow trench isolation region to form the trench, an etching rate of an etching substance to the shallow trench isolation region is smaller than an etching rate to the active region, so that the width of the first trench is larger than the width of the second trench.

Further, the depth of the first trench is smaller than that of the second trench, and the distance from the bottom of the first word line to the surface of the semiconductor substrate is smaller than that from the bottom of the second word line to the surface of the semiconductor substrate.

Further, before the step of etching the active region and the shallow trench isolation region to form the trench, the method further includes: forming a sacrificial layer on the surface of the semiconductor substrate, wherein the sacrificial layer covers the active region and the shallow trench isolation region; and in the step of etching the active region and the shallow trench isolation region to form the trench, etching the sacrificial layer, the active region and the shallow trench isolation region to form the trench.

Further, the step of forming a word line in the trench further includes: sequentially forming a dielectric layer, an adhesion layer and a conductive layer in the groove, wherein the dielectric layer at least covers the inner surface of the groove, the adhesion layer at least covers the dielectric layer, and the conductive layer at least fills the groove; and removing part of the adhesion layer and the conductive layer to form a word line, wherein the upper surface of the word line is lower than the surface of the substrate.

Further, after the step of forming the word line in the trench, a protective layer is filled, the protective layer at least covering the word line.

In order to solve the above technical problem, the present invention further provides a semiconductor structure formed by the above semiconductor structure forming method, the semiconductor structure including: a semiconductor substrate having a plurality of independent active regions, the active regions being isolated by shallow trench isolation regions; the word line comprises a first word line and a second word line, the first word line is located in the active area, the second word line is located in the shallow trench isolation area, and the width of the first word line is larger than that of the second word line.

Further, the difference between the width of the first word line and the width of the second word line is 4 to 10 nm.

Furthermore, the width of the first word line is 20-30nm, and the width of the second word line is 17-25 nm.

Further, the distance from the bottom of the first word line to the surface of the semiconductor substrate is smaller than the distance from the bottom of the second word line to the surface of the semiconductor substrate.

Further, the distance from the bottom of the first word line to the surface of the semiconductor substrate is 140-165 nm, and the distance from the bottom of the second word line to the surface of the semiconductor substrate is 175-190 nm.

Further, the upper surface of the word line is lower than the surface of the semiconductor substrate.

Further, the distance from the upper surface of the word line to the surface of the semiconductor substrate is 60 to 75 nm.

Furthermore, the word line comprises a dielectric layer, an adhesion layer and a conductive layer which are arranged in sequence.

Further, the upper surface of the adhesion layer is lower than the upper surface of the conductive layer.

Further, the semiconductor structure further comprises a protective layer, and the protective layer at least covers the word line.

Further, the depth of the first word line is 65-105nm, and the depth of the second word line is 100-130 nm; the width of the first word line is 20-30nm, and the width of the second word line is 17-25 nm.

The semiconductor structure formed by the semiconductor structure forming method has the advantages that the thickness of the shallow trench isolation region between the second word line and the adjacent active region is large enough, so that when the second word line is electrified to work, the thickness of an inversion layer induced by the second word line in the active region is small or not enough to form a parasitic transistor structure, further, leakage current cannot be formed, and the storage performance of a semiconductor device is greatly improved.

Drawings

FIG. 1 is a schematic step diagram illustrating a method of forming a semiconductor structure according to one embodiment of the present invention;

FIGS. 2A-2N are process flow diagrams of one embodiment of a method of forming a semiconductor structure of the present invention;

FIGS. 3A and 3B are schematic structural diagrams illustrating a semiconductor structure according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another embodiment of a semiconductor structure in accordance with the present invention.

Detailed Description

The following detailed description of the semiconductor structure and the method for forming the same according to the present invention will be made with reference to the accompanying drawings.

As the integration degree of the semiconductor device is continuously increased, the semiconductor device may generate a leakage current. The inventors have found that the reason for the generation of the leakage current is that a parasitic transistor structure is formed in the semiconductor structure. The parasitic transistor structure may form a leakage current in the semiconductor device.

The inventors further found that, in the semiconductor structure, the buried Word Line (WL) may simultaneously pass through the active region (AA) and the Shallow Trench Isolation (STI), and the buried word line of the shallow trench isolation may induce an inversion layer in the active region adjacent to the buried word line during operation, thereby forming a parasitic transistor structure, and thus generating a leakage current.

Therefore, the present invention provides a method for forming a semiconductor structure and a semiconductor structure, which can prevent a parasitic transistor structure from being formed, thereby preventing a leakage current from being generated in the semiconductor structure.

Fig. 1 is a schematic step diagram of a method for forming a semiconductor structure according to an embodiment of the present invention, and referring to fig. 1, the method for forming a semiconductor structure according to the present invention includes the following steps: step S10, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of independent active regions which are isolated by shallow trench isolation regions; step S11, etching the active area and the shallow trench isolation area to form a trench, wherein the trench comprises a first trench and a second trench; the first groove is positioned in the active region, the second groove is positioned in the shallow groove isolation region, and the width of the first groove is greater than that of the second groove; step S12, forming word lines in the trenches, where the word lines include a first word line and a second word line, the first word line is located in the first trench, the second word line is located in the second trench, and a width of the first word line is greater than a width of the second word line.

Fig. 2A to 2N are process flow diagrams of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to step S10, fig. 2A and fig. 2B, wherein fig. 2A is a top view and fig. 2B is a schematic cross-sectional view taken along line a-a in fig. 2A, a semiconductor substrate having a plurality of independent active regions 201 is provided, and the active regions 201 are isolated by shallow trench isolation regions 202.

The material of the semiconductor substrate may be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the semiconductor substrate material is silicon. The semiconductor substrate is doped with certain impurity ions according to needs, and the impurity ions can be N-shaped impurity ions or P-shaped impurity ions. In an embodiment, the doping includes well region doping and source drain region doping.

The invention provides a forming method of the active region 201, which comprises the following steps: a plurality of shallow trenches are formed in the semiconductor substrate by adopting a photoetching method; the shallow trench isolation region 202 is formed by filling an isolation material in the shallow trench, where the isolation material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable isolation materials. In this embodiment, the isolation material is silicon oxide. The active region 201 is a semiconductor substrate isolated by the shallow trench isolation region 202. In this embodiment, as shown in fig. 2A, the active regions 201 extend along the direction B1, and the positions of the active regions 201 in adjacent rows may have a certain offset.

In this embodiment, when the shallow trench is filled with an isolation material, the isolation material also covers the upper surface of the semiconductor substrate, that is, the upper surface of the active region 201 also covers the isolation material. In fig. 2A, since the active region 201 is shielded by the isolation material, it is illustrated with a dotted line. In another embodiment of the present invention, after filling the isolation material in the shallow trench, the isolation material on the upper surface of the semiconductor substrate is removed, and only the isolation material in the shallow trench is remained; or when the shallow trench is filled with the isolation material, only the shallow trench is filled with the isolation material, and the upper surface of the semiconductor substrate is not covered with the isolation material.

Optionally, the following steps are included after step S10: referring to step S100 and fig. 2C, a sacrificial layer 210 is formed on the surface of the semiconductor substrate, wherein the sacrificial layer 210 covers the active region 201 and the shallow trench isolation region 202. The material of the sacrificial layer 210 includes one or more of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, single crystal silicon, and carbon.

Referring to step S11 and fig. 2D to fig. 2I, the active region 201 and the shallow trench isolation region 202 are etched to form a trench 203, where the trench 203 includes a first trench 203A and a second trench 203B, the first trench 203A is located in the active region 201, the second trench 203B is located in the shallow trench isolation region 202, and a width of the first trench 203A is greater than a width of the second trench 203B.

In this embodiment, since the surface of the semiconductor substrate further has the sacrificial layer 210, the sacrificial layer 210 is also etched correspondingly to form the trench 203 when step S11 is performed.

In this step, the trench 203 may be formed by photolithography and etching processes. During etching, the widths of the first trench 203A and the second trench 203B are controlled by changing the etching rate of the etching substance to the shallow trench isolation region 202 and the active region 201, that is, the etching selection ratio of the etching substance to the shallow trench isolation region 202 and the active region 201 is controlled to control the widths of the first trench 203A and the second trench 203B. Specifically, the etching rate of the etching substance to the shallow trench isolation region 202 is smaller than that to the active region 201, so that the width of the first trench 203A is larger than that of the second trench 203B.

A specific embodiment of the method for forming the trench is described below. In this embodiment, the shallow trench isolation 202 is a silicon dioxide isolation, and the active region 201 is a silicon active region. The forming method of the groove comprises the following steps:

referring to fig. 2D, a mask layer 220 and a photoresist layer 230 are formed on the sacrificial layer 210, wherein the mask layer 220 may be a single layer or a plurality of layers, and in this embodiment, the mask layer 220 includes a carbon layer 221 and a substrate layer 222 sequentially disposed.

Referring to fig. 2E, the photoresist layer 230 is patterned to form a window 231. Specifically, in this step, the photoresist layer 230 is patterned by ashing.

Referring to fig. 2F, the mask layer 220 is etched along the window 231 to expose the sacrificial layer 210. In this step, HBr and CF can be used₄Removing the SION layer 222 as an etching gas; o is₂、SO₂And Ar gas is used as an etching gas to remove the carbon layer 221.

Referring to fig. 2G, the sacrificial layer 210 is continuously etched to expose the active region and the shallow trench isolation region. In this step, CF may be used₄、CH₂F₂And He gas is used as etching gas to remove the sacrificial layer 210 so as to expose the active region and the shallow trench isolation region.

Please refer to fig. 2H, using Cl₂、HBr、CF₄And CHF3 is used as a gas source, and the active region 201 and the shallow trench isolation region 202 are etched for the first time by adopting a plasma process for a plurality of times. In this step, the Cl₂、HBr、CF₄And CHF₃The etching rate for silicon is greater than that for silicon dioxide, so in this step, the etching parameters, such as etching time, can be controlled to preliminarily form the first trench 203A having a set width. It will be appreciated that the shallow trench isolation regions will also be etched during this step, but in much less amount than silicon.

The photoresist layer 230 and the mask layer 220 are gradually etched and removed in the etching process, and if the photoresist layer 230 and the mask layer 220 are not completely removed before the step of forming the first trench 203A shown in fig. 2H, the photoresist layer 230 and the mask layer 220 are removed by ashing, etching, and the like.

Referring to FIG. 2I and FIG. 2J, FIG. 2I is a top view, and FIG. 2J is a schematic cross-sectional view taken along line A-A of FIG. 2I and using CF₄And CHF₃And as a gas source, performing secondary etching on the active region 201 and the shallow trench isolation region 202 for a certain time by using a plasma process. In this step, CF₄And CHF₃The etching rate for silicon dioxide is greater than that for silicon, so in this step, the etching parameters, such as etching time, can be controlled to form the second trench 203B with a set width. It will be appreciated that the active area 201 will also continue to be etched during this step, but in much less amount than silicon dioxide.

Further, a byproduct cleaning step is also included after etching. For example, with O₂The first trench 203A and the second trench 203B are acted upon for a certain time to clean the byproducts.

The width W1 of the first trench 203A formed by the above method is larger than the width W2 of the second trench 203B. It will be appreciated that other methods of forming the trenches may be used by those skilled in the art. Since the width W1 of the first trench 203A is greater than the width W2 of the second trench 203B, the widths of the subsequently formed first word line and the second word line are also different.

Further, the width W1 of the first trench 203A is 20 to 30nm, the width W2 of the second trench 203B is 17 to 25nm, and the difference between the width W1 of the first trench 203A and the width W2 of the second trench 203B is 4 to 10 nm. If the size of the second trench 203B is too small, the width of a second word line 270B (shown in fig. 2L) subsequently formed in the second trench 203B is too small, which may result in large word line resistance and slow transistor turn-on.

Further, in the present embodiment, the depth D1 of the first trench 203A is smaller than the depth D2 of the second trench 203B, so that the depths of the subsequently formed first word line and the second word line are different.

Referring to step S12, a word line is formed in the trench 203. The word lines comprise a first word line and a second word line, the first word line is located in the first groove, the second word line is located in the second groove, and the width of the first word line is larger than that of the second word line.

The following is a description of a method of forming a word line.

Referring to fig. 2K, a dielectric layer 240, an adhesion layer 250 and a conductive layer 260 are sequentially formed in the trench 203, wherein the dielectric layer 240 at least covers the inner surface of the trench 203, the adhesion layer 250 at least covers the dielectric layer 240, and the conductive layer 260 at least fills the trench 203. In this embodiment, the dielectric layer 240 and the adhesion layer 250 are formed only in the trench 203, and in other embodiments of the present invention, the dielectric layer 240 and the adhesion layer 250 are also formed on the upper surface of the sacrificial layer 210 in sequence due to the influence of the manufacturing process; before the conductive layer 260 is formed, the dielectric layer 240 and the adhesion layer 250 on the surface of the sacrificial layer 210 are removed. In this embodiment, the conductive layer 260 also covers the upper surface of the sacrificial layer 210.

The dielectric layer 240 may be an oxide layer, which may be used as a gate oxide layer. The dielectric layer 240 may be formed using an In-Situ Steam Generation (ISSG) process. It can be understood that, if the dielectric layer 240 is formed by an in-situ water vapor generation process, since the material of the shallow trench isolation region 202 cannot be oxidized, the dielectric layer 240 is formed only in the first trench 203A of the active region 201, and the dielectric layer 240 is not formed in the second trench 203B of the shallow trench isolation region 202; if the dielectric layer 240 is formed by deposition or the like, the dielectric layer 240 can be formed in both the first trench 203A and the second trench 203B.

The adhesion layer 250 may be a titanium nitride layer, and the conductive layer 260 may be a tungsten metal layer.

Referring to fig. 2L and 2M, wherein fig. 2L is a top view and fig. 2M is a cross-sectional view taken along a line a-a in fig. 2L, a portion of the adhesion layer 250 and the conductive layer 260 are removed to form a word line 270, and an upper surface of the word line 270 is lower than a surface of the semiconductor substrate. In this step, the conductive layer 260 is etched to a predetermined height, and then a portion of the adhesion layer 250 not covered by the conductive layer 260 is removed to form a word line 270, wherein a first word line 270A is formed in the first trench 203A and a second word line 270B is formed in the second trench 203B. Since the dielectric layer 240 and the adhesion layer 250 have small thicknesses, the dielectric layer 240 and the adhesion layer 250 are not shown in fig. 2K in order to avoid overlapping lines in the drawing. It is understood that dielectric layer 240 is also partially removed or thinned as the etching process proceeds during this step.

Further, in the formed word line structure, the upper surface of the adhesion layer 250 is lower than the upper surface of the conductive layer 260, so as to reduce the gidl (gate index Drain) effect.

Referring to fig. 2M, since the width W1 of the first trench 203A is greater than the width W2 of the second trench 203B, the width C1 of the first word line 270A is greater than the width C2 of the second word line 270B. The thickness H of the shallow trench isolation region 202 between the second word line 270B and the adjacent active region 201 is large enough, so that when the second word line 270B is powered on to work, the thickness of an inversion layer induced by the second word line 270B in the active region 201 is small or zero, which is not enough to form a parasitic transistor structure, and further, no leakage current is formed, and the storage performance of the semiconductor device is greatly improved. In the prior art, the first word line and the second word line have the same width, and when the second word line is powered on to work, the thickness of an inversion layer induced by the second word line in an active region adjacent to the second word line is large, so that a parasitic transistor structure can be formed, and leakage current can be formed.

Further, since the depth D1 of the first trench 203A is smaller than the depth D2 of the second trench 203B, the distance H1 from the bottom of the first word line 270A to the surface of the semiconductor substrate is smaller than the distance H2 from the bottom of the second word line 270B to the surface of the semiconductor substrate, so as to form a fin structure, increase the channel width, and improve the performance of a transistor of a subsequently formed semiconductor device. Further, the distance H1 from the bottom of the first word line 270A to the surface of the semiconductor substrate is 140-165 nm, and the distance H2 from the bottom of the second word line 270B to the surface of the semiconductor substrate is 175-190 nm.

Further, the upper surfaces of the first word line 270A and the second word line 270B are flush, and a distance H3 from the upper surfaces of the first word line 270A and the second word line 270B to the surface of the semiconductor substrate is 60-75 nm. Further, after step S12, the method further includes the following steps: referring to fig. 2N, a protection layer 280 is filled, and the protection layer 280 at least covers the word line 270 to prevent the conductive layer 260 from being oxidized. The protection layer 280 may be a SiN layer. In this embodiment, the protection layer 280 also covers the surface of the sacrificial layer 210.

The invention also provides a semiconductor structure formed by the preparation method. Fig. 3A and 3B are schematic structural diagrams of a semiconductor structure according to an embodiment of the present invention, wherein fig. 3A is a top view, and fig. 3B is a schematic cross-sectional view taken along a-a line in fig. 3A, referring to fig. 3A and 3B, the semiconductor structure includes a semiconductor substrate and a word line 370.

The semiconductor substrate has a plurality of independent active regions 301, and the active regions 301 are isolated by shallow trench isolation regions 302.

The word lines 370 include a first word line 370A and a second word line 370B, the first word line 370A is located in the active region 301, and the second word line 370B is located in the shallow trench isolation region 302. The width C1 of the first word line 370A is greater than the width C2 of the second word line 370B. Further, the width C1 of the first word line 370A is 20 to 30nm, the width C2 of the second word line 370B is 17 to 25nm, and the difference between the width of the first word line 370A and the width of the second word line 370B is 4 to 10 nm. If the width of the second word line 370B is too small, the resistance of the word line is increased and the transistor is turned on slowly.

Further, the distance H1 from the bottom of the first word line 370A to the surface of the semiconductor substrate is smaller than the distance H2 from the bottom of the second word line 370B to the surface of the semiconductor substrate, so as to form a fin structure, increase the channel width, and improve the performance of a transistor of a subsequently formed semiconductor device. Further, the distance H1 from the bottom of the first word line 370A to the surface of the semiconductor substrate is 140-165 nm, and the distance H2 from the bottom of the second word line 370B to the surface of the semiconductor substrate is 175-190 nm.

Further, the first word line 370A is flush with the upper surface of the second word line 370B, and a distance H3 from the upper surfaces of the first word line 370A and the second word line 370B to the surface of the semiconductor substrate is 60-75 nm.

Fig. 4 is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention, referring to fig. 4, in which the semiconductor structure further includes a protection layer 380, and the protection layer 380 at least covers the word line 370.

In the present invention, the thickness H of the shallow trench isolation region 302 between the second word line 370B and the adjacent active region 301 is sufficiently large, so that when the second word line 370B is powered on to work, the thickness of the inversion layer induced by the second word line 370B in the active region 301 is small or not enough to form a parasitic transistor structure, and thus, no leakage current is formed, and the memory performance of the semiconductor device is greatly improved.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.