阅读说明：本技术 一种基于rram的高效可重构环形振荡器puf电路 (Efficient reconfigurable ring oscillator PUF circuit based on RRAM ) 是由 崔益军 黎江 刘伟强 王成华 于 2021-10-27 设计创作，主要内容包括：本发明公开了一种基于RRAM的高效可重构环形振荡器PUF电路,包括墒源电路和响应产生电路；第一激励作为地址输入给行解码器,以选择至少一个行作为环形振荡器的馈电输入,同时使能相应的WL线；第二激励作为地址输入给列选择器和写驱动电路,选择前述每个导通行中任意数量列的RRAM参与到熵源的提取中去；响应产生电路用于放大RRAM Crossbar阵列输出的随机熵源,并最终表现为环形振荡器的振荡频率的变化,再通过比较同一个环形振荡器在不同周期的振荡频率或者不同环形振荡器在同一个周期的振荡频率以产生唯一的响应值。本发明拥有良好的均匀性、唯一性和可靠性,可配置性强,大大缩小了电路面积。(The invention discloses a high-efficiency reconfigurable ring oscillator PUF circuit based on RRAM, which comprises a moisture source circuit and a response generation circuit; a first stimulus is applied as an address input to the row decoder to select at least one row as a feed input to the ring oscillator while enabling the corresponding WL line; inputting the second excitation as an address to a column selector and a write driving circuit, and selecting any number of columns of RRAMs in each conducting row to participate in the extraction of the entropy source; the response generation circuit is used for amplifying a random entropy source output by the RRAM Crossbar array, and finally expressing the change of the oscillation frequency of the ring oscillator, and generating a unique response value by comparing the oscillation frequency of the same ring oscillator in different periods or the oscillation frequency of different ring oscillators in the same period. The invention has good uniformity, uniqueness and reliability, strong configurability and greatly reduced circuit area.)

1. A high-efficiency reconfigurable ring oscillator (PUF) circuit based on RRAM, the PUF circuit comprising an earth moisture source circuit and a response generation circuit;

the response generating circuit comprises at least one ring oscillator; the moisture source circuit comprises a column selector, a write driving circuit, an RRAM Crossbar array and a row decoder; the RRAM Crossbar array comprises three circuit control lines, namely a Row line Row, a column line Col and an enabling signal line WL; the enabling signal line WL is used for enabling the NMOS tube to control whether the 1T1R cells of the corresponding row are conducted or not; the row lines and column lines are used to select different rows and corresponding RRAM paths to achieve the configurability of the PUF;

in a response generation phase, a first stimulus is input to the row decoder as an address to select at least one row as a feed input to the ring oscillator while enabling the corresponding WL line; inputting the second excitation as an address to a column selector and a write driving circuit, and selecting any number of RRAM columns in each conducting row to participate in the extraction of the entropy source; wherein, RRAM in each row is parallel state, and the final resistance is the parallel value of all selected RRAM;

the column selector and the write driving circuit apply power supply voltage to RRAMs of corresponding rows in the RRAM Crossbar array, and the RRAMs are connected with the drain electrode of a PMOS (P-channel metal oxide semiconductor) of the ring oscillator circuit through a row decoder so as to apply the generated random moisture source to the power supply end of the ring oscillator;

the response generation circuit is used for amplifying a random entropy source output by the RRAM Crossbar array, and finally expressing the change of the oscillation frequency of the ring oscillator, and generating a unique response value by comparing the oscillation frequency of the same ring oscillator in different periods or the oscillation frequency of different ring oscillators in the same period.

2. The RRAM-based high-efficiency reconfigurable ring oscillator (PUF) circuit of claim 1, wherein the response generation circuit includes N ring oscillators, N counters, and 1 comparator;

the power supply ends of the N ring oscillators are connected with the N row decoders in a one-to-one correspondence mode, the output ends of the N ring oscillators are connected with the input ends of corresponding counters, and the output ends of the counters are connected to the comparator;

and N is a positive integer greater than or equal to 2.

3. The RRAM-based high-efficiency reconfigurable ring oscillator (PUF) circuit of claim 1, wherein the response generation circuit includes M ring oscillators and M comparison circuits;

each comparison circuit comprises a counter, a register and a comparator; the power supply ends of the M ring oscillators are connected with the M row decoders in a one-to-one correspondence mode, and the output ends of the M ring oscillators are connected with the input ends of the counters of the corresponding comparison circuits; the output end of the counter is divided into two paths, wherein one path is directly connected to the comparator, and the other path is connected to the comparator through the register;

and M is a positive integer greater than or equal to 1.

4. The RRAM-based high-efficiency reconfigurable ring oscillator (PUF) circuit of any one of claims 1-3, wherein the ring oscillator is comprised of an 8-stage CMOS inverter and a 1-stage nand gate;

all PMOS in CMOS inverter are connected with RRAM Crossbar array, and pass through NAND gateEnableEnabling signals to control whether the ring oscillator circuit generates oscillation;

one input end and one output end of the NAND gate are connected with each inverter end to end; the other input end of the NAND gate is used as a control signal, the ring oscillator is enabled to oscillate when authentication is needed, and the NAND gate is configured to output a stable signal when the operation is not needed, so that the ring oscillator module is in a stable state and does not oscillate any more.

5. A method of operating a RRAM-based high-efficiency reconfigurable ring oscillator (PUF) circuit according to any one of claims 1 to 3, the method comprising the steps of:

step one, Reset stage: before the PUF circuit deployment work, performing Reset operation on the PUF circuit to set the PUF circuit as a PUF example; the method comprises the following steps:

setting the size of an RRAM Crossbar array as B multiplied by B; opening all WL lines, driving all column lines and row lines, inputting pulse voltage exceeding RRAM reverse threshold to all column lines, and resetting RRAM to HRS;

step two, excitation configuration stage:

inputting A + B bit excitation, equally dividing the A bit excitation into x signal selections, enabling all WL lines, selecting a row channel of a corresponding row, simultaneously inputting the A bit excitation to a row decoder, switching on row lines of the x rows, and suspending unselected row lines; enabling the corresponding column line by adopting other B-bit excitation, and supplying power to the column line of the bit if the excitation is 1; the column line of the bit is suspended when the excitation is '0';

step three, response generation stage:

after input excitation, in a gated row, RRAMs corresponding to opened column lines participate in feeding of RO modules, and the RRAMs in the row are all in parallel state, and the final resistance is the parallel value of all selected RRAMs; then the voltage input into the ring oscillator is changed due to the difference between the RRAM resistance devices, and finally the output is the difference of the oscillation frequency of the ring oscillator; the oscillation frequencies of the same ring oscillator in different periods or the oscillation frequencies of different ring oscillators in the same period are compared by a comparator to generate a unique 1-bit response value.

6. The method of operating a RRAM-based high-efficiency reconfigurable ring oscillator (PUF) circuit according to claim 5, further comprising the steps of:

step four, a PUF refreshing stage:

when the number of CRPs generated by the PUF circuit exceeds a threshold value of machine learning successful modeling, refreshing the PUF circuit, resetting the PUF circuit to be a new PUF instance, and enabling the model to be invalid and not being capable of successfully predicting the generation of response; the refresh operation includes:

and opening all WL lines, driving all column lines and row lines, inputting pulse voltage exceeding the forward threshold of the RRAM to all the column lines, setting the RRAM to be LRS, and then executing the Reset phase of the first step again to enable the HRS resistance value of all the RRAMs to be changed due to the change of the RRAM period.

Technical Field

The invention relates to the technical field of hardware security, in particular to a high-efficiency reconfigurable ring oscillator PUF circuit based on RRAM and a working method thereof.

Background

The rapid development of the internet of things causes more attention to hardware security problems. The ubiquitous terminal devices of the internet of things such as wearable devices, household appliances and various sensors provide more attack opportunities for enemies to terminal nodes. In a traditional software encryption mode, a secret key needs to be stored in a nonvolatile memory, a complex encryption algorithm is provided, the traditional software encryption mode is easily attacked by physical attacks such as side channel attacks, and the password can be cracked through information such as energy consumption, running time and electromagnetic radiation in the encryption algorithm implementation process. In addition, because the internet of things device generally works in a scene with limited resources, the traditional software encryption algorithm is not suitable for the internet of things node with limited area and power consumption. Therefore, a Physical Unclonable Function (PUF) is favored by researchers as a low-power, lightweight hardware security encryption primitive. PUFs can extract random errors introduced by integrated circuit chips (ICs) during manufacturing due to temperature, voltage, process, etc., as keys, and can be used for device authentication and for generation of cryptographic keys. When a stimulus is input to the PUF after the system is powered on (Challenge), the PUF extracts the inherent physical entropy in the chip to generate a unique Response value (Response), and the same stimulus is input to the same PUF structure of different chips, and the Response values are different, so that the stimulus Response pairs (CRPs) can be used as security certificates of hardware circuit devices.

PUFs can be classified into strong PUFs and weak PUFs according to the functional relationship between the number of CRPs and the basic unit of the PUF. The number of CRPs of a strong PUF grows exponentially with the increase of the number of elementary units of the PUF, while the number of CRPs of a weak PUF is a linear or polynomial function of the number of elementary units. Classical strong PUF architectures include reconfigurable ring oscillator PUF (cro PUF) and arbiter PUF (apuf). The reconfigurable ring oscillator PUF is formed by connecting odd inverters in series to form a Ring Oscillator (RO), oscillation frequencies generated by different ROs are different due to fixed process errors in the inverters, different ROs are selected by a selector to be output, and finally the frequencies of two paths of collected signals are compared by a comparator, so that an unpredictable response value of 1 bit is generated. Whether a strong PUF or a weak PUF, once an adversary is able to predict its CRPs with high accuracy, they are no longer secure. Although the PUF can resist physical attacks to a certain extent, modeling attacks based on powerful machine learning algorithms such as Logistic Regression (LR) and covariance matrix adaptive evolution strategy (CMA-ES) can model the strong PUF with higher mathematical precision, and CRPs can be predicted to a certain extent. While weak PUFs do not discuss their modeling attacks because of the limited CRP space. The traditional CRO PUF is simple in structure and easy to model, and the prediction rate of response of machine learning attack on the traditional CRO PUF can reach over 90%.

CMOS technology is limited by the trend of process scaling, resulting in CMOS-based PUF structures that face bottlenecks in area and power consumption. RRAM is widely used as a new PUF design primitive as a new entropy source due to its advantages of low power consumption, high density, and compatibility with CMOS technology. RRAM has two resistance states, a High Resistance State (HRS) and a Low Resistance State (LRS), and can be switched between these two resistance states by applying appropriate forward and reverse voltages, and can be used as a new design primitive for PUFs due to process variations between RRAM devices and between cycles. Therefore, a high-security reconfigurable PUF design based on RRAM needs to be found out urgently, and the high-reconfigurability is utilized to reduce the circuit area, so that the reconfigurable PUF is used in an application scene of the limited resources of the internet of things.

The invention with the patent number of CN109495272A proposes a strong PUF circuit based on a memristor, which uses 2T2R as a basic unit, generates a unique response value by comparing currents of two columns of paths, has the characteristics of high area utilization rate, configurability and reutilization, and has excellent randomness and modeling attack resistance. However, the strong PUF circuit needs to adopt the nonvolatile memory array and the 2T2R basic unit at the same time, and still needs to occupy a large area; the current comparison mode has higher requirement on the precision of a reading circuit; meanwhile, the anti-attack capability of the model is realized only through strong randomness, and machine learning attack cannot be avoided completely in fact.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides the high-efficiency reconfigurable ring oscillator PUF circuit based on the RRAM, which has good uniformity, uniqueness and reliability, strong configurability and greatly reduced circuit area; in addition, based on the periodic change of the RRAM, the invention provides a reset mechanism of the RCRO PUF design, after a certain number of stimulus response pairs (CRP) are used, the PUF can be reset to a new PUF example, the device utilization rate of the RRAM is improved, the safety of the PUF to modeling attack is enhanced, and the method is suitable for application scenarios in which authentication information needs to be updated when the ownership of equipment is transferred.

In order to achieve the purpose, the invention adopts the following technical scheme:

a RRAM-based high-efficiency reconfigurable ring oscillator (PUF) circuit comprising an entropy source circuit and a response generation circuit;

the response generating circuit comprises at least one ring oscillator; the moisture source circuit comprises a column selector, a write driving circuit, an RRAM Crossbar array and a row decoder; the RRAM Crossbar array comprises three circuit control lines, namely a Row line Row, a column line Col and an enabling signal line WL; the enabling signal line WL is used for enabling the NMOS tube to control whether the 1T1R cells of the corresponding row are conducted or not; the row lines and column lines are used to select different rows and corresponding RRAM paths to achieve the configurability of the PUF;

in a response generation phase, a first stimulus is input to the row decoder as an address to select at least one row as a feed input to the ring oscillator while enabling the corresponding WL line; inputting the second excitation as an address to a column selector and a write driving circuit, and selecting any number of RRAM columns in each conducting row to participate in the extraction of the entropy source; wherein, RRAM in each row is parallel state, and the final resistance is the parallel value of all selected RRAM;

the column selector and the write driving circuit apply power supply voltage to RRAMs of corresponding rows in the RRAM Crossbar array, and the RRAMs are connected with the drain electrode of a PMOS (P-channel metal oxide semiconductor) of the ring oscillator circuit through a row decoder so as to apply the generated random moisture source to the power supply end of the ring oscillator;

the response generation circuit is used for amplifying a random entropy source output by the RRAM Crossbar array, and finally expressing the change of the oscillation frequency of the ring oscillator, and generating a unique response value by comparing the oscillation frequency of the same ring oscillator in different periods or the oscillation frequency of different ring oscillators in the same period.

In order to optimize the technical scheme, the specific measures adopted further comprise:

further, the response generation circuit includes N ring oscillators, N counters, and 1 comparator;

the power supply ends of the N ring oscillators are connected with the N row decoders in a one-to-one correspondence mode, the output ends of the N ring oscillators are connected with the input ends of corresponding counters, and the output ends of the counters are connected to the comparator;

and N is a positive integer greater than or equal to 2.

Further, the response generation circuit includes M ring oscillators and M comparison circuits;

each comparison circuit comprises a counter, a register and a comparator; the power supply ends of the M ring oscillators are connected with the M row decoders in a one-to-one correspondence mode, and the output ends of the M ring oscillators are connected with the input ends of the counters of the corresponding comparison circuits; the output end of the counter is divided into two paths, wherein one path is directly connected to the comparator, and the other path is connected to the comparator through the register;

and M is a positive integer greater than or equal to 1.

Further, the ring oscillator is composed of an 8-stage CMOS inverter and a 1-stage NAND gate;

all PMOS in CMOS inverter are connected with RRAM Crossbar array, and pass through NAND gateEnableEnabling signals to control whether the ring oscillator circuit generates oscillation;

one input end and one output end of the NAND gate are connected with each inverter end to end; the other input end of the NAND gate is used as a control signal, the ring oscillator is enabled to oscillate when authentication is needed, and the NAND gate is configured to output a stable signal when the operation is not needed, so that the ring oscillator module is in a stable state and does not oscillate any more.

The invention also provides a working method of the high-efficiency reconfigurable ring oscillator PUF circuit based on the RRAM, and the working method comprises the following steps:

step one, Reset stage: before the PUF circuit deployment work, performing Reset operation on the PUF circuit to set the PUF circuit as a PUF example; the method comprises the following steps:

setting the size of an RRAM Crossbar array as B multiplied by B; opening all WL lines, driving all column lines and row lines, inputting pulse voltage exceeding RRAM reverse threshold to all column lines, and resetting RRAM to HRS;

step two, excitation configuration stage:

inputting A + B bit excitation, equally dividing the A bit excitation into x signal selections, enabling all WL lines, selecting a row channel of a corresponding row, simultaneously inputting the A bit excitation to a row decoder, switching on row lines of the x rows, and suspending unselected row lines; enabling the corresponding column line by adopting other B-bit excitation, and supplying power to the column line of the bit if the excitation is 1; the column line of the bit is suspended when the excitation is '0';

step three, response generation stage:

after input excitation, in a gated row, RRAMs corresponding to opened column lines participate in feeding of RO modules, and the RRAMs in the row are all in parallel state, and the final resistance is the parallel value of all selected RRAMs; then the voltage input into the ring oscillator is changed due to the difference between the RRAM resistance devices, and finally the output is the difference of the oscillation frequency of the ring oscillator; the oscillation frequencies of the same ring oscillator in different periods or the oscillation frequencies of different ring oscillators in the same period are compared by a comparator to generate a unique 1-bit response value.

Further, the working method further comprises the following steps:

step four, a PUF refreshing stage:

when the number of CRPs generated by the PUF circuit exceeds a threshold value of machine learning successful modeling, refreshing the PUF circuit, resetting the PUF circuit to be a new PUF instance, and enabling the model to be invalid and not being capable of successfully predicting the generation of response; the refresh operation includes:

and opening all WL lines, driving all column lines and row lines, inputting pulse voltage exceeding the forward threshold of the RRAM to all the column lines, setting the RRAM to be LRS, and then executing the Reset phase of the first step again to enable the HRS resistance value of all the RRAMs to be changed due to the change of the RRAM period.

The invention has the beneficial effects that:

(1) the invention utilizes the RRAM Crossbar array as the voltage control module of the ring oscillator, and the supply voltage of the ring oscillator changes due to the resistance difference between different devices of the RRAM and different periods, thereby controlling the oscillation frequency and efficiently generating PUF response.

(2) According to the invention, any number of RRAMs in two different rows can be selected as entropy sources through configuration, so that the method has good uniformity, uniqueness and reliability, and compared with the latest PUF design based on RRAM delay units, the PUF has strong configurability, and the circuit area is greatly reduced.

(3) The invention provides a comparison optimization design, which is characterized in that the output of two paths of ring oscillators is not compared in one period any more, but the oscillation frequency of the same path of signal is compared in two periods, so that the deviation of the oscillation frequency of an upper path and a lower path caused by the process error and noise jitter brought by a CMOS (complementary metal oxide semiconductor) tube in two different ring oscillators during comparison is reduced.

(4) In addition, based on the periodic change of the RRAM, the invention provides a reset mechanism of the RCRO PUF design, after a certain number of stimulus response pairs (CRP) are used, the PUF can be reset to a new PUF example, the device utilization rate of the RRAM is improved, the safety of the PUF to modeling attack is enhanced, and the method is suitable for application scenarios in which authentication information needs to be updated when the ownership of equipment is transferred.

Drawings

Figure 1 is a schematic diagram of a RRAM-based high-efficiency reconfigurable ring oscillator PUF circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a configuration strategy of an RCRO PUF according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of an optimized design of an RCRO PUF according to an embodiment of the present invention.

Detailed Description

The present invention will now be described in further detail with reference to the accompanying drawings.

It should be noted that the terms "upper", "lower", "left", "right", "front", "back", etc. used in the present invention are for clarity of description only, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not limited by the technical contents of the essential changes.

The general circuit design of the RRAM-based high-efficiency reconfigurable ring oscillator PUF (RCRO PUF) is shown in fig. 1, the basic unit of the RRAM-based high-efficiency reconfigurable ring oscillator PUF (RCRO PUF) is a 1T1R structure, and the RRAM-based high-efficiency reconfigurable ring oscillator PUF, the RCRO PUF and the RRAM-based high-efficiency reconfigurable ring oscillator PUF comprise a read-write module, a ring oscillator module and an output acquisition comparison module. The RRAM array is m × n and includes word lines WL. The WL line is used to turn on or off the NMOS of the corresponding row to gate the RRAM cell, and when a conductive path of a certain row is gated, the WL line of the row needs to be enabled correspondingly to prevent leakage current and the like from affecting the reliability of the PUF. The RO module comprises 8 inverters and 1 NAND gate which are connected end to end, and the NAND gate can control whether RO can generate oscillation or not through a control signal: when Enable = "1", RO may generate oscillation; when Enable = "0", then RO cannot oscillate. When the RRAM array feeds the RO, the RO begins to oscillate. Compared with the traditional CRO PUF, the design saves a large amount of inverter resources.

In the PUF basic unit, an entropy source circuit mainly comprises an NMOS-RRAM (1 resistor 1 RRAM, 1T 1R) Crossbar array circuit and a corresponding programming and reading circuit. The Crossbar array structure formed by the 1T1R cells realizes reconfigurable operation through a column selector, a row decoder and a WL enabling line. The 1T1R structure may make the proposed PUF implementation compatible with mainstream memory applications based on RRAM Crossbar arrays, and increase density to minimize circuit area. The 1T1R array includes three circuit control lines, Row line Row, column line Col and enable signal line WL, and accordingly, the excitation signal mainly includes three parts, the column selector, Row decoder and WL enable line and the oscillation enable signal of the ring oscillator. The NMOS transistor may be enabled by WL to control whether the 1T1R cell of the row is conducting. By opening the respective row and column lines, different rows and respective RRAM paths can be selected, thereby achieving configurability of the PUF.

The first stimulus is applied as an address input to the row decoder, two different rows are selected as the feed inputs to the two ring oscillators, while the corresponding WL lines need to be enabled, and then the second stimulus is applied as an address input to the column selector, and any number of RRAMs in the two rows can be selected to participate in the extraction of the entropy source. Due to resistance difference between RRAM devices, when two signals are input with the same voltage, the output current and the voltage of the power supply end of the ring oscillator generate slight difference, so that the oscillation frequency of the ring oscillator changes greatly. Due to flexible configuration and strong reconfigurability, a large number of excitation response pairs can be generated in circuits with the same area for equipment identity authentication.

The response generating circuit comprises a 9-stage ring oscillator circuit formed by connecting 8-stage inverters and 1-stage NAND gates end to end, one input end and one output end of each NAND gate are connected with the inverters end to end, the odd-level inversion structure can ensure the stability of oscillation, the other input end of each NAND gate is used as a control signal, and the ring oscillator is enabled to oscillate when authentication is needed; when the PUF does not work, the enabling signal can configure the NAND gate to output as a stable signal, so that the ring oscillator module is in a stable state and does not oscillate any more, and the power consumption of the PUF during the non-work is reduced. The ring oscillator circuit can amplify the random entropy source of the RRAM Crossbar array, ultimately appearing as a change in the oscillation frequency of the ring oscillator. And finally, a counter and a comparator circuit are included, the counter counts the oscillation frequency, and the comparator compares the frequency to generate a unique response value. Since the supply voltage first needs to pass through the 1T1R array and then the voltage is applied to the supply terminals of the ring oscillator, the supply voltage of the ring oscillator is relatively low, and the lower voltage can lower the oscillation frequency of the ring oscillator, thereby avoiding a large number of bits in the counter.

The working principle of the RRAM Crossbar array and the ring oscillator circuit is as follows: supply voltage is applied to the RRAM of the corresponding row in the 1T1R array through the column selector and the write driving circuit, and then the RRAM is connected with the drain of the ring oscillator circuit PMOS through the row decoder. The ring oscillator circuit comprises 8-stage inverters and 1-stage NAND gates, wherein PMOS in all CMOS logic gates are connected with RRAM Crossbar array, and pass through the NAND gatesEnableEnable signal, controllableCompared with the traditional reconfigurable ring oscillator PUF, the design only uses a 9-level reverse structure, saves a large amount of inverter resources and greatly reduces power consumption.

Since there are also process errors between the two ring oscillators, which may cause frequency offset, the final response value has poor uniformity, and the ring oscillators are susceptible to temperature, aging, and the like. In order to enhance the uniformity and stability of the response of the RO PUF, the invention also provides an optimized design capable of improving the uniformity and reliability of the RO PUF, and the optimized design compares the output of two paths of ring oscillators in one period, but compares the oscillation frequency of the same path of signals in two periods. The design is characterized in that a register module is added on the basis of the original RO PUF design to separate two ring oscillators, and a counter is connected with a comparator and a register at the same time. The register can store the oscillation frequency in the last period, and the oscillation frequency is compared with the oscillation frequency in the present period so as to reduce the deviation of the up-and-down oscillation frequency caused by the process error and the noise jitter brought by the CMOS tube in two different ring oscillators during comparison. Meanwhile, the design is not limited to two paths of signals any more, in order to increase the response speed of the PUF, the area can be sacrificed, a multi-path response extraction circuit is added, and a multi-bit response value is generated in one period.

Assuming that the RRAM array size of the RCRO PUF is 32 × 32 (1 k), the specific operation steps of the PUF to generate CRPs are:

1) and a Reset stage: before the PUF deployment works, it needs to be Reset to set it as a kind of PUF instance. All WL lines are turned on, all Col lines (column lines) and Row lines (Row lines) are driven, and a pulse voltage exceeding the reverse threshold of RRAM is input to all Col lines, with RRAM Reset to HRS. Because the RRAM of each row is finally connected in parallel to participate in the feeding of the RO, a higher resistance value is needed to ensure the reliability of the output;

2) and (3) excitation configuration stage: the 10-bit excitation is divided into two 5-bit signal selection and two WL lines are enabled, a Row path corresponding to two rows is selected, meanwhile, the 10-bit excitation is input to a Row decoder, and the Row lines of the two rows are connected. The unselected rows are left floating. In addition, 32-bit excitation enables the corresponding Col line, and if the excitation is '1', the Col line of the bit is powered; the actuation to "0" floats the Col line of the bit. Therefore, a stimulus of input 42 bit is required to produce a one-bit response value;

3) a response generation stage: after input excitation, in the gated Row, the RRAM corresponding to the opened Col line participates in the feeding of the RO module, and the RRAMs in the Row are all in parallel, so that the final resistance is the parallel value of all the selected RRAMs. Due to the device-to-device difference in the resistance of the RRAM, the voltage input to the RO varies, and the final output is a difference in the oscillation frequency of the RO. Comparing the magnitude of the two paths of RO oscillation frequencies through a comparator to generate a unique 1 bit response value;

4) and a PUF refreshing stage: when the number of CRPs generated by the PUF exceeds the threshold for successful modeling by machine learning, the PUF needs to be refreshed and reset to a new PUF instance, making its model invalid and unable to successfully predict the generation of a response. And a refresh operation, which is to open all WL lines, drive all Col lines and Row lines, input a pulse voltage exceeding the forward threshold of the RRAM to all Col lines, Set all RRAM to LRS, and then re-perform the Reset phase. Due to the change of the RRAM period, the HRS resistance values of all the RRAMs are changed, and the effect of resetting the PUF to resist the machine learning attack is achieved.

For the excitation of the RCRO PUF, the specific configuration scheme is shown in FIG. 2, the excitation bit length is 42 bits, 33-42 bits are Row selection bits, and every 5 bits correspond to the addresses of a Row line and a WL line, so that two transverse paths are gated. Because any number of RRAM can be selected to participate in the generation of the response in each row of the RCRO PUF, the first 32 bits stimulate a Col line for every 1 bit, and a "1" indicates that the RRAM for that column is enabled. Finally, all enabled RRAMs of the row feed the RO modules in the form of parallel resistors. In an m × n PUF array, any number of RRAMs may be selected per row, and thus the number of configurable pairs of stimulus responses per row is:

in m rows, any two rows of lanes can be selected for output at a time, so the overall configurable number of stimulus response pairs is:

the proposed RCRO PUF design increases the reconfigurability of the PUF, can generate a large number of excitation response pairs, and significantly improves the device utilization rate of the RRAM.

The invention also provides an optimized design, which can ignore the process error of the phase inverter in the RO, the specific design is shown in figure 3, and a register module is added in the original output design. RRAM_S1And RRAM_S2The oscillation frequency in this one cycle, i.e., the value of the counter, is stored by the added register module for the parallel resistance value of the selected two Row paths to be compared with the value in the next cycle. The PUF response is generated by comparing the oscillation frequencies of the two ROs, but by comparing the oscillation frequencies of the same RO twice, in this case, the generated frequency is based on the same RO, so that the self frequency difference between the two ROs can be avoided. Meanwhile, the oscillation frequency of the RO can be influenced by the aging of the phase inverter, the optimized design can avoid the influence of different aging degrees of the two ROs, and the reliability and the safety of the PUF are improved. Fig. 3 includes two independent response generating paths, which are identical in structure and operation, and the two paths are used to increase the response generating rate, but consume a larger area, so that a trade-off between area and rate is needed. Each Row of the open circuit can generate a response value through an output circuit of an independent circuit, so that the maximum bit response generated in each period is the number of rows of the RRAM array under the condition that the area allows. In the resource-limited equipment, only one output circuit can be adopted at least, and the circuit area is reduced.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.