阅读说明：本技术 一种薄膜晶体管的制备方法、薄膜晶体管及显示面板 (Preparation method of thin film transistor, thin film transistor and display panel ) 是由 雍玮娜 于 2021-08-02 设计创作，主要内容包括：本发明涉及一种薄膜晶体管的制备方法、薄膜晶体管及显示面板。本发明先在有源层远离栅极绝缘层的一侧的表面上依次制备第一金属层和第二金属层,然后对第一金属层和第二金属层进行图案化处理,然后采用电镀工艺在图案化处理后的第二金属层远离第一金属层的一侧的表面上制备第三金属层,第三金属层还覆盖于第二金属层的侧壁和第一金属层的侧壁上。采用电镀工艺制备第三金属层,第三金属层可以按照第二金属层的图案进行生长,避免对第三金属层进行图案化处理,进而避免现有技术中存在的源漏极层的蚀刻异常现象。利用第三金属层保护第二金属层,防止退火处理时第二金属层发生氧化,进而提升薄膜晶体管的电性性能,最终提升显示面板的显示效果。(The invention relates to a preparation method of a thin film transistor, the thin film transistor and a display panel. The method comprises the steps of firstly, sequentially preparing a first metal layer and a second metal layer on the surface of one side, far away from a grid electrode insulating layer, of an active layer, then carrying out patterning treatment on the first metal layer and the second metal layer, then preparing a third metal layer on the surface of one side, far away from the first metal layer, of the second metal layer after the patterning treatment by adopting an electroplating process, and covering the third metal layer on the side wall of the second metal layer and the side wall of the first metal layer. The third metal layer is prepared by adopting an electroplating process, can grow according to the pattern of the second metal layer, avoids patterning the third metal layer and further avoids the abnormal etching phenomenon of the source drain electrode layer in the prior art. The third metal layer is used for protecting the second metal layer, so that the second metal layer is prevented from being oxidized during annealing treatment, the electrical property of the thin film transistor is further improved, and the display effect of the display panel is finally improved.)

1. A preparation method of a thin film transistor is characterized by comprising the following steps:

providing a glass substrate, and sequentially preparing a grid layer, a grid insulating layer, an active layer and a source drain layer on the glass substrate;

the preparation method of the source drain layer comprises the following steps:

preparing a first metal layer on the surface of one side of the active layer away from the gate insulating layer;

preparing a second metal layer on the surface of one side of the first metal layer away from the active layer;

patterning the second metal layer and the first metal layer; and

and preparing a third metal layer on the surface of the patterned side of the second metal layer away from the first metal layer by adopting an electroplating process, wherein the third metal layer also covers the side wall of the second metal layer and the side wall of the first metal layer.

2. The method for manufacturing a thin film transistor according to claim 1, further comprising the steps of:

and annealing the glass substrate, the gate electrode layer, the gate insulating layer, the active layer and the source drain layer.

3. The method of claim 1, wherein the third metal layer is made of an inert metal.

4. The method for manufacturing a thin film transistor according to claim 3, wherein the inert metal comprises: mercury (Hg), silver (Ag), palladium (Pd), platinum (Pt), gold (Au), and titanium (Ti).

5. The method according to claim 1, wherein the active layer is made of an oxide.

6. The method according to claim 5, wherein the oxide comprises IGZO or ITZO.

7. The method of claim 1, wherein the first metal layer and the second metal layer are formed by physical vapor deposition.

8. A thin film transistor formed by the method for manufacturing a thin film transistor according to any one of claims 1 to 7.

9. A display panel comprising the thin film transistor according to claim 8.

10. The display panel according to claim 9, wherein the display panel is an LCD display panel or an OLED display panel.

Technical Field

The application relates to the technical field of display, in particular to a preparation method of a thin film transistor, the thin film transistor and a display panel.

Background

In the preparation process of the thin film transistor, the source and drain layers are used as conduction paths of all signals, and the performance of the source and drain layers has a crucial influence on the performance of the thin film transistor and further has a crucial influence on the display effect of the display panel. In order to improve the bonding force between the main conductive metal (such as copper) and other films, reduce the diffusion effect of the main conductive metal, and protect the main conductive metal from other conditions such as high temperature and moisture, the source/drain layer needs to be a double-layer structure or a three-layer structure.

At present, complex electrochemical reaction often occurs in the patterning etching process of the source drain layer, so that abnormal etching is caused. For example, because the corrosion potential of molybdenum is lower than that of copper, molybdenum can protect copper and preferentially corrode, the molybdenum on the top layer is in a state of protecting copper for a long time, the etching speed is high, and the molybdenum on the top layer is seriously damaged when a good Taper angle is not formed on the edge of the source drain electrode layer or the lower layer of metal molybdenum is not etched completely, so that a photoresist above the metal of the source drain electrode layer cannot be attached to the molybdenum on the top layer, the phenomenon of falling off occurs, and further, the large-area metal wire is abnormally etched.

At present, the etching solution in the patterning process of the source drain layer damages the active layer and needs to be repaired by annealing treatment, but because the molybdenum metal on the top layer is completely etched in the patterning etching process of the existing source drain layer, the exposed copper metal can be seriously oxidized in the annealing process, and then the performance of the thin film transistor is influenced, and the display effect of the display panel is finally influenced.

Disclosure of Invention

The invention aims to provide a preparation method of a thin film transistor, the thin film transistor and a display panel, which can solve the problems of abnormal etching and the like in the patterning etching process of a source drain layer of the conventional thin film transistor.

In order to solve the above problems, the present invention provides a method for manufacturing a thin film transistor, comprising the steps of: providing a glass substrate, and sequentially preparing a grid layer, a grid insulating layer, an active layer and a source drain layer on the glass substrate; the preparation method of the source drain layer comprises the following steps: preparing a first metal layer on the surface of one side of the active layer away from the gate insulating layer; preparing a second metal layer on the surface of one side of the first metal layer away from the active layer; patterning the second metal layer and the first metal layer; and preparing a third metal layer on the surface of the patterned side of the second metal layer away from the first metal layer by adopting an electroplating process, wherein the third metal layer also covers the side wall of the second metal layer and the side wall of the first metal layer.

Further, the preparation method of the thin film transistor further comprises the following steps: and annealing the glass substrate, the gate electrode layer, the gate insulating layer, the active layer and the source drain layer.

Furthermore, the third metal layer is made of inert metal.

Further, the inert metal includes: mercury (Hg), silver (Ag), palladium (Pd), platinum (Pt), gold (Au), and titanium (Ti).

Furthermore, the active layer is made of oxide.

Further, the oxide includes IGZO or ITZO.

Furthermore, the preparation processes of the first metal layer and the second metal layer are both physical vapor deposition processes.

In order to solve the above problems, the present invention provides a thin film transistor, which is formed by the method for manufacturing a thin film transistor according to the present invention.

In order to solve the above problems, the present invention provides a display panel including the thin film transistor according to the present invention.

Further, the display panel is an LCD display panel or an OLED display panel.

The invention has the advantages that: the method comprises the steps of firstly, sequentially preparing and forming a first metal layer and a second metal layer on the surface of one side, far away from a grid electrode insulating layer, of an active layer, then carrying out patterning treatment on the first metal layer and the second metal layer, then preparing a third metal layer on the surface of one side, far away from the first metal layer, of the second metal layer after patterning treatment by adopting an electroplating process, and covering the third metal layer on the side wall of the second metal layer and the side wall of the first metal layer. The third metal layer is prepared by adopting an electroplating process, can grow according to the pattern of the second metal layer, avoids patterning the third metal layer and further can avoid the abnormal etching phenomenon of the source drain electrode layer in the prior art. The third metal layer is used for protecting the second metal layer, so that the second metal layer is prevented from being oxidized during annealing treatment, the electrical property of the thin film transistor is further improved, and the display effect of the display panel is finally improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a thin film transistor according to the present invention;

FIG. 2 is a diagram of the steps for fabricating a thin film transistor according to the present invention;

FIG. 3 is a diagram of a fabrication step of a source drain layer of the present invention;

fig. 4 is a schematic illustration of the preparation of the third metal layer.

Description of reference numerals:

100. a thin film transistor;

1. a glass substrate; 2. A gate layer;

3. a gate insulating layer; 4. An active layer;

5. a source drain layer;

51. a first metal layer; 52. A second metal layer;

53. and a third metal layer.

Detailed Description

The following detailed description of the preferred embodiments of the present invention is provided to enable those skilled in the art to make and use the present invention in a complete manner, and is provided for illustration of the technical disclosure of the present invention so that the technical disclosure of the present invention will be more clearly understood and appreciated by those skilled in the art how to implement the present invention. The present invention may, however, be embodied in many different forms of embodiment, and the scope of the present invention should not be construed as limited to the embodiment set forth herein, but rather construed as being limited only by the following description of the embodiment.

The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc., are only directions in the drawings, and are used for explaining and explaining the present invention, but not for limiting the scope of the present invention.

In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for convenience of understanding and description, and the present invention is not limited to the size and thickness of each component.

The present embodiment provides a display panel. The display panel includes a thin film transistor 100. The display panel may be an LCD display panel or an OLED display panel. In this embodiment, the display panel is an LCD display panel.

As shown in fig. 1, the thin film transistor 100 includes: a glass substrate 1, a gate electrode layer 2, a gate insulating layer 3, an active layer 4, and a source drain layer 5.

Wherein the gate layer 2 is disposed on a surface of one side of the glass substrate 1. The material of the gate layer 2 is metal, such as copper (Cu) or molybdenum (Mo).

Wherein, the gate insulating layer 3 is disposed on a surface of the gate electrode layer 2 on a side away from the glass substrate 1. The gate insulating layer 3 is mainly used to prevent the short circuit phenomenon caused by the contact between the gate layer 2 and the active layer 4. The gate insulating layer 3 may be made of SiO₂And SiNx.

Wherein, the active layer 4 is arranged on the surface of one side of the gate insulating layer 3 far away from the glass substrate 1. In this embodiment, the active layer 4 is made of an oxide, such as IGZO or ITZO. In the prior art, the etching solution in the patterning process of the source/drain layer 5 has little influence on the active layer made of the a-Si material, and has a large damage to the active layer 4 made of the oxide material, so this embodiment mainly solves the problem that the etching solution in the patterning process of the source/drain layer 5 damages the active layer 4 made of the oxide material.

As shown in fig. 1, the source/drain layer 5 is disposed on a surface of the active layer 4 on a side away from the glass substrate 1. The source drain layer 5 includes: a first metal layer 51, a second metal layer 52, and a third metal layer 53.

Wherein, the first metal layer 51 is disposed on the surface of the active layer 4 on the side far away from the glass substrate 1. In this embodiment, the material of the first metal layer 51 is molybdenum (Mo).

The second metal layer 52 is disposed on a surface of the first metal layer 51 on a side away from the glass substrate 1. In this embodiment, the material of the second metal layer 52 is copper (Cu).

The third metal layer 53 is disposed on a surface of the second metal layer 52 on a side away from the glass substrate 1, and covers a sidewall of the second metal layer 52 and a sidewall of the first metal layer 51. The material of the third metal layer 53 is an inert metal. The inert metal includes: mercury (Hg), silver (Ag), palladium (Pd), platinum (Pt), gold (Au), and titanium (Ti).

The third metal layer 53 protects the second metal layer 52, so as to prevent the second metal layer 52 from being oxidized during the annealing process, thereby improving the electrical performance of the thin film transistor 100 and finally improving the display effect of the display panel.

As shown in fig. 2, this embodiment further provides a method for manufacturing the thin film transistor 100 according to this embodiment, which includes the following steps: s1, providing a glass substrate 1; s2, preparing a gate electrode layer 2 on a surface of one side of the glass substrate 1; s3, preparing a gate insulating layer 3 on a surface of the gate layer 2 on a side away from the glass substrate 1; s4, preparing an active layer 4 on the surface of the gate insulating layer 3 on the side away from the glass substrate 1; s5, preparing a source drain layer 5 on the surface of the active layer 4 on the side far away from the glass substrate 1; and S6, annealing the glass substrate 1, the gate electrode layer 2, the gate insulating layer 3, the active layer 4 and the source drain layer 5.

The damage of the etching solution to the active layer 4 during the patterning process of the first metal layer 51 and the second metal layer 52 is improved by the annealing process, and the electrical performance of the thin film transistor 100 is improved.

As shown in fig. 3, S5 specifically includes: s51, preparing a first metal layer 51 on the surface of the active layer 4 away from the gate insulating layer 3 by using a physical vapor deposition process; s52, preparing a second metal layer 52 on a surface of the first metal layer 51 on a side away from the active layer 4 by using a physical vapor deposition process; s53, patterning the second metal layer 52 and the first metal layer 51 by an exposure and development process; and S54, preparing a third metal layer 53 on the surface of the patterned side of the second metal layer 52 away from the first metal layer 51 by using an electroplating process, wherein the third metal layer 53 also covers the side wall of the second metal layer 52 and the side wall of the first metal layer 51.

As shown in fig. 4, the preparation step of the third metal layer 53 includes: the glass substrate 1, the gate electrode layer 2, the gate insulating layer 3, the active layer 4, the patterned first metal layer 51, and the patterned second metal layer 52 are entirely placed in an electrolytic cell 6. The electrolytic cell 6 includes an electrolyte containing metal ions 61 of the material of the third metal layer 53 to be produced. And applying voltage to the second metal layer 52 by using a peripheral wire, and growing the metal ions 61 according to the pattern of the second metal layer 52 to form the third metal layer 53.

The third metal layer 53 is prepared by an electroplating process, and the third metal layer 53 can grow according to the pattern of the second metal layer 52, so that patterning of the third metal layer 53 is avoided, and the abnormal etching phenomenon of the source drain layer 5 in the prior art can be further avoided.

The above detailed description is made on the method for manufacturing a thin film transistor, the thin film transistor, and the display panel, and the principle and the implementation of the present application are described herein by using specific examples, and the description of the above examples is only used to help understanding the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.