阅读说明：本技术 基于单片机实现1553b总线通信的方法及系统 (Method and system for realizing 1553B bus communication based on single chip microcomputer ) 是由 黄柳莺 张毅 范晓琳 李奕辉 于 2021-07-29 设计创作，主要内容包括：本发明提供了一种基于单片机实现1553B总线通信的方法及系统,包括单片机对1553B芯片读操作方法,包括先读高8位,设置MSB-LSBn＝‘1’,进行“哑读”操作,数据丢弃；等待一段时间；设置MSB-LSBn＝‘0’,读低地址,存入共用体RTdata的高字节RTdata.bytedata[1]；设置MSB-LSBn＝‘1’,读高地址,存入共用体的低字节RTdata.bytedata[0]；函数返回值是共用体的字RTdata.worddata。本发明克服单片机8位数据接口,与1553B 16位数据总线接口的矛盾,提高数据处理效率,并具有一定的灵活性。(The invention provides a method and a system for realizing 1553B bus communication based on a single chip microcomputer, which comprises a method for reading a 1553B chip by the single chip microcomputer, wherein the method comprises the steps of firstly reading 8 high bits, setting MSB _ LSBn to be 1 ', carrying out ' dummy reading ' operation and discarding data; waiting for a period of time; setting MSB _ LSBn as '0', reading a low address, and storing a high byte RTdata of a shared body RTdata [1 ]; setting MSB _ LSBn as '1', reading a high address, and storing a low byte RTdata of a shared body; the function return value is a common body word rtdata. The invention overcomes the contradiction between the 8-bit data interface of the singlechip and the 1553B 16-bit data bus interface, improves the data processing efficiency and has certain flexibility.)

1. A method for realizing 1553B bus communication based on a single chip microcomputer is characterized by comprising a method for reading a 1553B chip by the single chip microcomputer, wherein the method for reading the 1553B chip by the single chip microcomputer comprises the following steps:

step S1: firstly reading the upper 8 bits, setting MSB _ LSBn to be 1 ', performing ' dummy reading ' operation, and discarding data;

step S2: waiting for a period of time;

step S3: setting MSB _ LSBn as '0', reading a low address, and storing a high byte RTdata of a shared body RTdata [1 ];

step S4: setting MSB _ LSBn as '1', reading a high address, and storing a low byte RTdata of a shared body;

step S5: the function return value is a common body word rtdata.

2. The method for realizing 1553B bus communication based on the single chip microcomputer as claimed in claim 1, wherein the function in step S5 completes dummy read operation by accessing an external address, and after waiting for a period of time, reads high and low bytes respectively and stores the high and low bytes in RTdata of a shared body; the get byte operation starts with a low address and deposits the fetched bytes from high to low.

3. The method for realizing 1553B bus communication based on the single-chip microcomputer according to claim 1, wherein the method for realizing 1553B bus communication based on the single-chip microcomputer further comprises a data block pointer method for obtaining an instruction stack, and the data block pointer method for the instruction stack comprises the following steps:

step 1: reading a pointer of an instruction stack;

step 2: comparing a pointer of the instruction stack to a defined variable;

and step 3: judging whether the compared contents are consistent;

and 4, step 4: if not, reading a Received instruction Word in the message block, taking the Received instruction Word as new instruction content, and storing the new instruction content in a corresponding union variable;

and 5: adding 4 to the variable;

step 6: and (5) repeating the steps 1-5 until the variable is consistent with the pointer of the instruction stack, all new instructions are read and saved, and no omission exists.

4. The method for realizing 1553B bus communication based on the single chip microcomputer according to claim 3, wherein the step 4 comprises the following steps:

step 4.1: identifying which data block is remote control or remote measurement according to the instruction information of the message block, and calling different program sections;

step 4.2: circularly taking the number according to the length occupied by the data block, and storing the taken number into a certain shared body;

step 4.3: judging the packet header of the data in the shared body, and if the data in the shared body is incorrect, exiting the module, and executing the step 5;

step 4.4: if the packet header is judged correctly, performing ISO verification of a module 255 on each data until all data are verified; after the check is correct, extracting effective valve control instructions, storing the effective valve control instructions into a corresponding register, and then quitting the module to execute the step 5; and if the ISO check error is found, directly exiting the module and executing the step 5.

5. The method for realizing 1553B bus communication based on the single chip microcomputer of claim 3, wherein each message block in the step 5 occupies 4 word units, and after the last instruction is taken, 4 is added to a variable.

6. A system for realizing 1553B bus communication based on a single chip microcomputer is characterized by comprising a 1553B chip reading operation system of the single chip microcomputer, wherein the 1553B chip reading operation system of the single chip microcomputer comprises the following modules:

module M1: firstly reading the upper 8 bits, setting MSB _ LSBn to be 1 ', performing ' dummy reading ' operation, and discarding data;

module M2: waiting for a period of time;

module M3: setting MSB _ LSBn as '0', reading a low address, and storing a high byte RTdata of a shared body RTdata [1 ];

module M4: setting MSB _ LSBn as '1', reading a high address, and storing a low byte RTdata of a shared body;

module M5: the function return value is a common body word rtdata.

7. The system for realizing 1553B bus communication based on the single-chip microcomputer as claimed in claim 6, wherein the function in the module M5 completes dummy read operation by accessing an external address, and after waiting for a period of time, reads high and low bytes respectively and stores the high and low bytes in a shared body RTdata; the get byte operation starts with a low address and deposits the fetched bytes from high to low.

8. The system for realizing 1553B bus communication based on the single-chip microcomputer of claim 6, wherein the system for realizing 1553B bus communication based on the single-chip microcomputer further comprises a data block pointer system for obtaining an instruction stack, and the data block pointer system for the instruction stack comprises the following modules:

module 1: reading a pointer of an instruction stack;

and (3) module 2: comparing a pointer of the instruction stack to a defined variable;

and a module 3: judging whether the compared contents are consistent;

and (4) module: if not, reading a Received instruction Word in the message block, taking the Received instruction Word as new instruction content, and storing the new instruction content in a corresponding union variable;

and a module 5: adding 4 to the variable;

and a module 6: blocks 1-5 are repeated until the variables are consistent with the pointer of the instruction stack and all new instructions are read and saved without omission.

9. The system for realizing 1553B bus communication based on the single chip microcomputer of claim 8, wherein the module 4 comprises the following modules:

module 4.1: identifying which data block is remote control or remote measurement according to the instruction information of the message block, and calling different program sections;

module 4.2: circularly taking the number according to the length occupied by the data block, and storing the taken number into a certain shared body;

module 4.3: judging the packet header of the data in the shared body, and if the data in the shared body is incorrect, exiting the module and executing a module 5;

module 4.4: if the packet header is judged correctly, performing ISO verification of a module 255 on each data until all data are verified; after the check is correct, effective valve control instructions are extracted and stored in corresponding registers, and then the module is withdrawn, and a module 5 is executed; if an ISO check error is found, the module is directly exited, module 5 executed.

10. The system for realizing 1553B bus communication based on the single chip microcomputer of claim 8, wherein each message block in the module 5 occupies 4 word units, and after the last instruction is taken, 4 is added to a variable.

Technical Field

The invention relates to the technical field of communication between a single chip microcomputer and a peripheral chip, in particular to a method and a system for realizing 1553B bus communication based on the single chip microcomputer, and particularly relates to a method for realizing 1553B bus communication based on the single chip microcomputer.

Background

The 1553B bus is a standard bus for the networking of the electronic subsystems of the American air force, has extremely high reliability and is widely applied to the military fields of aerospace and the like. The message of the 1553B bus consists of a plurality of 16-bit words, and is high in speed and efficiency. However, in many current aerospace products, a single chip microcomputer is used as a master control CPU, only 8-bit data buses are used, and the data are generally processed according to bytes in the single chip microcomputer, because the single chip microcomputer is inflexible in processing the data bits, the received data cannot be converted into 16 bits, and the limitation on data processing is caused. For the received instruction, a terminal is generally used to combine with a last command register, and in such a processing mode, if there is interrupt nesting and the priority of the 1553B interface chip is not high, there is a risk of losing the instruction.

The patent document with the publication number of CN102447600B discloses an asynchronous communication mode of the invention, in particular to a method for realizing HOMEBUS bus communication by a singlechip without a synchronous clock output asynchronous communication, which provides a method for realizing HOMEBUS bus communication by simulating a synchronous clock signal by using a PWM signal in the singlechip during asynchronous communication, thereby randomly selecting the singlechip to realize the HomeBus communication without being limited to the singlechip of H8 series and Fuji series, the singlechip is arranged as the singlechip with the PWM output function, and RXD, TXD and PWM ports of the singlechip are respectively connected with RXD, TXD and RXK ports of HOMEBUS.

In view of the above-mentioned related art, the inventor considers that there are problems of low data processing efficiency and low flexibility, and therefore, a technical solution is needed to improve the above technical problems.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method and a system for realizing 1553B bus communication based on a single chip microcomputer.

The method for realizing 1553B bus communication based on the single chip microcomputer comprises a method for reading a 1553B chip by the single chip microcomputer, wherein the method for reading the 1553B chip by the single chip microcomputer comprises the following steps:

step S1: firstly reading the upper 8 bits, setting MSB _ LSBn to be 1 ', performing ' dummy reading ' operation, and discarding data;

step S2: waiting for a period of time;

step S3: setting MSB _ LSBn as '0', reading a low address, and storing a high byte RTdata of a shared body RTdata [1 ];

step S4: setting MSB _ LSBn as '1', reading a high address, and storing a low byte RTdata of a shared body;

step S5: the function return value is a common body word rtdata.

Preferably, the function in step S5 completes the dummy read operation by accessing the external address, waits for a period of time, reads the high and low bytes, and stores the read bytes in the common body RTdata; the get byte operation starts with a low address and deposits the fetched bytes from high to low.

Preferably, the method for the single chip microcomputer to realize 1553B bus communication further comprises a data block pointer method for obtaining an instruction stack, and the data block pointer method for the instruction stack comprises the following steps:

step 1: reading a pointer of an instruction stack;

step 2: comparing a pointer of the instruction stack to a defined variable;

and step 3: judging whether the compared contents are consistent;

and 4, step 4: if not, reading a Received instruction Word in the message block, taking the Received instruction Word as new instruction content, and storing the new instruction content in a corresponding union variable;

and 5: adding 4 to the variable;

step 6: and (5) repeating the steps 1-5 until the variable is consistent with the pointer of the instruction stack, all new instructions are read and saved, and no omission exists.

Preferably, the step 4 comprises the steps of:

step 4.1: identifying which data block is remote control or remote measurement according to the instruction information of the message block, and calling different program sections;

step 4.2: circularly taking the number according to the length occupied by the data block, and storing the taken number into a certain shared body;

step 4.3: judging the packet header of the data in the shared body, and if the data in the shared body is incorrect, exiting the module, and executing the step 5;

step 4.4: if the packet header is judged correctly, performing ISO verification of a module 255 on each data until all data are verified; after the check is correct, extracting effective valve control instructions, storing the effective valve control instructions into a corresponding register, and then quitting the module to execute the step 5; and if the ISO check error is found, directly exiting the module and executing the step 5.

Preferably, each message block in step 5 occupies 4 word units, and after the last instruction is fetched, 4 is added to the variable.

The invention also provides a system for realizing 1553B bus communication based on the single chip microcomputer, which comprises a 1553B chip reading operation system of the single chip microcomputer, wherein the 1553B chip reading operation system of the single chip microcomputer comprises the following modules:

module M1: firstly reading the upper 8 bits, setting MSB _ LSBn to be 1 ', performing ' dummy reading ' operation, and discarding data;

module M2: waiting for a period of time;

module M3: setting MSB _ LSBn as '0', reading a low address, and storing a high byte RTdata of a shared body RTdata [1 ];

module M4: setting MSB _ LSBn as '1', reading a high address, and storing a low byte RTdata of a shared body;

module M5: the function return value is a common body word rtdata.

Preferably, the function in the module M5 completes the dummy read operation by accessing the external address, and after waiting for a period of time, reads the high and low bytes respectively and stores the read bytes in the common body RTdata; the get byte operation starts with a low address and deposits the fetched bytes from high to low.

Preferably, the system for realizing 1553B bus communication by the single chip microcomputer further comprises a data block pointer system for acquiring an instruction stack, and the data block pointer system for the instruction stack comprises the following modules:

module 1: reading a pointer of an instruction stack;

and (3) module 2: comparing a pointer of the instruction stack to a defined variable;

and a module 3: judging whether the compared contents are consistent;

and (4) module: if not, reading a Received instruction Word in the message block, taking the Received instruction Word as new instruction content, and storing the new instruction content in a corresponding union variable;

and a module 5: adding 4 to the variable;

and a module 6: blocks 1-5 are repeated until the variables are consistent with the pointer of the instruction stack and all new instructions are read and saved without omission.

Preferably, said module 4 comprises the following modules:

module 4.1: identifying which data block is remote control or remote measurement according to the instruction information of the message block, and calling different program sections;

module 4.2: circularly taking the number according to the length occupied by the data block, and storing the taken number into a certain shared body;

module 4.3: judging the packet header of the data in the shared body, and if the data in the shared body is incorrect, exiting the module and executing a module 5;

module 4.4: if the packet header is judged correctly, performing ISO verification of a module 255 on each data until all data are verified; after the check is correct, effective valve control instructions are extracted and stored in corresponding registers, and then the module is withdrawn, and a module 5 is executed; if an ISO check error is found, the module is directly exited, module 5 executed.

Preferably, each message block in the module 5 occupies 4 word units, and after the last instruction is fetched, 4 is added to the variable.

Compared with the prior art, the invention has the following beneficial effects:

1. the invention overcomes the contradiction between the 8-bit data interface of the singlechip and the 1553B 16-bit data bus interface, improves the data processing efficiency and has certain flexibility;

2. according to the invention, by utilizing the characteristic that a 1553B chip stores a received message in an instruction stack and responding to a 1553B bus in a query rather than interrupt manner, the RT accesses a data block pointer instead of the previous instruction register every time, so that the instruction is ensured not to be lost;

3. the invention does not occupy the resources interrupted by the 1553B chip, has great advantages for the application with low requirements on remote measurement or real-time performance, can avoid the interruption conflict in the processor and reasonably utilizes the resources.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a flow chart of the single chip microcomputer reading operation of a 1553B chip;

FIG. 2 is a flow chart of a query and fetch instruction according to the present invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The invention provides a method and a system for realizing 1553B bus communication based on a single chip microcomputer, which define an 8-bit character type array of two one-dimensional elements and a 16-bit integer variable, establish a shared body, utilize the variables in the shared body to share a storage space, complete the conversion of bytes and words and flexibly read the high and low bits of the byte variables. And updating bytes or words in the shared body at any time according to program needs, and accessing as required. On the other hand, when reading messages on the 1553B bus, a data block pointer in the RT instruction stack is directly accessed, if the pointer is judged to point to the next message, a Received instruction Word (Received Command Word) in the message packet is read, the instruction Word is new instruction content, the read data is stored in the shared body, and message addresses can be accessed one by controlling the pointer of the shared body, so that no message is leaked. And the data stored in the shared body can be flexibly operated by bytes or words.

The sharing body is utilized to overcome the limitation that an 8-bit data bus of the singlechip is matched with a 16-bit data bus of 1553B, so that the data processing efficiency is improved; defining a pointer to catch up with a data block pointer in an instruction stack, reading an instruction word, and avoiding missing a message; a shared body unit is opened up, a one-dimensional character type array of two elements, an integer variable and a pointer type are defined, high-low bit flexible reading of byte variables is completed by using the pointer, and bytes or words in the shared body can be updated at any time according to program requirements and accessed as required.

Using a shared body to match with a small tail end processor architecture, firstly reading 8 high bits, setting P0.0(MSB _ LSBn) to be 1 ', performing ' dummy read ' operation, and discarding data; setting P0.0(MSB _ LSBn) as '0', reading low address, and storing into high byte of shared body; setting P0.0(MSB _ LSBn) '1', the high address is read and stored in the low byte of the common bank.

And reading the 1553B bus, defining a data block pointer in a variable 'catch-up' instruction stack, and reading a Received instruction Word (Received Command Word) in the message packet if the data block pointer points to the next message, wherein the instruction Word is new instruction content and is stored in the shared body. If the data block pointer is judged to be the same as the last time, no new message is indicated. Therefore, according to the size of the stack space, 64-512 messages can be cached in different ways, and the message addresses can be accessed one by controlling the pointers of the unions, so that one message cannot be missed.

The instruction fetching operation can realize word operation and byte algorithm on the same data without occupying more memory space.

When software is implemented, a shared body unit is opened up, because variables in the shared body share a storage space, a character type array containing two elements, an integer variable and a pointer variable are defined to construct the shared body, the main function is to perfectly realize the conversion of 8 bits and 16 bits by utilizing the characteristics of the two shared storage spaces, and simultaneously, the pointer is utilized to finish the flexible reading of high and low bits of byte variables. And updating bytes or words in the shared body at any time according to program needs, and accessing as required.

For reading messages on the 1553B bus, generally, the last instruction (last command) is accessed, but the method easily loses the instruction. The invention combines the opened unit to directly access the data block pointer in the RT instruction stack, if the pointer is judged to point to the next message, the Received instruction Word (Received Command Word) in the message packet is read, and the instruction Word is the new instruction content. If the data block pointer is judged to be the same as the last time, no new message is indicated. Therefore, according to the size of the stack space, 64-512 messages can be cached in different ways, and the message addresses can be accessed one by controlling the pointers in the unions, so that one message cannot be missed.

The invention is successfully applied to a large project at present, and the phenomenon of instruction loss is not found after a plurality of tests in early stages and flight test verification.

Firstly, a shared body is defined, 3 members are defined inside, one is a one-dimensional array byte [2] containing 2 character type elements, one is integer variable worddata, and the other is pointer pt.

Due to the 8-bit interface mode of the single chip microcomputer, an 8-bit data bus is connected to the D15-D8 and the D7-D0 of the 1553B chip at the same time, an external address line and a strobe signal are needed to select whether a low byte or a high byte is operated, and the first byte to be read needs to be discarded, namely 'dummy read'. The method aims at writing the read byte into the shared body, so that 8-bit data of the CPU bus can be automatically converted into a 16-bit word internally. According to the idea, a function for reading the 1553B bus is designed.

Referring to fig. 1, the specific steps are as follows:

step S1: firstly reading the upper 8 bits, setting P0.0(MSB _ LSBn) to be 1 ', performing ' dummy reading ' operation, and discarding data; step S2: waiting for a period of time; step S3: setting P0.0(MSB _ LSBn) as '0', reading a low address, and storing a high byte RTdata.byte data [1] of the common body RTdata; step S4: setting P0.0(MSB _ LSBn) as '1', reading a high address, and storing a low byte RTdata.byte data [0] of the shared body; step S5: the function return value is a common body word rtdata.

The function completes dummy read operation by accessing an external address, reads high and low bytes after waiting for a period of time, stores the high and low bytes into a shared RTdata, and realizes reading of 16-bit data on a 1553B bus. It should be noted here that the get byte operation starts with a low address and the get byte is put from high to low, so that the resulting word is the value of the normal variable.

Referring to FIG. 2, the data block pointer of the instruction stack is obtained by the following process:

step 1: reading a pointer of an instruction stack; step 2: compare the pointer of the instruction stack to a self-defined variable (assuming the variable name Ptstu _ my); and step 3: judging whether the compared contents are consistent; and 4, step 4: if the Received Command Word is inconsistent with the Received Command Word, the Received Command Word in the message block is read and stored as new Command content in a corresponding unit variable (assuming that the variable name is RTarray.

In general, a new instruction needs to verify whether the content of the instruction is legal, for example, ISO check of module 255, according to the following steps:

step 4.1: identifying which data block is remote control or remote measurement according to the instruction information of the message block, and calling different program sections; step 4.2: circularly taking the number according to the length occupied by the data block, and storing the taken number into a certain shared body; step 4.3: judging the packet header of the data in the shared body, wherein the operation is convenient by using words, and if the operation is incorrect, exiting the module and executing the step 5; step 4.4: if the packet header is judged to be correct, performing ISO verification of a module 255 on each data (by byte) until all data are verified. And if the check is correct, extracting a valid valve control instruction, storing the valid valve control instruction in a corresponding register, and then exiting the module to execute the step 5. And if the ISO check error is found, directly exiting the module and executing the step 5.

And 5: add 4 to the variable Ptstu _ my. Because each message block occupies 4 word units, after the last instruction is taken, 4 is added to the variable Ptstu _ my in order to catch up the position of the pointer of the data block; step 6: steps 1-5 are repeated until Ptstu _ my coincides with the pointer of the instruction stack. I.e. all new instructions are read and saved down without omission.

The invention also provides a system for realizing 1553B bus communication based on the single chip microcomputer, which comprises a 1553B chip reading operation system of the single chip microcomputer, wherein the 1553B chip reading operation system of the single chip microcomputer comprises the following modules:

module M1: firstly reading the upper 8 bits, setting P0.0(MSB _ LSBn) to be 1 ', performing ' dummy reading ' operation, and discarding data; module M2: waiting for a period of time; module M3: setting P0.0(MSB _ LSBn) as '0', reading a low address, and storing a high byte RTdata.byte data [1] of the common body RTdata; module M4: setting P0.0(MSB _ LSBn) as '1', reading a high address, and storing a low byte RTdata.byte data [0] of the shared body; module M5: the function return value is a common body word rtdata. The function completes dummy reading operation by accessing an external address, reads high and low bytes after waiting for a period of time, and stores the high and low bytes in the share RTdata; the get byte operation starts with a low address and deposits the fetched bytes from high to low.

The system for realizing 1553B bus communication by the singlechip further comprises a data block pointer system for acquiring an instruction stack, wherein the data block pointer system of the instruction stack comprises the following modules: module 1: reading a pointer of an instruction stack; and (3) module 2: comparing a pointer of the instruction stack to a defined variable; and a module 3: and judging whether the compared contents are consistent.

And (4) module: if not, reading a Received instruction Word in the message block, taking the Received instruction Word as new instruction content, and storing the new instruction content in a corresponding union variable; module 4.1: identifying which data block is remote control or remote measurement according to the instruction information of the message block, and calling different program sections; module 4.2: circularly taking the number according to the length occupied by the data block, and storing the taken number into a certain shared body; module 4.3: judging the packet header of the data in the shared body, and if the data in the shared body is incorrect, exiting the module and executing a module 5; module 4.4: if the packet header is judged correctly, performing ISO verification of a module 255 on each data until all data are verified; after the check is correct, effective valve control instructions are extracted and stored in corresponding registers, and then the module is withdrawn, and a module 5 is executed; if an ISO check error is found, the module is directly exited, module 5 executed.

And a module 5: adding 4 to the variable; each message block takes 4 word units, and after the last instruction is fetched, 4 is added to the variable Ptstu _ my.

And a module 6: blocks 1-5 are repeated until the variables are consistent with the pointer of the instruction stack and all new instructions are read and saved without omission.

The invention establishes a shared body to convert 8-bit data and 16-bit data, can also read 8-bit high bytes or low bytes at will through a pointer, easily realizes different splicing requirements of byte data, saves memory space, and solves the limitation that 8-bit buses of a singlechip are matched with 16-bit external interfaces to a certain extent. From the application case, for the same instruction, some data are more convenient to adopt word processing, and some data need byte operation. Such as packet identification, packet length, etc. of the data packet, the content of the data is clearly defined in the protocol, and the reading of the word in the community can be used to determine whether the content is correct. However, for checking a data packet, for example, using the ISO checking method as packet error control, a modulo 255 operation of bytes is required for the data, and the operation can be performed by reading the corresponding bytes of the common bank.

The invention adopts a method of tracking the pointer of the data block, can open up the size of a stack area according to the requirement, control the cached message items, can cache 64-512 messages with unequal amount, even if the CPU fails to respond to a 1553B bus instruction in time due to other interruption disturbance, the CPU can continue to read the instruction from the stack after responding to the external interruption until all new instructions are completely fetched, and the instruction is received without omission.

The invention is flexible, simple and easy to implement, and is suitable for communication between most single-chip microcomputers and 1553B buses. The method has successful application to propulsion line boxes for the third lunar exploration and to control drives for the propulsion system of the new spacecraft.

Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.