阅读说明：本技术 半导体封装方法及半导体封装结构 (Semiconductor packaging method and semiconductor packaging structure ) 是由 周辉星 于 2020-03-27 设计创作，主要内容包括：本申请提供一种半导体封装方法及半导体封装结构。所述半导体封装方法包括：将至少一个待封装的裸片贴装于载板上,所述裸片靠近所述载板的表面为正面,所述裸片的正面设有多个焊垫；形成第一包封层,所述第一包封层覆盖在所述载板上,包封住所述至少一个待封装的裸片；剥离所述载板,露出所述裸片的正面；将至少一个引线框固定于所述裸片的正面,并将所述引线框的引脚与对应的裸片的焊垫电连接；所述引线框包括至少一个引脚区,每一所述引脚区与一个所述裸片对应,每一所述引脚区设有至少一个引脚；在所述引脚上形成将所述焊垫引出的导电结构。(The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: mounting at least one bare chip to be packaged on a carrier plate, wherein the surface of the bare chip close to the carrier plate is a front surface, and a plurality of welding pads are arranged on the front surface of the bare chip; forming a first encapsulating layer, wherein the first encapsulating layer covers the carrier plate and encapsulates the at least one bare chip to be encapsulated; stripping the carrier plate to expose the front surface of the bare chip; fixing at least one lead frame on the front surface of the bare chip, and electrically connecting the pins of the lead frame with the welding pads of the corresponding bare chip; the lead frame comprises at least one lead area, each lead area corresponds to one bare chip, and each lead area is provided with at least one lead; and forming a conductive structure for leading out the welding pad on the pin.)

1. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises:

mounting at least one bare chip to be packaged on a carrier plate, wherein the bare chip is provided with a front surface, the front surface of the bare chip is close to the surface of the carrier plate, and the front surface of the bare chip is provided with a plurality of welding pads;

forming a first encapsulating layer, wherein the first encapsulating layer covers the carrier plate and encapsulates the at least one bare chip to be encapsulated;

stripping the carrier plate to expose the front surface of the bare chip;

fixing at least one lead frame on the front surface of the bare chip, and electrically connecting the pins of the lead frame with the welding pads of the corresponding bare chip; the lead frame comprises at least one lead area, each lead area corresponds to one bare chip, and each lead area is provided with at least one lead;

and forming a conductive structure for leading out the welding pad on the pin.

2. The semiconductor packaging method of claim 1, wherein the securing at least one leadframe to the front side of the die comprises:

placing at least one lead frame on the front side of the die, so that the lead area of the lead frame is opposite to the corresponding die, and the lead is opposite to the welding pad of the die;

and forming an adhesive layer, so that the lead frame is fixed on the front surface of the bare chip and the first packaging layer through the adhesive layer, and the surface of the pin is exposed out of the adhesive layer.

3. The semiconductor packaging method according to claim 2, wherein a through hole is provided on the pin, and the adhesive layer is formed in the through hole; the electrically connecting the pins of the lead frame with the pads of the corresponding die includes:

removing the adhesive layer in the through hole;

and filling a conductive material in the through hole to enable the pin to be electrically connected with the welding pad through the conductive material.

4. The semiconductor packaging method according to claim 1, wherein the lead frame includes a plurality of the lead areas, the lead frame includes a plurality of first connecting rods and a plurality of second connecting rods, the plurality of first connecting rods surround to form a frame body, the second connecting rods are arranged in the frame body to divide the frame body into the plurality of lead areas, and leads of the lead areas are connected to the first connecting rods or the second connecting rods.

5. The semiconductor packaging method according to claim 4, wherein the pin is provided with a through hole, the pin is connected with the first connecting rod, and the through hole is arranged on the side of the pin, which is far away from the first connecting rod; or the pins are connected with the second connecting rod, and the through holes are formed in one side, deviating from the second connecting rod, of the pins.

6. The semiconductor packaging method according to claim 4, wherein a package structure is obtained after forming the conductive structure on the leads, the semiconductor packaging method further comprising:

and cutting the packaging structure, and removing the first connecting rod and the second connecting rod.

7. The semiconductor packaging method of claim 1, wherein after forming the conductive structure on the leads, the semiconductor packaging method further comprises: and forming a dielectric layer on the lead frame, wherein the dielectric layer covers the exposed lead frame, and the surface of the conductive structure, which is far away from the lead frame, exposes the dielectric layer.

8. The semiconductor packaging method of claim 1, wherein prior to forming the conductive structure on the leads, the semiconductor packaging method further comprises:

forming a dielectric layer on the lead frame, the dielectric layer covering the lead frame;

forming an opening on the dielectric layer at a position corresponding to the pin, wherein the opening exposes a part of the pin;

the forming of the conductive structure on the pin includes: and filling a conductive material in the opening to form a conductive structure.

9. The semiconductor packaging method according to claim 7 or 8, further comprising:

forming a rewiring layer on the dielectric layer, the rewiring layer being electrically connected to the conductive structure;

and forming a second packaging layer and a conductive convex column embedded in the second packaging layer, wherein the second packaging layer is used for packaging the rewiring layer and the exposed dielectric layer, the second packaging layer is exposed on the surface of the conductive convex column, and the conductive convex column is electrically connected with the rewiring layer.

10. A semiconductor package structure, comprising:

the packaging structure comprises a first packaging layer, a second packaging layer and a packaging material, wherein at least one concave cavity is arranged on the first packaging layer;

the bare chips are in one-to-one correspondence with the cavities, the bare chips are positioned in the corresponding cavities, the front surfaces of the bare chips are exposed out of the first packaging layer, and a plurality of welding pads are arranged on the front surfaces of the bare chips;

at least one pin fixed on the front surface of the bare chip, wherein each pin corresponds to one bare chip and is electrically connected with a welding pad of the corresponding bare chip;

and the conductive structure is formed on the pin and leads out the welding pad.

11. The semiconductor package structure according to claim 10, wherein the pins are provided with through holes, the semiconductor package structure further comprising a conductive material filled in the through holes, and the pins are electrically connected to corresponding bonding pads of the die through the conductive material.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.

Background

Common semiconductor packaging technologies, such as die packaging technologies, mainly include the following processes: the method comprises the steps of firstly bonding the front surface of a bare chip on a substrate through an adhesive tape, carrying out hot-press plastic package, peeling the substrate, then forming a rewiring structure on the front surface of the bare chip, and carrying out packaging.

The process of forming the rewiring structure comprises the steps of sputtering, whirl coating, photoetching, electroplating, film etching and the like, and the process is complex, so that the packaging time of the whole packaging process is long.

Disclosure of Invention

A first aspect of an embodiment of the present application provides a semiconductor packaging method, including:

mounting at least one bare chip to be packaged on a carrier plate, wherein the bare chip is provided with a front surface, the front surface of the bare chip is close to the surface of the carrier plate, and the front surface of the bare chip is provided with a plurality of welding pads;

forming a first encapsulating layer, wherein the first encapsulating layer covers the carrier plate and encapsulates the at least one bare chip to be encapsulated;

stripping the carrier plate to expose the front surface of the bare chip;

fixing at least one lead frame on the front surface of the bare chip, and electrically connecting the pins of the lead frame with the welding pads of the corresponding bare chip; the lead frame comprises at least one lead area, each lead area corresponds to one bare chip, and each lead area is provided with at least one lead;

and forming a conductive structure for leading out the welding pad on the pin.

In one embodiment, the securing at least one lead frame to the front side of the die includes:

placing at least one lead frame on the front side of the die, so that the lead area of the lead frame is opposite to the corresponding die, and the lead is opposite to the welding pad of the die;

and forming an adhesive layer, so that the lead frame is fixed on the front surface of the bare chip and the first packaging layer through the adhesive layer, and the surface of the pin is exposed out of the adhesive layer.

In one embodiment, the pin is provided with a through hole, and the adhesive layer is formed in the through hole; the electrically connecting the pins of the lead frame with the pads of the corresponding die includes:

removing the adhesive layer in the through hole;

and filling a conductive material in the through hole to enable the pin to be electrically connected with the welding pad through the conductive material.

In one embodiment, the lead frame includes a plurality of the pin areas, the lead frame includes a plurality of first connecting rods and a plurality of second connecting rods, the plurality of first connecting rods surround to form a frame body, the second connecting rods are arranged in the frame body to divide the frame body into the plurality of pin areas, and pins of the pin areas are connected with the first connecting rods or the second connecting rods.

In one embodiment, the pin is provided with a through hole, the pin is connected with the first connecting rod, and the through hole is arranged on one side of the pin, which is far away from the first connecting rod; or the pins are connected with the second connecting rod, and the through holes are formed in one side, deviating from the second connecting rod, of the pins.

In one embodiment, a package structure is obtained after forming the conductive structure on the leads, and the semiconductor packaging method further comprises:

and cutting the packaging structure, and removing the first connecting rod and the second connecting rod.

In one embodiment, after forming the conductive structure on the lead, the semiconductor packaging method further includes: and forming a dielectric layer on the lead frame, wherein the dielectric layer covers the exposed lead frame, and the surface of the conductive structure, which is far away from the lead frame, exposes the dielectric layer.

In one embodiment, before forming the conductive structure on the lead, the semiconductor packaging method further includes:

forming a dielectric layer on the lead frame, the dielectric layer covering the lead frame;

forming an opening on the dielectric layer at a position corresponding to the pin, wherein the opening exposes a part of the pin;

the forming of the conductive structure on the pin includes: and filling a conductive material in the opening to form a conductive structure.

In one embodiment, the semiconductor packaging method further includes:

forming a rewiring layer on the dielectric layer, the rewiring layer being electrically connected to the conductive structure;

and forming a second packaging layer and a conductive convex column embedded in the second packaging layer, wherein the second packaging layer is used for packaging the rewiring layer and the exposed dielectric layer, the second packaging layer is exposed on the surface of the conductive convex column, and the conductive convex column is electrically connected with the rewiring layer.

A second aspect of an embodiment of the present application provides a semiconductor package structure, including:

the packaging structure comprises a first packaging layer, a second packaging layer and a packaging material, wherein at least one concave cavity is arranged on the first packaging layer;

the bare chips are in one-to-one correspondence with the cavities, the bare chips are positioned in the corresponding cavities, the front surfaces of the bare chips are exposed out of the first packaging layer, and a plurality of welding pads are arranged on the front surfaces of the bare chips;

at least one pin fixed on the front surface of the bare chip, wherein each pin corresponds to one bare chip and is electrically connected with a welding pad of the corresponding bare chip;

and the conductive structure is formed on the pin and leads out the welding pad.

In one embodiment, the pins are provided with through holes, the semiconductor package structure further includes a conductive material filled in the through holes, and the pins are electrically connected with the corresponding bonding pads of the die through the conductive material.

The embodiment of the application achieves the main technical effects that:

according to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the welding pads of the bare chip are led out through the pins of the lead frame to realize the fan-out wiring, and the lead frame is prepared in advance.

Drawings

FIG. 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

fig. 2 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;

fig. 3 is a schematic structural diagram of a die to be packaged according to an exemplary embodiment of the present application;

fig. 4 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;

FIG. 5 is a schematic diagram of a leadframe structure provided by an exemplary embodiment of the present application;

fig. 6 is a partial schematic view of the lead frame shown in fig. 5 taken along line AA;

FIG. 7 is a partial schematic view of the lead frame shown in FIG. 5 taken along line CC;

FIG. 8 is a partial schematic view of the lead frame shown in FIG. 5 taken along line BB;

fig. 9 is a schematic structural diagram of a third intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;

fig. 10 is a schematic structural diagram of a fourth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;

fig. 11 is a schematic structural diagram of a semiconductor package structure according to an exemplary embodiment of the present application;

fig. 12 is a schematic structural diagram of another semiconductor package structure provided in an exemplary embodiment of the present application;

fig. 13 is a schematic structural diagram of another semiconductor package structure according to an exemplary embodiment of the present application.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 150.

In step 110, at least one die to be packaged is mounted on a carrier, the die having a front surface, the front surface of the die being close to the surface of the carrier, the front surface of the die having a plurality of bonding pads.

A first intermediate structure as shown in fig. 2 may be obtained via step 110. In the embodiment shown in fig. 2, a plurality of dies 20 to be packaged are mounted on the carrier 10. In other embodiments, the number of the dies 20 to be packaged mounted on the carrier board 10 may be one.

In one embodiment, the die 20 to be packaged may be obtained by dicing a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with an insulating layer and a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the back surface of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.

The pads of the die 20 to be packaged are formed by conductive electrodes leading from the internal circuitry of the die to the surface of the die. Referring to fig. 3, the front surface of the die 20 to be packaged may be provided with a plurality of pads 21 and an insulating layer 22 formed between the pads 21, the insulating layer 22 may cover edges of the pads 21, and the thickness of the insulating layer 22 may be greater than that of the pads 21. The bonding pads 21 are prepared on the conductive electrodes of the bare chip 20, and the conductive electrodes of the bare chip are led out.

Only two pads 21 are illustrated on each die 20 in the structure shown in fig. 2. In practice, more than two pads 21 may be provided on the die 20, as shown in fig. 3.

In one embodiment, the shape of the carrier plate 10 may be circular, rectangular or other shape. The carrier 10 may be a small-sized wafer substrate, or may be a larger-sized carrier, such as a stainless steel substrate, a polymer substrate, etc.

In one embodiment, the die 20 to be packaged may be attached to the carrier 10 by an adhesive layer, and the adhesive layer may be made of a material that is easily peeled off so as to peel off the carrier 10 and the die 20 to be packaged later, for example, the adhesive layer may be made of a thermal release material that can be heated to lose its adhesiveness.

In step 120, a first encapsulating layer is formed, wherein the first encapsulating layer covers the carrier plate and encapsulates the at least one die to be encapsulated.

A second intermediate structure as shown in fig. 4 may be obtained through step 120. Referring to fig. 4, a first encapsulating layer 30 is formed on the die 20 and the exposed carrier 10 for completely encapsulating the die 20 to be packaged to reconstruct a flat plate structure, so that after the carrier 10 is peeled off, the re-wiring and packaging can be continued on the reconstructed flat plate structure.

In one embodiment, before forming the first encapsulation layer 30, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities from the surfaces of the die 20 and the carrier 10, so that the connection between the first encapsulation layer 30 and the die 20 and the carrier 10 to be packaged is more intimate and no delamination or cracking occurs.

In one embodiment, the first encapsulant layer 30 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.

In step 130, the carrier is stripped to expose the front side of the die.

In one embodiment, the carrier board 10 can be mechanically peeled off directly from the first encapsulant layer 30 and the die 20 to be packaged. In another embodiment, the carrier 10 and the die 20 to be packaged are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity after being heated, so as to peel off the carrier 10. After the carrier 10 is peeled off, the front surface of the die 20 to be packaged is exposed.

In one embodiment, after step 130, a support plate may be disposed on the back side of the first encapsulant layer 30 facing away from the die 20 to provide support for subsequent steps.

In step 140, at least one lead frame is fixed on the die, and the pins of the lead frame are electrically connected with the bonding pads of the corresponding die; the lead frame comprises at least one lead area, each lead area corresponds to one bare chip, and each lead area is provided with at least one lead.

Because the lead frame comprises at least one pin area, one pin area corresponds to one bare chip, the pin area is provided with at least one pin, and the pin of the pin area is electrically connected with the corresponding bonding pad of the bare chip 20 to be packaged, the pin of the pin area can lead out the bonding pad of the bare chip. The lead frame is prepared in advance, and compared with the scheme that the bonding pad of the bare chip is led out by forming the rewiring layer on the bare chip 20, the packaging process can be simplified, the time for forming the rewiring layer is saved, and the time for the semiconductor packaging method is reduced.

The number of the lead frame 40 may be one, and when the number of the dies 20 to be packaged is plural, the lead frame 40 includes a plurality of lead regions 41, and the number of the lead regions 41 may be the same as the number of the dies 20. In other embodiments, the number of lead frames 40 may be multiple, each lead frame 40 may include one or more lead regions 41, and the total number of lead regions 41 of the multiple lead frames 40 may be the same as the number of dies 20 to be packaged.

In one embodiment, referring to fig. 5 to 8, the lead frame 40 includes a plurality of the lead regions 41. The lead frame 40 includes a plurality of first connecting rods 42 and a plurality of second connecting rods 43, the plurality of first connecting rods 42 enclose to form a frame body, the plurality of second connecting rods 43 are disposed in the frame body to divide the frame body into a plurality of lead areas 41, and the leads 411 of the lead areas 41 are connected to the first connecting rods 42 or the second connecting rods 43. When a plurality of pins 411 are disposed in the pin area 41, the plurality of pins 411 are arranged at intervals in the pin area 41. In the illustrated embodiment, the lead frame 40 includes four first links 42 and two second links 43, and the four first links 42 surround a rectangular frame body. Two second connecting rods 43 are crosswise arranged in the frame body, and two ends of the second connecting rods 43 are respectively connected with two oppositely arranged first connecting rods 42, so that the second connecting rods 43 divide the area in the frame body into four pin areas 41. In other embodiments, the lead frame 40 may include one lead region 41. When the lead frame 40 includes a plurality of lead areas 41, the leads 411 of the plurality of lead areas 41 are connected to each other by the first connecting bar 42 and the second connecting bar 43 to form an integral structure, which helps to simplify the packaging process.

In one embodiment, the leads 411 are provided with through holes 412, and when the lead frame 40 is fixed on the die 20, the through holes 412 on the leads 411 are opposite to the corresponding pads 21 of the die 20. The through holes 412 of the leads 411 are opposite to the pads 21 of the die 20, which means that the through holes 412 correspond to the pads 21 in position in the lamination direction perpendicular to the film layers. The through hole 412 is filled with a conductive material in a subsequent step, and the pin 411 is electrically connected to the pad 21 of the die 20 through the conductive material in the through hole 412. With such an arrangement, the bottom of the conductive material in the through hole 412 directly contacts the pad 21, and the side of the conductive material directly contacts the pin 411, so that the pin 411 and the pad 21 are electrically connected well, thereby avoiding the problem of poor contact between the pin 411 and the pad 21.

In one embodiment, when the pin 411 is connected to the first link 42, the through hole 412 on the pin 411 is disposed on a side of the pin 411 facing away from the first link 42. When the pin 411 is connected to the second link 43, the through hole 412 is disposed at a portion of the pin 411 facing away from the second link 43. With this arrangement, after the lead frame 40 is fixed on the die 20, a portion of the lead 411 is located at a side of the die 20, but not above the die 411, which helps to reduce the density of the lead-out pads 21, thereby facilitating electrical connection between other devices and the pads 21.

In one embodiment, the plurality of pins 411 in the same pin area 41 may be arranged at intervals along the circumferential direction, so as to ensure that the pads 21 at different positions in the die 20 can be led out through the corresponding pins 411.

In one embodiment, the lead frame 40 may be formed of a metal plate by etching.

In one embodiment, the step of securing the lead frame to the die may be accomplished by steps 141 and 142 as follows.

In step 141, the lead frame is placed on the die with the lead regions of the lead frame opposite the corresponding die and the leads opposite the bond pads of the die.

A third intermediate structure as shown in fig. 9 is obtained through step 141. The vias 412 on the leads 411 correspond in location to the pads 21 of the die 20.

In step 142, an adhesive layer is formed, so that the lead frame is fixed on the die and the first encapsulation layer through the adhesive layer, and the surface of the lead is exposed out of the adhesive layer.

A fourth intermediate structure as shown in fig. 10 is obtained through step 142.

The adhesive layer 50 may be made of an insulating material for protecting the lead frame 40 and fixing the lead frame 40 on the surface of the die 20 and the first encapsulation layer 30. The adhesive layer 50 covers the front surface of the exposed die 20 and the surface of the exposed first encapsulant layer 30, and wraps the sides of the leads 411, the first links 42, and the second links 43.

In one embodiment, when forming the adhesive layer 50, the adhesive layer 50 may cover the surfaces and the side portions of the lead 411, the first link 42, and the second link 43, and then the adhesive layer 50 is thinned to reduce the thickness of the adhesive layer 50 to be substantially the same as the thickness of the lead frame 40, thereby exposing the surfaces of the lead 411, the first link 42, and the second link 43.

In one embodiment, the step of electrically connecting the leads of the leadframe with the pads of the corresponding die can be accomplished by the following steps 143 and 144.

In step 143, the adhesive layer in the through hole is removed.

When the adhesive layer 50 is formed, the through holes 412 of the leads 411 are also filled with the adhesive layer, and the adhesive layer in the through holes 412 needs to be removed before the conductive material is formed in the through holes 412.

In one embodiment, the material of the adhesive layer 50 is photosensitive, and the adhesive layer 50 in the through hole 412 can be removed by light irradiation. In other embodiments, the adhesive layer 50 is made of a laser-reactive material, and the adhesive layer in the through hole 412 can be removed by laser.

In step 144, a conductive material is filled in the through hole, so that the pin is electrically connected to the pad through the conductive material.

The thickness of the conductive material formed in via 412 may be the same as the thickness of pin 411 so that the surface of the resulting structure after filling with conductive material is level throughout.

In step 150, a conductive structure is formed on the lead to lead out the pad.

The semiconductor package structure shown in fig. 11 can be obtained through step 150. The surface of each lead 411 facing away from the first encapsulant layer 30 may be formed with a conductive structure 60, so that the conductive structure 60 leads out the pad 21 of the die 20. The conductive structure 60 may be a pillar, such as a cylinder, or a cube.

In one embodiment, referring to fig. 12, the surface of the leadframe 40 facing away from the first encapsulant layer 30 may be formed with a dielectric layer 70. The dielectric layer 70 covers the exposed lead frame 40 and the exposed adhesive layer 50, and the surface of the conductive structure 60 away from the lead frame 40 exposes the dielectric layer 70. The dielectric layer 70 is used to protect the leads 411 and the conductive structure 60.

In one embodiment, the step of forming the dielectric layer 70 may be performed after the step 150, that is, the conductive structure 60 is formed first, and then the dielectric layer 70 is formed, wherein the dielectric layer 70 contacts the sidewall of the conductive structure 60.

In this embodiment, the thickness of the dielectric layer 70 may be substantially the same as the thickness of the conductive structure 60, with the surface of the conductive structure 60 exposed. In the process of forming the dielectric layer 70, the initially formed dielectric layer 70 may cover the surface and the side portions of the conductive structure 60, and then the dielectric layer 70 is thinned to reduce the thickness of the dielectric layer 70 to be substantially the same as the thickness of the conductive structure 60, thereby exposing the surface of the conductive structure 60.

In another embodiment, the step of forming the dielectric layer 70 may be performed before step 150. Between step 150, the step of forming the dielectric layer 70 may be accomplished by:

forming a dielectric layer on the lead frame, wherein the dielectric layer covers the lead frame and the exposed adhesive layer;

and forming openings on the dielectric layer at positions corresponding to the pins, wherein the openings expose parts of the pins.

In this embodiment, the forming of the conductive structure on the lead includes: and filling a conductive material in the opening of the dielectric layer to form a conductive structure.

In one embodiment, after forming the dielectric layer 70, the semiconductor packaging method further includes:

forming a rewiring layer on the dielectric layer, the rewiring layer being electrically connected to the conductive structure;

and forming a second packaging layer and a conductive convex column embedded in the second packaging layer, wherein the second packaging layer is used for packaging the rewiring layer and the exposed dielectric layer, the second packaging layer is exposed on the surface of the conductive convex column, and the conductive convex column is electrically connected with the rewiring layer.

A sixth intermediate structure as shown in fig. 13 is obtained by the above steps. As shown in fig. 13, the redistribution layer 80 is electrically connected to the conductive structure 60, and the redistribution layer 80 is led out through the conductive pillar 90, so that the conductive pillar 90 leads out the bonding pad 21 of the die 20. In this way, a multi-layer package structure can be realized. The redistribution layer 80 includes patterned traces formed on the surface of the dielectric layer 70, and the patterned traces are electrically connected to the conductive structures 60.

In one embodiment, in the process of forming the second encapsulant layer 91 and the conductive posts 90, the conductive posts 90 may be formed on the redistribution layer 80, and then the second encapsulant layer 91 is formed on the exposed redistribution layer 80 and the exposed dielectric layer 70, wherein the surface of the conductive posts 91 exposes the second encapsulant layer 91.

In another embodiment, in the process of forming the second encapsulant layer 91 and the conductive posts 90, the second encapsulant layer 91 may be formed on the redistribution layer 80 and the exposed dielectric layer 70, an opening may be formed in the second encapsulant layer 91 at a position corresponding to the connection point of the lead 411, and then the conductive posts 90 may be formed in the opening of the second encapsulant layer 91.

In one embodiment, after obtaining the semiconductor package structure shown in fig. 12 or fig. 13, the semiconductor packaging method further includes: and cutting the semiconductor packaging structure, and removing the first connecting rod and the second connecting rod. The package structure may be diced along the dotted lines shown in fig. 12 and 13, and the diced package structure may be cut into a plurality of package units including only a single die 20. Wherein the cutting can be performed by means of laser or mechanical cutting. The first link and the second link are removed by cutting, so that the connection of the plurality of pins 411 through the first link or the second link can be avoided, and the influence on the normal operation of the die caused by the electrical connection of different bonding pads 21 of the die can be avoided. According to the semiconductor packaging method provided by the embodiment of the application, the welding pads of the bare chip are led out through the pins of the lead frame to realize the fan-out wiring, and the lead frame is prepared in advance.

The embodiment of the application also provides a semiconductor packaging structure. Referring to fig. 12 and 13, the semiconductor package structure includes:

the first encapsulating layer 30 is provided with at least one concave cavity;

at least one bare chip 20 to be packaged, the bare chip 20 to be packaged and the cavity correspond to each other one by one, the bare chip 20 to be packaged is located in the corresponding cavity, the front surface of the bare chip 20 to be packaged exposes the first encapsulating layer 30, and the front surface of the bare chip 20 is provided with a plurality of welding pads;

at least one pin 411 fixed on the front surface of the dies 20, each pin 411 corresponding to one of the dies 20, the pin 411 electrically connected to the corresponding pad of the die 20;

and the conductive structure 60 is formed on the pin 411 and leads out a bonding pad of the bare chip.

In one embodiment, the semiconductor package structure further includes an adhesive layer 50. The adhesive layer 50 covers the exposed front surface of the die 20 and the exposed surface of the first encapsulant layer 30, and the adhesive layer 50 covers the surface and the side portions of the leads 411 to fix the leads 411.

In one embodiment, the semiconductor package structure further includes a dielectric layer 70. A dielectric layer 70 covers the exposed leadframe 40 and the surface of the conductive structure 60 facing away from the leadframe 40 exposes the dielectric layer 70. The dielectric layer 70 is used to protect the leads 411 and the conductive structure 60.

In one embodiment, referring to fig. 13, the semiconductor package structure further includes a redistribution layer 80, a conductive pillar 90, and a second encapsulant layer 91. Wherein, the redistribution layer 80 is formed on the dielectric layer 70, and the redistribution layer 80 is electrically connected to the conductive structure 60. The conductive post 90 is formed on the rewiring layer 80 to draw out the rewiring layer 80. The second encapsulant layer 91 encapsulates the exposed redistribution layer 80 and the dielectric layer 70, and encapsulates the side portions of the conductive posts 90, and the surface of the conductive posts 90 exposes the second encapsulant layer 91.

In one embodiment, the pins 411 are provided with through holes 412, the semiconductor package structure further includes a conductive material filled in the through holes 412, and the pins 411 are electrically connected to the pads of the die 20 through the conductive material in the through holes 412.

In the present application, the apparatus embodiments and the method embodiments may complement each other without conflict. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.

The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.