阅读说明：本技术 半导体封装方法及半导体封装结构 (Semiconductor packaging method and semiconductor packaging structure ) 是由 周辉星 于 2020-03-27 设计创作，主要内容包括：本申请提供一种半导体封装方法及半导体封装结构。其中,半导体封装方法包括在待封装的裸片正面形成保护层,将被动元件通过所述保护层层叠固定于所述待封装的裸片的正面,形成层叠组件；其中,所述被动元件远离所述裸片一侧的表面被所述保护层所包覆；将所述层叠组件贴设于载板上,所述待封装的裸片的正面朝向所述载板；形成包封层,所述包封层至少包封所述待封装的裸片。(The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the steps of forming a protective layer on the front surface of a bare chip to be packaged, and laminating and fixing a passive element on the front surface of the bare chip to be packaged through the protective layer to form a laminated assembly; wherein, the surface of the passive element far away from the bare chip side is covered by the protective layer; the stacked assembly is pasted on a carrier plate, and the front surface of the bare chip to be packaged faces the carrier plate; forming an encapsulation layer encapsulating at least the die to be packaged.)

1. A semiconductor packaging method, comprising:

forming a protective layer on the front surface of a bare chip to be packaged, and laminating and fixing a passive element on the front surface of the bare chip to be packaged through the protective layer to form a laminated assembly; wherein, the surface of the passive element far away from the bare chip side is covered by the protective layer;

the stacked assembly is pasted on a carrier plate, and the front surface of the bare chip to be packaged faces the carrier plate;

forming an encapsulation layer encapsulating at least the die to be packaged.

2. The semiconductor packaging method according to claim 1, wherein the forming a protection layer on the front surface of the die to be packaged, and laminating and fixing a passive component on the front surface of the die to be packaged through the protection layer to form a laminated assembly comprises:

applying the protective layer on the front side of the die to be packaged;

preliminarily heating the protective layer to reduce the viscosity of the protective layer, and applying the passive element to a preset position of the front side of the die to be packaged through the protective layer;

and continuously heating the protective layer, wherein the protective layer is heated and solidified, and the passive element is solidified to the front side of the bare chip to be packaged along with the protective layer.

3. The semiconductor packaging method of claim 1, wherein before forming a protective layer on a front side of a die to be packaged, the method comprises:

and thinning the bare chip to be packaged by grinding the back surface of the bare chip to be packaged.

4. The semiconductor packaging method of claim 1, wherein after forming the encapsulation layer, the method comprises:

and stripping the carrier plate.

5. The semiconductor packaging method of claim 4, wherein after peeling the carrier plate, the method comprises:

forming a wiring structure on the surface of the protective layer far away from the bare chip; the wiring structure is electrically connected with the electric connecting keys of the passive element and electrically connected with the welding pads on the front surface of the bare chip.

6. The semiconductor packaging method according to claim 5, wherein after peeling the carrier board and before forming the wiring structure, the method comprises:

forming a first protective layer opening and a second protective layer opening on the protective layer; the first protective layer opening is positioned at the electric connection key on the passive element, and the second protective layer opening is positioned at the welding pad of the bare chip;

filling a first conductive medium in the first protective layer opening to form a first electric connection part, and filling a second conductive medium in the second protective layer opening to form a second electric connection part; the wiring structure is electrically connected with the electric connecting key of the passive element through the first electric connecting part and is electrically connected with the welding pad on the front surface of the bare chip to be packaged through the second electric connecting part.

7. The method of claim 1, wherein after forming the stacked assembly and before attaching the stacked assembly to a carrier, the method comprises:

respectively forming a first protective layer opening and a second protective layer opening on the protective layer; the first protective layer opening corresponds to the electrical connection key of the passive element, and the second protective layer opening corresponds to the bonding pad on the front surface of the bare chip to be packaged.

8. The semiconductor packaging method of claim 7, wherein after forming a first protective layer opening and a second protective layer opening in the protective layer, respectively, the method comprises:

and filling a second conductive medium in the second protective layer opening to form a second electric connection part which can be electrically connected with the welding pad on the front surface of the bare chip to be packaged.

9. The semiconductor packaging method of claim 8, wherein after forming the encapsulation layer, the semiconductor packaging method comprises:

stripping the carrier plate;

and forming a wiring structure on the surface of the protective layer far away from the bare chip, wherein the wiring structure is electrically connected with the electric connecting key of the passive element through the first electric connecting part and is electrically connected with the welding pad on the front surface of the bare chip through the second electric connecting part.

10. The semiconductor packaging method according to claim 5 or claim 9, wherein the wiring structure includes a wiring layer and a third electrical connection provided on a surface of the wiring layer on a side away from the die, and after the wiring structure is formed on the surface of the protective layer away from the die, the method includes:

and forming a dielectric layer on the wiring structure, wherein the dielectric layer can cover the exposed wiring layer, part of the third electric connection part and the exposed protective layer, and the surface of the third electric connection part, which is far away from the wiring layer, exposes the dielectric layer.

11. A semiconductor package, comprising:

the encapsulating layer is provided with a plurality of concave cavities;

the die and the passive element are arranged in a stacked mode, the die and the passive element are located in the cavity, the back face of the die faces the bottom of the cavity, and the passive element is arranged on the front face of the die;

the protective layer covers the exposed part of the passive element and the exposed part of the front surface of the bare chip, a first protective layer opening and a second protective layer opening are formed on the protective layer, the first protective layer opening is positioned at the position of the electric connection key on the passive element, and the second protective layer opening is positioned at the position of the welding pad of the bare chip;

and the wiring structure is positioned on the surface of one side of the protective layer, which is far away from the bare chip, and is used for leading out the bonding pads on the front surface of the bare chip and the electric connection keys of the passive element.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.

Background

At present, in a semiconductor packaging process, a die and a passive component, such as a capacitor, a resistor, an inductor, etc., are often required to be packaged in a package to perform a certain function. With the miniaturization and light weight of electronic devices, chip packages with compact structure and small volume are favored by more and more markets, and how to further reduce the volume of such chip packages including bare chips and passive components is a problem to be solved in the art.

Disclosure of Invention

One aspect of the present application provides a semiconductor packaging method, comprising:

forming a protective layer on the front surface of a bare chip to be packaged, and laminating and fixing a passive element on the front surface of the bare chip to be packaged through the protective layer to form a laminated assembly, wherein the surface of the passive element, which is far away from the bare chip, is covered by the protective layer;

the stacked assembly is pasted on a carrier plate, and the front surface of the bare chip to be packaged faces the carrier plate;

forming an encapsulation layer encapsulating at least the die to be packaged.

Optionally, the forming a protection layer on the front surface of the die to be packaged, and stacking and fixing the passive element on the front surface of the die to be packaged through the protection layer to form a stacked assembly includes:

applying the protective layer on the front side of the die to be packaged;

preliminarily heating the protective layer to reduce the viscosity of the protective layer, and applying the passive element to a preset position of the front side of the die to be packaged through the protective layer;

and continuously heating the protective layer, wherein the protective layer is heated and solidified, and the passive element is solidified to the front side of the bare chip to be packaged along with the protective layer.

Optionally, before forming the protective layer on the front side of the die to be packaged, the method includes:

and thinning the bare chip to be packaged by grinding the back surface of the bare chip to be packaged.

Optionally, after forming the encapsulation layer, the method comprises:

and stripping the carrier plate.

Optionally, after peeling off the carrier plate, the method includes:

forming a wiring structure on the surface of the protective layer far away from the bare chip; the wiring structure is electrically connected with the electric connecting keys of the passive element and electrically connected with the welding pads on the front surface of the bare chip.

Optionally, after the carrier board is peeled off and before the wiring structure is formed, the method includes:

forming a first protective layer opening and a second protective layer opening on the protective layer; the first protective layer opening is positioned at the electric connection key on the passive element, and the second protective layer opening is positioned at the welding pad of the bare chip;

filling a first conductive medium in the first protective layer opening to form a first electric connection part, and filling a second conductive medium in the second protective layer opening to form a second electric connection part; the wiring structure is electrically connected with the electric connecting key of the passive element through the first electric connecting part and is electrically connected with the welding pad on the front surface of the bare chip to be packaged through the second electric connecting part.

Optionally, after the stacked assembly is formed and before the stacked assembly is attached to the carrier plate, the method includes:

respectively forming a first protective layer opening and a second protective layer opening on the protective layer; the first protective layer opening corresponds to the electrical connection key of the passive element, and the second protective layer opening corresponds to the bonding pad on the front surface of the bare chip to be packaged.

Optionally, after forming a first protection layer opening and a second protection layer opening on the protection layer, respectively, the method includes:

and filling a second conductive medium in the second protective layer opening to form a second electric connection part which can be electrically connected with the welding pad on the front surface of the bare chip to be packaged.

Optionally, after forming the encapsulation layer, the semiconductor packaging method includes:

stripping the carrier plate;

and forming a wiring structure on the surface of the protective layer far away from the bare chip, wherein the wiring structure is electrically connected with the electric connecting key of the passive element through the first electric connecting part and is electrically connected with the welding pad on the front surface of the bare chip through the second electric connecting part.

Optionally, the wiring structure includes a wiring layer and a third electrical connection portion provided on a surface of the wiring layer on a side away from the die, and after the wiring structure is formed on the surface of the protection layer away from the die, the method includes:

and forming a dielectric layer on the wiring structure, wherein the dielectric layer can cover the exposed wiring layer, part of the third electric connection part and the exposed protective layer, and the surface of the third electric connection part, which is far away from the wiring layer, exposes the dielectric layer.

Another aspect of the present application provides a semiconductor package structure, including:

the encapsulating layer is provided with a plurality of concave cavities;

the die and the passive element are arranged in a stacked mode, the die and the passive element are located in the cavity, the back face of the die faces the bottom of the cavity, and the passive element is arranged on the front face of the die;

the protective layer covers the exposed part of the passive element and the exposed part of the front surface of the bare chip, a first protective layer opening and a second protective layer opening are formed on the protective layer, the first protective layer opening is positioned at the position of the electric connection key on the passive element, and the second protective layer opening is positioned at the position of the welding pad of the bare chip;

and the wiring structure is positioned on the surface of one side of the protective layer, which is far away from the bare chip, and is used for leading out the bonding pads on the front surface of the bare chip and the electric connection keys of the passive element.

According to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the bare chip and the passive element are stacked to form a compact structure, so that the overall occupied space of a product is reduced. And directly fix the passive component in the front of bare chip through the protective layer, and avoid fixing the passive component through the adhesive linkage, be favorable to attenuate holistic thickness of product to further realize reducing the whole occupation space's of product beneficial effect. The semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.

Drawings

Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure.

Fig. 2 is a process flow diagram for preparing a die in a semiconductor packaging method according to an exemplary embodiment of the present disclosure.

Fig. 3(a) -3 (j) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a semiconductor package structure obtained by the semiconductor packaging method according to an exemplary embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

In a semiconductor packaging process, a die and a passive component, such as a capacitor, a resistor, an inductor, etc., are often packaged in a package to perform a certain function. With the miniaturization and light weight of electronic devices, chip packages with compact structure and small volume are favored by more and more markets, and how to further reduce the volume of such chip packages including bare chips and passive components is a problem to be solved in the art.

In order to solve the above-mentioned problems in the semiconductor packaging technology, the present application provides a semiconductor packaging method. In the packaging process, firstly, a protective layer is formed on the front surface of a bare chip to be packaged, and a passive element is fixedly laminated on the front surface of the bare chip to be packaged through the protective layer to form a laminated assembly; wherein, the surface of the passive element far away from the bare chip side is covered by the protective layer. And secondly, the laminated assembly is attached to a carrier plate, and the front surface of the bare chip to be packaged faces the carrier plate. Finally, an encapsulating layer is formed, and the encapsulating layer is formed on the back side of the bare chip to be packaged and the exposed carrier plate. According to the above embodiment of the application, the stacked arrangement of the bare chip and the passive element forms a compact structure, so that the overall occupied space of the product is reduced. And directly fix the passive component in the front of bare chip through the protective layer, and avoid fixing the passive component through the adhesive linkage, be favorable to attenuate holistic thickness of product to further realize reducing the whole occupation space's of product beneficial effect. The semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.

As shown in fig. 1, fig. 2, fig. 3(a) -fig. 3(j), and fig. 4, the present disclosure provides a semiconductor packaging method and a semiconductor packaging structure.

Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the semiconductor packaging method includes the following steps 101 to 105:

step 101: forming a protective layer on the front surface of a bare chip to be packaged, and laminating and fixing a passive element on the front surface of the bare chip to be packaged through the protective layer to form a laminated assembly; wherein, the surface of the passive element far away from the bare chip side is covered by the protective layer.

Step 103: and pasting the laminated assembly on a carrier plate, wherein the front surface of the bare chip to be packaged faces the carrier plate.

Step 105: forming an encapsulation layer encapsulating at least the die to be packaged.

In the semiconductor package structure formed by the semiconductor package method in this embodiment, the stacked arrangement of the bare chip and the passive element forms a compact structure, so that the overall occupied space of the product is reduced. And directly fix the passive component in the front of bare chip through the protective layer, and avoid fixing the passive component through the adhesive linkage, be favorable to attenuate holistic thickness of product to further realize reducing the whole occupation space's of product beneficial effect. The semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.

In this embodiment, before step 101, the semiconductor packaging method may include: a die is provided.

In some embodiments, a semiconductor wafer 100 is first provided, as shown in fig. 2. The front surface of the semiconductor wafer 100, i.e. the front surface corresponding to the die 201 to be packaged, has an insulating layer 2011 and a pad 2012, and the pad 2012 is used for making an electrical connection with the outside. The front side of the die 201 to be packaged is the active side of the die 201 to be packaged. Next, the semiconductor wafer 100 is cut along the dicing streets by using a cutting device, so as to obtain a plurality of dies 201 to be packaged. The cutting process can be mechanical cutting or laser cutting.

Optionally, in some embodiments, before the semiconductor wafer 100 is diced, the back surface of the semiconductor wafer 100, that is, the back surface of the die 201 to be packaged, may be ground to reduce the thickness of the die 201 to be packaged, so as to reduce the thickness of the final overall package structure, and further achieve the beneficial effect of reducing the overall occupied space.

In step 101, as shown in fig. 3(a), the following steps S1, S2 and S3 may be specifically included:

in step S1, a protective layer 202 is applied on the front side of the die 201 to be packaged. The protective layer 202 is made of an insulating material. The protective layer material may include BCB benzocyclobutene, PI polyimide, PBO Polybenzoxazole (Polybenzoxazole), epoxy, abf (ajinomoto buildup film), polymer matrix dielectric film, organic polymer film, or other material with similar insulating and structural properties. It may also be an organic/inorganic composite material such as a resin polymer to which inorganic particles are added. Optionally, the protective layer is preferably selected to be compatible with chemical cleaning, polishing, etc. The protective layer 202 may be formed on the die 201 to be packaged by Lamination (Coating), Coating (Coating), Printing (Printing), or the like.

After preliminary heating the protective layer 202 in step S2, the passive element 301 is applied to a predetermined position of the front surface of the die 201 to be packaged through the protective layer 202. Since the viscosity of the protective layer 202 after the preliminary heating is first reduced, the protective layer 202 has strong fluidity at this time. Therefore, the passive element 301 is placed at a predetermined position on the front surface of the die 201 to be packaged, and the preliminarily heated protective layer 202 originally between the passive element 301 and the die 201 to be packaged can be pushed away by pressing so that the passive element 301 can be placed at the predetermined position on the front surface of the die 201 through the protective layer having reduced viscosity.

In step S3, the protection layer 202 is continuously heated, and as the heating progresses, the protection layer 202 is heated and cured, and the passive component 301 is cured to the front side of the die 201 to be packaged along with the protection layer 202.

Since the passive device is often smaller, and in this embodiment, the passive device 301 is significantly smaller than the die 201, after the passive device 301 is placed on the front surface of the die 201, the viscosity of the material of the protection layer 202 is lower before the temperature of the protection layer reaches the curing temperature, and a portion of the protection layer 202 can move to cover the surface of the passive device 301. Therefore, after the protective layer 202 is continuously heated and cured, when the passive element 301 is cured to the front surface of the die 201 to be packaged along with the protective layer 202, the surface of the passive element 301 away from the die 202 is also covered by the protective layer 202, and actually, it can be understood that the surface of the passive element 301, other than the surface attached to the front surface of the die 201 to be packaged, is covered by the protective layer 202. In the present application, the surface 2002 of the protective layer 202, which is the side away from the die 201, is entirely planar for subsequent mounting.

It should be noted that the temperature for preliminary heating of the material used for the protective layer of the present application is generally selected to be lower than the curing temperature of the material used for the protective layer. According to the rheological characteristics of the protective layer material in the curing process, the viscosity of the protective layer material is reduced along with the increase of the temperature during the primary heating, and when the temperature is increased to the curing temperature or above, the protective layer material can generate cross-linking among molecules, so that the viscosity is increased, and the curing effect is achieved. In the preliminary heating of the protective layer, the preliminary heating is such that the temperature of the protective layer should be below and controllable below the curing temperature of the material layer. Optionally, when the protective layer is initially heated, the initial heating allows the temperature of the protective layer to be controlled at or near the lowest viscosity that allows the protective layer material to cure rheologically. Thus, it is convenient to arrange the passive element. While after the passive component is applied to the predetermined location of the die, heating may continue to raise the temperature of the protective layer to or above its curing temperature. The time length of the preliminary heating, the temperature reached by the protective layer after the preliminary heating, the time length of the continuous heating, and the temperature reached by the protective layer after the continuous heating can all be determined according to the specific application environment, such as the material of the protective layer and the corresponding curing temperature thereof.

As can be seen from the above, the step of laminating the passive element 301 to the die 201 to be packaged and the step of forming the protective layer 202 on the die 201 to be packaged are performed simultaneously.

After step 101 is completed and before step 103 is entered, the semiconductor packaging method may include steps 1021 and 1022 as follows:

in step 1021, a first passivation opening 2021 and a second passivation opening 2022 are formed on the passivation layer respectively as shown in fig. 3 (b). The first passivation opening 2021 corresponds to the electrical connection key of the passive device 301, such that the electrical connection key of the passive device 301 is exposed from the first passivation opening 2021. The second passivation opening 2022 corresponds to at least the pads on the front surface of the die 201 to be packaged or the lines led out from the pads, so that the pads on the front surface of the die 201 to be packaged or the lines led out from the pads are exposed from the second passivation opening 2022.

For the material of the passivation layer 202 being a laser-reactive material, the first passivation opening 2021 and the second passivation opening 2022 can be formed by laser patterning. For the material of the passivation layer 202 is a photosensitive material, the first passivation opening 2021 and the second passivation opening 2022 can be formed by photolithography and patterning. The shape of the first passivation opening 2021 may be round, but may also be other shapes such as oval, square, line, etc. Of course, the shape of the second passivation opening 2022 may be round, but may also be other shapes such as oval, square, line, etc.

In step 1022, as shown in fig. 3(c), the first passivation opening 2021 is filled with a first conductive medium to form a first electrical connection portion 2031 capable of being electrically connected to the electrical connection key of the passive device 301, so that the electrical connection key of the passive device 301 is led out to the surface of the passivation layer 202; and filling a second conductive medium in the second protective layer opening 2022 to form a second electrical connection portion 2032 capable of electrically connecting with the pad 2012 on the front surface of the die 201 to be packaged, so that the pad 2012 on the front surface of the die 201 to be packaged is led out to the surface of the protective layer 202.

Optionally, in some embodiments, after the first passivation layer opening and the second passivation layer opening are formed, the first conductive medium may not be filled in the first passivation layer opening and the second conductive medium may not be filled in the second passivation layer opening, so that the plurality of first passivation layer openings and the plurality of second passivation layer openings are still in a hollow state after the stacked assembly formed in step 101 is subsequently mounted on the carrier board.

It should be noted that, in some other embodiments, after the step 101 is completed, the step 103 may be directly performed without forming the first passivation opening and the second passivation opening.

In step 103, as shown in fig. 3(d), the stacked assembly formed in step 101 is mounted on the carrier 200, the front surface of the die 201 to be packaged faces the carrier 200, and the surface of the passive component 301 having the electrical connection keys also faces the carrier 200.

Alternatively, the stack may be attached to the carrier plate by an adhesive layer (not shown). The adhesive layer is used for bonding the laminated assembly, and the adhesive layer can be made of a material easy to peel off so as to peel off the carrier plate and the laminated assembly in a subsequent process, for example, a thermal separation material which can lose viscosity by heating can be used.

Optionally, in other embodiments, the adhesive layer may have a two-layer structure, i.e., a thermal separation material layer and an adhesive layer, the thermal separation material layer is adhered to the carrier plate 200 and loses its viscosity when heated, so as to be able to be peeled off from the carrier plate 200, and the adhesive layer has an adhesive material layer and can be used for adhering the stacked assembly. After the stacked assembly is peeled off the carrier 200, the adhesion layer thereon can be removed by chemical cleaning. In one embodiment, the adhesive layer may be formed on the carrier 200 by lamination, printing, or the like.

It should be noted that, as shown in fig. 3(d), the stacked assemblies are placed on the carrier 200 according to a predetermined arrangement position, for convenience of expression, only one stacked assembly is shown in the drawing, and actually, a plurality of stacked assemblies on the carrier 200 are arranged according to a predetermined position.

It can be understood that, in one packaging process, there may be a plurality of dies and passive components to be packaged, that is, a plurality of stacked assemblies are mounted on the carrier 200 at the same time for packaging, and after the packaging is completed, the stacked assemblies are cut into a plurality of packages; one package may include one or more stacked components, and the position of one or more stacked components may be set according to the needs of an actual product.

In step 105, an encapsulating layer 204 is formed on the carrier 200, wherein the encapsulating layer 204 can encapsulate the back surface of the die 201 to be packaged, the side surface of the protection layer 202 and the exposed carrier. For the carrier with the adhesive layer, the encapsulating layer can cover the back surface of the die 201 to be packaged and the exposed adhesive layer, and of course, if the surface of the carrier 200 close to the stacked assembly still has an exposed area, the exposed area can also be covered by the encapsulating layer. As shown in fig. 3(e), the encapsulating layer 204 completely encapsulates the carrier 200 and the stacked assembly to reconstruct a flat plate structure, so that the wiring and packaging can be continued on the reconstructed flat plate structure after the carrier 200 is peeled off.

In one embodiment, the encapsulating layer 204 may be formed by laminating an epoxy resin film or an abf (ajinomoto build film), or by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound.

The upper surface 2041 of the encapsulating layer 204 away from the carrier 200 is substantially flat and parallel or substantially parallel to the surface of the carrier 200. The thickness of encapsulant layer 204 may be thinned by grinding or polishing surface 2041. In some alternative embodiments, the thickness of the encapsulation layer 204 may be thinned to the back side of the die 201.

When encapsulating with the encapsulating layer 204, since the encapsulating layer needs to be molded under high pressure during molding, the encapsulating material easily penetrates between the carrier 200 and the die 201 during the molding process. The protection layer 202 is disposed to prevent the encapsulant from penetrating the surface of the die 201 and the passive component, and even if the encapsulant penetrates the surface of the die 201 and the passive component, the surface of the protection layer 202 can be directly processed by a chemical method or a grinding method after being peeled off from the carrier, without directly contacting the front surface of the die and the surface of the passive component having the electrical connection key, so that the circuit structure and the passive component on the front surface of the die 201 cannot be damaged.

Further, in some embodiments, as shown in fig. 3(f), the carrier sheet 200 may be peeled off after the formation of the encapsulant layer 204. For the adhesive layer having the thermal decomposition film between the stacked assembly and the carrier 200, the adhesive layer may be reduced in viscosity after being heated by heating, so as to peel off the carrier 200. By peeling carrier sheet 200 with the heated adhesive layer, damage to the laminate assembly during peeling can be minimized. Of course, in other embodiments, the carrier board 200 can be directly and mechanically peeled off.

After the carrier 200 is peeled off, the lower surface of the encapsulating layer 204 and the surface of the passivation layer 202 originally facing the carrier 200 may be exposed. For the protective layer 202 formed with the first and second electrical connection portions 2031 and 2032, surfaces of the first and second electrical connection portions 2031 and 2032 remote from the die 201 may also be exposed. Thus, after the carrier board 200 is peeled off, a flat panel structure including the die 201, the passive component 301, the passivation layer 202, the first electrical connection portion 2031 and the second electrical connection portion 2032 disposed on the passivation layer, and the encapsulating layer 204 is obtained. On the formed flat plate structure, wiring can be performed according to actual conditions, so that the bare chip 201 and the passive element 301 are electrically connected with the outside. Optionally, electrical connections between the dies 2012 and the passive components 301 may also be formed. Similar structural elements can be obtained after the carrier board 200 is peeled off, where the passivation layer 202 is only formed with the first passivation opening 2021 and the second passivation opening 2022 without forming the first electrical connection portion 2031 and the second electrical connection portion 2032, and the passivation layer 202 is not formed with the first passivation opening 2021 and the second passivation opening 2022, which is not described herein again.

In the above-described embodiment of the present application, after the carrier board 200 is peeled off, the surface of the protection layer 202 is exposed, and the stacked assembly is attached to the carrier board 200 through the adhesive layer having the thermal release material layer and the adhesion layer, which is also present on the surface of the protection layer 202, and the adhesion layer can be removed by a chemical method. The protection layer 202 can also protect the passive element 301 and the surface of the die 201 from damage when the adhesion layer is chemically removed. After the adhesive layer is completely removed, if the encapsulating material is infiltrated in the prior art, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated. Without the protective layer 202, the surfaces of the die 201 and the passive element 301 cannot be treated by chemical or polishing to prevent the circuit on the front surface of the die 201 and the passive element 301 from being damaged.

Further, a wiring structure may be formed on a surface of the protection layer 202 away from the die 201. The wiring structure can be electrically connected with the electrical connection keys of the passive component 301 and the bonding pads on the front surface of the die 201, so as to lead out the electrical connection keys of the passive component 301 and the bonding pads on the front surface of the die 201.

For the protective layer 202 formed with the first electrical connection portion 2031 and the second electrical connection portion 2032 before the stacked assembly is attached to the carrier board 200, the step of forming the wiring structure may include: as shown in fig. 3(g), a wiring layer 206 having conductive traces is formed. The wiring layer 206 is formed on the surface of the passivation layer 202 and the surface of the encapsulation layer 204 on the same side as the surface of the passivation layer 202. The wiring layer 206 is electrically connected to the first electrical connection portion 2031 and the second electrical connection portion 2032, and is electrically connected to the passive element 301 through the first electrical connection portion 2031 and electrically connected to the die 201 through the second electrical connection portion 2032. Further, as shown in fig. 3(h), a third electrical connection portion 207 is formed in the wiring layer 206. After that, as shown in fig. 3(i), a dielectric layer 208 is formed on the surfaces of the wiring layer 206 and the third electrical connection portion 207. The dielectric layer 208 may be formed to a thickness such that the surface of the third electrical connection portion 207 is just exposed; the dielectric layer 208 may cover all exposed surfaces of the encapsulating layer 204, the passivation layer 202 and the wiring layer 206, and then be thinned to the surface of the third electrical connection portion 207. In this process, the conductive member of the wiring structure includes the wiring layer 206 and the third electrical connection portion 207.

The third electrical connection portion 207 is preferably circular, but may be other shapes such as a rectangle and a square, and the third electrical connection portion 207 is electrically connected to the wiring layer 206. Specifically, the third electrical connection portion 207 may be formed in the wiring layer 206 by photolithography and plating.

In another embodiment, after the wiring layer 206 is formed, a dielectric layer 208 is formed on the wiring layer 206 and the exposed passivation layer 202 and the exposed encapsulating layer 204, the dielectric layer 208 has a dielectric layer opening, and then a third electrical connection portion 207 electrically connected to the wiring layer 206 is formed in the dielectric layer opening of the dielectric layer 208. In this process, the conductive member of the wiring structure includes the wiring layer 206 and the third electrical connection portion 207.

In yet another embodiment, the dielectric layer opening of the dielectric layer may not be filled, i.e. the third electrical connection portion 207 electrically connected to the wiring layer 206 is not formed, so that the pad or the connection point of the wiring layer of the completed package is exposed from the dielectric layer opening. In this process, the conductive member of the wiring structure includes only the wiring layer 206.

In one embodiment, the dielectric layer 208 may be formed by Lamination (plating), Molding (Molding) or Printing (Printing), and preferably an epoxy compound is used.

It should be noted that, for the passivation layer 202 to form only the first passivation opening 2021 and the second passivation opening 2022 without forming the first electrical connection portion 2031 and the second electrical connection portion 2032 before attaching the stacked assembly to the carrier 200, after peeling off the carrier 200 and before forming the wiring structure, it is necessary to fill the first conductive medium in the first passivation opening to form the first electrical connection portion, and fill the second conductive medium in the second passivation opening to form the second electrical connection portion. And then, forming a wiring structure on the surface of the protective layer far away from the bare chip. The wiring structure is electrically connected with the electric connecting key of the passive element through the first electric connecting part and is electrically connected with the welding pad on the front surface of the bare chip to be packaged through the second electric connecting part. The structure, specific arrangement and connection relationship of the wiring structure can refer to the above description, and are not repeated herein.

In addition, for the passivation 202 not having the first passivation opening 2021 and the second passivation opening 2022 before attaching the stacked assembly to the carrier 200, after peeling the carrier 200 and before forming the wiring structure, the first passivation opening and the second passivation opening need to be formed on the passivation. The first protection layer opening is located at the position of the electrical connection key on the passive element, and the second protection layer opening is located at the position of the welding pad of the bare chip. And then, filling a first conductive medium in the first protective layer opening to form a first electric connection part, and filling a second conductive medium in the second protective layer opening to form a second electric connection part. And then, forming a wiring structure on the surface of the protective layer far away from the bare chip. The wiring structure is electrically connected with the electric connecting key of the passive element through the first electric connecting part and is electrically connected with the welding pad on the front surface of the bare chip to be packaged through the second electric connecting part. The structure, specific arrangement, connection relationship, and the like of the first electrical connection portion, the second electrical connection portion, and the wiring structure can refer to the above description, and are not repeated herein. Further, in some embodiments, repeated routing may be performed outside of the routing structure, such as one or more routing layers may be formed outside of the dielectric layer in the same manner to achieve multi-layer routing of the product.

In this embodiment, since the resist opening is already formed in the resist layer 202, at least the resist opening can be directly seen when the first wiring layer 206 is formed, and thus, the wiring layer 206 can be aligned more accurately when formed.

Further, after the package of the wiring structure is formed, as shown in fig. 3(j), the entire package structure is cut into a plurality of packages, i.e., semiconductor package structures, by laser or mechanical cutting, and the structure of the formed semiconductor package structure is shown in fig. 4.

Fig. 4 is a schematic structural diagram of a semiconductor package structure obtained by the semiconductor packaging method according to an exemplary embodiment of the present application. As shown in fig. 4, the semiconductor package structure includes:

the encapsulating layer 204 is provided with a plurality of concave cavities.

The semiconductor device comprises a bare chip 201 and a passive element 301 which are arranged in a stacked mode, wherein the bare chip 201 and the passive element 301 are located in a cavity, the back surface of the bare chip 201 faces the bottom of the cavity, and the passive element 301 is arranged on the front surface of the bare chip 201.

The passivation layer 201 covers the exposed portion of the passive device 301 and the exposed portion of the front surface of the die 201, and the passivation layer 202 has a first passivation opening 2021 and a second passivation opening 2022, the first passivation opening 2021 is located at the electrical connection key on the passive device 301, and the second passivation opening 2022 is located at the pad of the die.

And the wiring structure is positioned on the surface of the side of the protective layer 202 far away from the bare chip 201 and is used for leading out a bonding pad on the front surface of the bare chip 201 and an electrical connection key of the passive element 301.

In this way, the semiconductor package structure of the present embodiment forms a compact structure by stacking the bare chip and the passive element, thereby reducing the overall occupied space of the product. And directly fix the passive component in the front of bare chip through the protective layer, and avoid fixing the passive component through the adhesive linkage, be favorable to attenuate holistic thickness of product to further realize reducing the whole occupation space's of product beneficial effect. The semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.

The passive element 301 in the semiconductor package is smaller than the die 201, and the projection of the passive element 301 on the front side of the die 201 is located within the outer perimeter of the die 201.

In some embodiments, the wiring structure includes: a routing layer 206 with conductive traces. The wiring layer 206 is formed on the surface of the passivation layer 202 and the surface of the encapsulation layer 204 on the same side as the surface of the passivation layer 202. The wiring layer 206 is electrically connected to the passive element 301 through the first electrical connection portion 2031 in the first passivation opening 2021, and is electrically connected to the die 201 through the second electrical connection portion 2032 in the second passivation opening 2022.

Further, the wiring structure may further include a dielectric layer 208. The dielectric layer 208 is formed on the wiring layer 206 and the exposed passivation layer 202 and the exposed encapsulating layer 204, and has a dielectric layer opening. The dielectric layer opening is provided with a third electrical connection portion 207 electrically connected to the wiring layer 206.

In another embodiment, the wiring structure includes more wiring layers to achieve multi-layer wiring of the product.

In the present embodiment, each structural element of the semiconductor package structure can refer to the related description of the corresponding structural element in the semiconductor package method, which is not repeated herein.

In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.