阅读说明：本技术 半导体结构的制作方法 (Method for manufacturing semiconductor structure ) 是由 周鸿儒 彭远清 郭俊铭 于 2021-05-26 设计创作，主要内容包括：半导体结构的制作方法,包括制作半导体结构,其包括外延成长第一组成与第二组成交错的多个层状物的堆叠。层状物的该堆叠延伸越过半导体基板的第一区与第二区。蚀刻半导体基板的第二区中的层状物的堆叠以形成开口。进行钝化制程以将氯导向开口的至少一表面。在进行钝化制程之后,成长外延衬垫层于开口中。(A method of fabricating a semiconductor structure includes fabricating a semiconductor structure including epitaxially growing a stack of layers having first and second compositions that are interleaved. The stack of layers extends across a first region and a second region of the semiconductor substrate. The stack of layers in the second region of the semiconductor substrate is etched to form an opening. A passivation process is performed to direct chlorine to at least one surface of the opening. After the passivation process is performed, an epitaxial liner layer is grown in the opening.)

1. A method for fabricating a semiconductor structure, comprising:

epitaxially growing a stack of layers of alternating first and second compositions, the stack of layers extending across a first and second region of a semiconductor substrate;

etching the stack of layers in the second region of the semiconductor substrate to form an opening;

performing a passivation process to guide chlorine to at least one surface of the opening; and

after the passivation process is performed, an epitaxial liner layer is grown in the opening.

Technical Field

Embodiments of the present invention relate to methods of fabricating semiconductor structures, and more particularly, to passivating exposed surfaces of openings prior to an epitaxial process.

Background

The electronic industry continues to demand smaller and faster electronic devices that support more sophisticated functions. In view of the foregoing, there is a continuing trend in the semiconductor industry to produce low cost, high performance, and low power integrated circuits. Semiconductor integrated circuit dimensions (e.g., minimum feature sizes) may be reduced to achieve these remote goals, thereby improving throughput and reducing associated costs. However, the scaling down of the dimensions tends to increase the complexity of the semiconductor fabrication process. In order to realize the continued progress of semiconductor integrated circuits and device units, similar progress in semiconductor manufacturing processes and techniques is also needed.

Although planar transistors continue to meet the technological requirements of many device types, multi-gate devices have recently been introduced to increase gate-channel coupling, reduce off-state current, and reduce short channel effects to improve gate control. One of the multiple gate devices is a finfet. Finfet devices are known by the name fin structures that are formed on and extend from a substrate and may be used to form channels for field effect transistors. Another multi-gate device is a fully-wrapped-gate transistor, which may partially address performance challenges associated with finfet transistors. The name of the all-around gate device comes from the fact that its gate structure can extend and completely surround the channel, which can provide more electrostatic control than a finfet. Finfet and wrap-around gate devices are compatible with existing cmos processes (e.g., processes for planar transistors), and their three-dimensional structure maintains gate control and mitigates short channel effects while allowing for large scale reductions. Generally, finfet devices may be implemented when planar device performance does not meet performance requirements. Fully-wrapped-gate devices may be implemented when the finfet does not meet performance requirements. Substrates must therefore be prepared for a variety of device types. The prior art cannot completely meet the requirements of all aspects.

Disclosure of Invention

An embodiment of the invention describes a method for fabricating a semiconductor structure. The method includes epitaxially growing a stack of layers of alternating first and second compositions. The stack of layers extends across the first and second regions of the semiconductor substrate. The method includes etching the stack of layers in the second region of the semiconductor substrate to form an opening. A passivation process is performed to direct chlorine to at least one surface of the opening. After the passivation process is performed, an epitaxial liner layer is grown in the opening.

Another embodiment described herein includes a method of fabricating a semiconductor structure that includes forming a stack including a first silicon germanium layer and a second silicon germanium layer. And forming a first silicon layer between the first silicon-germanium layer and the second silicon-germanium layer. Etching a first region of the stack includes removing portions of each of the first silicon layer, the first silicon germanium layer, and the second silicon germanium layer to provide an opening, and a first sidewall of the opening includes the first silicon germanium layer, the first silicon layer, and the second silicon germanium layer. A passivation process is performed on the first sidewall to form a passivated sidewall. Epitaxially growing a silicon layer on the passivated sidewalls.

Yet another embodiment described herein includes a method of fabricating a semiconductor structure that includes growing an epitaxial stack of interleaved layers of silicon and silicon germanium on a substrate. An opening is etched in the epitaxial stack to expose a surface of the substrate. Directing hydrogen chloride toward a substrate having an etched opening; and growing a first portion of the silicon epitaxial material in the opening at a first temperature and a second portion of the silicon epitaxial material on the first portion at a second temperature after introducing the hydrogen chloride, the second temperature being greater than the first temperature.

Drawings

Fig. 1 is a flow chart of a method of fabricating a multi-gate device or portion thereof in one or more embodiments of the invention.

FIGS. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9B, 10A, 10B, 11A, and 11B are isometric views of a semiconductor structure 200 formed according to the method of FIG. 1, in one embodiment.

Fig. 2B, 3B, 4B, 5B, 6B, 7B, and 8B are cross-sectional views of a semiconductor structure 200 formed according to the method of fig. 1, in one embodiment.

FIG. 12 is a diagram of certain steps of the method of FIG. 1, in one embodiment.

Wherein the reference numerals are as follows:

t: transition period

X-X': first section plane

100: method of producing a composite material

102, 104, 106, 108, 110, 112, 114, 116, 118, 120: step (ii) of

200: semiconductor structure

202: substrate

202: surface of the substrate

204: epitaxial stack

206, 208, 702: epitaxial layer

210: hard mask layer

212: first region

214: second region

302: opening of the container

502: side wall

602: epitaxial liner layer

902, 904: fin unit

906: shallow trench isolation structure

1002, 1004: gate stack

1006: dielectric layer

1102: interlayer dielectric layer

1104: source/drain structure

1108: metal grid

Detailed Description

The following detailed description can be read in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is noted that the various structures are for illustrative purposes only and are not drawn to scale as is normal in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of presentation.

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The particular arrangements and examples shown are meant to simplify the present invention and not to limit the invention. For example, the formation of a first element on a second element is described as including direct contact between the two elements, or the separation of additional elements other than direct contact between the two elements. Moreover, various examples of the invention may be repeated using the same reference numerals for brevity, but elements having the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same correspondence.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.

It is noted that some device types according to some embodiments of the present invention are multi-gate transistors. The gate structure of the multi-gate transistor is formed on at least two sides of the channel region. These multi-gate devices may include p-type metal oxide semiconductor multi-gate devices or n-type metal oxide semiconductor multi-gate devices. Certain examples herein may be considered as finfet transistors due to fin structures. In the embodiments described herein, the multi-gate transistor may be considered to be a fully-wrapped-gate device. The gate structure or portions thereof included in the all-around gate device may be formed on four sides of the channel region (e.g., around a portion of the channel region). In the embodiments described herein, the channel regions of the devices may be located in nanowire channels, rod-like channels, and/or other suitable channel arrangements. In the embodiments described herein, a device may have one or more channel regions (e.g., nanowires) associated with a single continuous gate structure. However, one of ordinary skill in the art will appreciate that the present teachings can be used with a single channel (e.g., a single nanowire) or any number of channels. One of ordinary skill in the art will appreciate that embodiments of the present invention may also be used to advantage in other exemplary semiconductor devices.

Embodiments of the invention provide many more advantages than the prior art, but it is understood that other embodiments may provide different advantages, all of which need not be described herein, and all of which need not have a particular advantage. In embodiments of the present invention, process flows and device structures are provided that may include nanowire or nanosheet devices, planar devices, and/or finfet devices on a single substrate. For example, n-type devices (e.g., n-type field effect transistors) and p-type devices (e.g., p-type field effect transistors) may be formed. It is certain that in some embodiments, a p-type field effect transistor device may comprise a nanowire or nanosheet device, while an n-type field effect transistor device may comprise a finfet device. In some embodiments, the n-type field effect transistor and the p-type field effect transistor devices may each comprise nanowire or nanosheet devices, while other n-type field effect transistors and/or p-type field effect transistors having different performance requirements may comprise fin field effect transistors or planar devices. Embodiments of the present invention introduce devices and methods that prepare substrates to define regions for forming such devices. In other words, the devices and methods herein may provide a region on a substrate to form a nanowire or nanosheet device and another region on the substrate to form a finfet device (or planar transistor or other device type of nanowire that does not require a wrap-around gate). The methods provided herein can improve the composition of layers formed on a substrate to reduce unwanted species from these regions of the substrate. Other embodiments and advantages of the present invention will be readily apparent to those of ordinary skill in the art in view of the teachings herein.

Fig. 1 shows a method 100 of fabricating a semiconductor, which includes fabricating a semiconductor structure. The method 100 may be used to form a semiconductor structure that includes a plurality of semiconductor devices including a multi-gate device. The term "multi-gate device" as used herein refers to a device (e.g., a semiconductor transistor) having at least some gate material on multiple sides of at least one channel. In some examples, the multi-gate device may be considered a fully-wrapped-gate device with gate material on at least four sides of the at least one channel. The channel regions can be considered "nanowires," which comprise channel regions of various geometries (e.g., cylinders or rods) and various dimensions. Furthermore, the multi-gate devices of some examples may include finfet devices, or a combination of finfet devices and fully-wrapped-gate devices. It should be understood that the steps of the method 100 may be used in a cmos process flow and are described only briefly herein. Additional steps may be performed before, after, and/or during the method 100.

Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9B, 10A, 10B, 11A, and 11B are isometric views of a semiconductor structure 200 at various stages of the method 100 of fig. 1, in one embodiment. Fig. 2B, 3B, 4B, 5B, 6B, 7B, and 8B are cross-sectional views corresponding to the respective isometric views described above, which are cross-sectional views taken along a first cross-section X-X' (see fig. 2A) of the semiconductor structure 200 according to one embodiment. Fig. 12 is a diagram corresponding to the steps of the method 100 of fig. 1, in one embodiment.

It should be understood that portions of the semiconductor structure 200 may be fabricated by cmos process flow, and thus some processes are described briefly herein. In addition, the semiconductor structure 200 may include various other devices and structures, such as other types of implanted regions, devices (e.g., additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory, and/or other logic circuits, or the like), although the associated drawings and description have been simplified to facilitate an understanding of the inventive concepts of the present embodiments. In some embodiments, the semiconductor structure 200 formed in the method 100 may include interconnected semiconductor devices (e.g., transistors, including p-type field effect transistors, n-type field effect transistors, or the like). Moreover, it should be noted that the process steps of the method 100 (including any description in conjunction with the figures) are exemplary only and are not limiting to the embodiments of the present invention to those not actually recited in the claims.

The method 100 begins with step 102 providing a substrate. As an example shown in FIG. 2, step 102 of one embodiment provides a substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon substrate. The substrate 202 may comprise a variety of layers, which may include conductive or insulating layers formed on a semiconductor substrate. The substrate 202 may comprise a variety of doping configurations depending on design requirements known in the art.

In one embodiment, the substrate 202 includes a first region 212 for devices in a first configuration and a second region 214 for devices in a second configuration. For example, the first region 212 of one embodiment is designed for a fully-wrapped-gate transistor, while the second region 214 is designed for a finfet transistor. In another embodiment, the first region 212 is designed for a fully-wrapped-gate transistor, while the second region 214 is designed for a planar transistor. Although the exemplary figures show a single second region 214 and one or more first regions 212, it should be noted that any number of first and second regions may be present on the substrate 202.

As described above, the substrate 202 may be silicon. However, the substrate 202 may also comprise other semiconductors such as germanium, silicon carbide, silicon germanium, or diamond. The substrate 202 may instead comprise a semiconductor compound and/or a semiconductor alloy. In addition, the substrate 202 may optionally include an epitaxial layer, which may be stressed to enhance performance, may include a silicon-on-insulator structure, and/or may have other suitable enhancements.

In one embodiment, the method 100 proceeds with an anti-punch through implant at step 102. For example, an anti-punch through implant may be performed in the region below the channel region of the device to avoid punch through or unwanted diffusion. In some embodiments, one or more anti-punch through implants may be performed for each of the n-type device region and the p-type device region.

As shown in fig. 1, step 104 of the method 100 is followed by growing one or more epitaxial layers on the substrate to form an epitaxial stack. In some embodiments, a hard mask is formed on the epitaxial stack. As an example, as shown in fig. 2, step 104 of one embodiment may form an epitaxial stack 204 on a substrate 202. The epitaxial stack 204 may include an epitaxial layer 206 of a first composition sandwiched between epitaxial layers 208 of a second composition. The first composition and the second composition may be different. In one embodiment, the epitaxial layer 206 of the first composition may be a silicon germanium layer and the epitaxial layer 208 of the second composition may be a silicon layer. However, other embodiments may include other first and second compositions that differ in oxidation rate and/or etch selectivity.

The silicon layer in the first region 212, such as the epitaxial layer 208 or portions thereof, may form a channel region of a wrap-around gate transistor of the semiconductor structure 200. For example, a silicon layer, such as the epitaxial layer 208, may be considered a "nanowire" that may be used to form a channel region of a fully-wrapped-gate device, such as an n-type or p-type fully-wrapped-gate device formed in the first region 212, as described below. These nanowires may also be used to form part of the source/drain structure of a fully wrapped-around gate device, as described below. Similarly, the term "nanowire" as used herein refers to a cylindrical or other arrangement of semiconductor layers, such as rods. The sandwiched silicon germanium layer, such as epitaxial layer 206, in the channel region of the fully wrapped-around gate in first region 212 may then be removed. The silicon germanium layer, such as epitaxial layer 206, may thus serve as a placeholder for a subsequently formed gate structure that may encapsulate the silicon layer, such as epitaxial layer 208, in first region 212.

It is noted that fig. 2A and 2B illustrate six sige layers, such as epitaxial layer 206, and six si layers, such as epitaxial layer 208, for illustrative purposes only and are not intended to limit embodiments of the present invention to the extent not actually recited in the claims. It is understood that any number of epitaxial layers may be formed in epitaxial stack 204, and the number of epitaxial layers depends on the number of channel regions required for the fully-wrapped-gate device. In some embodiments, the number of silicon layers, such as epitaxial layers 208, is between 4 and 10. Although the uppermost layer of the epitaxial stack 204 is shown as a silicon layer, such as the epitaxial layer 208, other arrangements are possible.

In some embodiments, each silicon germanium layer, such as epitaxial layer 206, is about 4nm to 8nm thick. In some embodiments, the thickness of the silicon germanium layer, such as epitaxial layer 206, is substantially uniform. In some examples, the topmost layer of the epitaxial stack 204 (e.g., the top silicon layer such as the epitaxial layer 208) may be thicker than the remaining epitaxial layer, which may mitigate possible loss of the topmost layer of the epitaxial stack 204 during subsequent chemical mechanical polishing processes, as described below. In some embodiments, each silicon layer, such as epitaxial layer 208, is about 5nm to 8nm thick. In some embodiments, the thickness of the stacked silicon layers, such as epitaxial layer 208, is substantially uniform. In some embodiments, a silicon layer, such as epitaxial layer 208, may serve as a channel region for a multi-gate device (e.g., a wrap-around gate device) subsequently formed in first region 212, and its thickness is selected depending on device performance considerations. A silicon germanium layer, such as epitaxial layer 206, may be used to define the gap distance between adjacent channel regions for subsequently formed multi-gate devices, with the thickness selected based on device performance considerations.

For example, the method of epitaxially growing the layer of the epitaxial stack 204 may be a molecular beam epitaxy process, a metal organic chemical vapor deposition process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer, such as a silicon layer (epi layer 208), may comprise the same material as the substrate 202. In some embodiments, the epitaxially grown epitaxial layers 206 and 208 may comprise different materials than the substrate 202. In various embodiments, epitaxial layer 206 (e.g., a silicon germanium layer) and epitaxial layer 208 (e.g., a silicon layer) are substantially dopant-free (e.g., with an extrinsic dopant concentration of about 0 cm)^-3To about 1x10¹⁷cm^-3) In which the epitaxial growth process is carried outThe doping is not performed intentionally.

As shown in fig. 2A and 2B, in one embodiment, step 104 may form a hard mask layer 210 on the epitaxial stack 204. In some embodiments, hard mask layer 210 comprises an oxide layer (e.g., an electrooxidation layer comprising silicon oxide), and a nitride layer (e.g., a pad nitride layer comprising silicon nitride) formed on the oxide layer. In some embodiments, the oxide layer may comprise thermally grown oxide, chemical vapor deposited oxide, and/or atomic layer deposited oxide, while the nitride layer may comprise a nitride layer deposited by chemical vapor deposition or other suitable technique. For example, the thickness of the oxide layer is between approximately 5nm and approximately 40 nm. In some embodiments, the thickness of the nitride layer may be between approximately 20nm to approximately 160 nm. The hard mask layer 210 may serve as a mask unit for a subsequent patterning step, as described below.

It is noted that in step 102 and in the example of fig. 2A and 2B, the epitaxial stack 204 may extend over the entire substrate 202. For example, the epitaxial stack 204 of some embodiments spans the entire semiconductor wafer.

Step 106 of the method 100 is followed by an etching process to etch the second region of the substrate. Step 106 may include a photolithography process to define the second region of the substrate and protect the first region of the substrate from etching. In addition, the second region of an embodiment can be defined as a region where a non-fully-wrapped-gate transistor (e.g., a planar transistor or a fin-shaped field effect transistor) is formed. FIGS. 3A and 3B illustrate step 106 of one embodiment. In some embodiments, a photolithography step may be performed to form a patterned photoresist layer to expose the second region 214. For example, some embodiments of the photolithography process may include forming a photoresist layer on the semiconductor structure 200, exposing the photoresist to a pattern (e.g., a first region of a mask), performing a post-exposure bake process, and developing the photoresist to form a patterned photoresist layer. In some embodiments, after forming the patterned photoresist layer, an etch process may be performed to etch the hard mask layer 210 and the epitaxial stack 204 in the second region 214, while the patterned photoresist layer and/or the hard mask layer 210 still masks the first region 212. In some examples, the etching process may include wet etching, dry etching, or a combination thereof. Furthermore, some embodiments may employ one or more different etch chemistries to effectively etch each hard mask layer 210 and the epitaxial layers 206 and 208 of the epitaxial stack 204. The epitaxial stack 204 in the second region 214 is etched away, forming an opening 302 in the second region 214. In one embodiment, a first dry etch process (e.g., arsenic etch or fluorocarbon etch) is performed to form the opening 302, followed by a second wet etch. In some examples, an etching process may be performed until the surface of the underlying substrate 202 in the second region 214 is exposed. The photoresist may be removed after the etching process, and the removal process may employ solvent, photoresist stripping, ashing, or other suitable techniques.

Step 108 of the method 100 is followed by a passivation process. The passivation process may mitigate unwanted phenomena such as diffusion of species into certain regions on the bottom and sidewalls of the opening provided in step 106. In one embodiment, the passivation process inhibits germanium diffusion from a silicon germanium layer, such as epitaxial layer 206, to a silicon layer, such as epitaxial layer 208, and/or to exposed surfaces of substrate 202. The passivation process may direct hydrogen chloride (e.g., in a gaseous state) toward the substrate, such as toward the opening provided by the etching of step 106. In some embodiments, a hydrogen carrier gas may be introduced to accompany the hydrogen chloride. The hydrogen chloride may passivate the sidewalls of the opening formed by the etching of step 106, as described below.

The dangling bonds of the sidewalls of the opening and/or the exposed substrate surfaces may be reduced to passivate these surfaces. Specifically, some embodiments have the silicon layer, such as epitaxial layer 208, and exposed substrate 202 comprised of silicon, which after etching creates dangling bonds. If left unreleased, these dangling bonds may attract germanium (as the temperature increases) that diffuses from an adjacent silicon germanium layer, such as epitaxial layer 206. The passivation process may prevent or mitigate germanium diffusion from the sige layer, such as epi layer 206, to the si layer, such as epi layer 208, and the upper surface of substrate 202. The mechanism of the passivation process will be described in detail below, but is not limited to any particular theory.

In one embodiment, step 108 is shown in fig. 4A and 4B, a passivation process introduces a hydrogen chloride species into the opening 302 in the substrate 202 in the second region 214. An epitaxial process (e.g., such as a molecular beam epitaxy process, an mocvd process, and/or other suitable epitaxial growth processes, as described below in steps 110 and/or 112) may be performed by introducing a hci species, such as a gas, into the chamber

The passivation process temperature of step 108 may be increased during processing (e.g., providing hci) until the chamber or substrate reaches a temperature suitable for performing step 110. In one embodiment, the temperature at which passivation is achieved may increase by approximately 35% to 60%. In one embodiment, the temperature of the passivation process may be between approximately 325 ℃ to 650 ℃.

While the above-described hydrogen chloride provides a chlorine source, it is understood that other chlorine sources are possible. In another embodiment of the method 100, step 108 may be omitted. For example, after etching the opening, an epitaxial liner layer of step 110 described below may be grown.

In one embodiment, the introduction of hydrogen chloride, particularly chlorine atoms, passivates the sidewalls of the opening 302 and/or the bottom surface of the opening 302. The chlorine atoms adhere to dangling bonds on the silicon layer, such as the epitaxial layer 208 and/or the silicon material on the lower surface of the opening (e.g., the exposed surface of the substrate 202). This results in bonding sites that are not available for germanium bonding when germanium in the sige is dissociated and diffused by the subsequent high temperature processes. As shown in fig. 5A and 5B, the processed sidewall 502 and the processed substrate surface 202A are passivated. The treated sidewall 502 and the substrate surface 202A contain chlorine to bond to dangling bonds of a silicon layer, such as the epitaxial layer 208. Germanium tends to be trapped by chlorine and out of the chamber, e.g., rather than diffusing into the silicon layer, e.g., epitaxial layer 208, and may be removed from the chamber, e.g., as exhaust products. In some embodiments, germanium diffusion increases with increasing temperature, and thus providing passivation of step 108 prior to the temperature-increasing epitaxial growth process of step 110 and/or step 112 advantageously limits germanium diffusion at increasing temperatures.

In some embodiments, the passivation process of step 108 and step 110 may be performed in-situ. The transition period between steps 108 and 110, which will be described in detail below, may include a period of time during which the chlorine source and the silicon source are introduced into the chamber.

In one embodiment, the passivation process pressure of step 108 is substantially similar to the epitaxial growth pressure of step 110. In one embodiment, the pressure may range from approximately 75Torr to approximately 350 Torr. In other embodiments, the pressure may be between approximately 275Torr to approximately 325 Torr. In one embodiment, the pressure is adjusted to properly restrict the reflow of the sige layer, such as the epi layer 206.

In some embodiments, the passivation process of step 108 additionally forms sidewalls 502 of the opening 302 (which have edges of the silicon layer, e.g., epitaxial layer 208), and also slightly etches sidewalls of the silicon germanium layer, e.g., epitaxial layer 206. A method of etching sidewalls of a silicon germanium layer, such as epitaxial layer 206, may employ a germanium source (e.g., germanium dichloride) in the exhaust product.

Step 110 of the method 100 is followed by an initial epitaxial growth process to form an epitaxial liner layer. An epitaxial liner layer is formed on the substrate in the second region, particularly in the openings provided by etching the second region in step 106. In one embodiment, step 108 is followed by step 110. In another embodiment, step 108 may be omitted and the etching of step 106 may be followed by step 110. Still another embodiment may omit step 110 and the method 100 may proceed to step 112. As shown in fig. 6A and 6B, in one embodiment, the step 110 may form an epitaxial liner layer 602 on the substrate 202 in the opening 302 in the second region 214. As shown in fig. 6A and 6B, in one embodiment, the step 110 may form an epitaxial liner layer 602 on the substrate 202 in the opening 302 in the second region 214. In one embodiment, an epitaxial liner layer 602 is formed on the processed substrate surface 202A and sidewalls 502 defining the opening 302. In some embodiments, the epitaxial liner layer 602 comprises silicon, although other materials are possible. In one embodiment, the silicon of the epitaxial liner layer 602 is not intentionally doped.

In one embodiment, the epitaxial layer 602 may be epitaxially grown by a molecular beam epitaxy process, a metal organic chemical vapor deposition process, and/or other suitable epitaxial growth processes. In some embodiments, the step of epitaxially growing the epitaxial liner 602 and the passivation process of step 108 may be performed in situ. In some embodiments, the epitaxial liner layer 602 and the substrate 202 may comprise the same material. In some embodiments, the epitaxial liner layer 602 and the substrate 202 may comprise different materials. As described above, the epitaxial liner layer 602 of at least some examples comprises epitaxially grown silicon. In various embodiments, the epitaxial liner layer is substantially free of dopants (ratio)E.g. with an applied dopant concentration of about 0cm^-3To about 1x10¹⁷cm^-3) For example, doping is not intentionally performed during the epitaxial growth process.

In one embodiment, the process temperature of step 110 is lower than the growth temperature of step 112, as described below. In one embodiment, the growth temperature of step 110 is between approximately 500 ℃ and 600 ℃. Fig. 12 shows that the process temperature for forming the epitaxial liner layer may be increased relative to the temperature during the passivation process of step 108. In one embodiment, the process pressure of step 110 is substantially similar to the pressure of step 108. In one embodiment, the pressure may be between approximately 75torr and approximately 350 torr. In another embodiment, the pressure is between approximately 275torr and 325 torr. In one embodiment, the pressure is adjusted to properly restrict the reflow of the sige layer, such as the epi layer 206.

In one embodiment, the passivated sidewalls 502 refer to silicon germanium layers adjacent to silicon layers, such as epitaxial layer 208, such as germanium of epitaxial layer 206, that are not connected to silicon layers, such as epitaxial layer 206, because chlorine has passivated the surface (e.g., chlorine has filled dangling bonds), as described above with respect to fig. 5A and 5B.

In one embodiment, the temperature of step 110 is sufficient to desorb chlorine from the passivated sidewalls 502 (e.g., breaking bonds of silicon dichloride), desorb any chlorine from a germanium-containing surface (e.g., germanium dichloride), and/or desorb hydrogen from silicon or germanium material on the sidewalls of the opening 302. The peak desorption of silicon dichloride from silicon may be the highest temperature, and thus this temperature may be the lowest temperature required to remove species in step 110 (e.g., prior to growing an epitaxial liner layer). Thus, in one embodiment, the epitaxial growth process temperature of step 110 is substantially equal to or greater than 586 ℃ (e.g., the desorption peak temperature for desorbing silicon dichloride from silicon).

In one embodiment, the method of forming the epitaxial liner layer 602 includes introducing a reactive gas, such as dichlorosilane, to form the silicon epitaxial liner layer 602. Although dichlorosilane is one of the silicon sources, other silicon precursors may be used in other embodiments in addition to or in place of dichlorosilane. In one embodiment, the processes of steps 108 and 110 may be performed in situ, and the reactive gas may be changed from hci in the passivation process of step 108 to dichlorosilane in the epitaxial growth of step 110. It is noted, however, that a transition period may be provided between steps 108 and 110.

The transition period between steps 108 and 110 includes flowing the chlorine source and the silicon source simultaneously. In one embodiment, the volume ratio (e.g., sccm) of the chlorine source (e.g., hci reactive gas) to the silicon source (e.g., dichlorosilane) during the transition period is approximately 1 to approximately 8. This can be viewed as flowing hydrogen chloride simultaneously with a silicon source (e.g., silicon dichloride) during the transition period. In one embodiment, the volume of dichlorosilane gas in the transition period is substantially the same as the volume of dichlorosilane during the epitaxial growth process of step 110. The temperature of the transition period may be the same as step 110, such as a transition period that occurs after the temperature of step 108 ramps up as shown in FIG. 12. In one embodiment, a carrier gas of hydrogen is used throughout steps 108 and 110 (including the transition period). Fig. 12 indicates the transition period T.

After the transition period, the flow rate of the silicon source (e.g., dichlorosilane) may be maintained for growing the epitaxial liner layer 602 in step 110. In one embodiment, the silicon source flow rate may be between approximately 300sccm and 500sccm to grow an epitaxial liner layer.

In one embodiment, the epitaxial liner layer 602 may be between 1nm and 10 nm. In another example, the epitaxial liner layer 602 may be between 1nm and 5 nm. In yet another embodiment, the epitaxial liner layer 602 may be between approximately 1nm and 2 nm.

Step 112 of the method 100 is followed by growing an epitaxial layer on the substrate in the second region. As shown in fig. 7A and 7B, step 112 of one embodiment forms an epitaxial layer 702 on the substrate 202 in the opening 302 remaining in the second region 214. In some embodiments, epitaxial layer 702 comprises silicon, although other embodiments are possible. In one embodiment, the silicon of epitaxial layer 702 is not intentionally doped. The epitaxial layer 702, or portions thereof, may form a channel region of a finfet device of the semiconductor structure 200. For example, epitaxial layer 702 may be used to form a channel region of a finfet device in second region 214, as described below. The epitaxial layer 702, or portions thereof, may form a channel region of a planar transistor device of the semiconductor structure 200.

In one embodiment of the present invention, the substrate is,the epitaxial layer 702 may be grown by a molecular beam epitaxy process, a metal organic chemical vapor deposition process, and/or other suitable epitaxial growth processes. In some embodiments, the step of epitaxially growing the epitaxial layer 702 and the step of growing the epitaxial liner layer 602 may be performed in situ. In some embodiments, the epitaxial layer 702 may comprise the same material as the substrate 202 and/or the epitaxial liner layer 602. In some embodiments, the epitaxial layer 702 and the substrate 202 may comprise different materials. As described above, the epitaxial layer 702 in at least some examples includes epitaxially grown silicon. In some embodiments, epitaxial layer 702 may instead comprise other materials such as germanium, semiconductor compounds (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), semiconductor alloys (e.g., silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and/or indium gallium arsenide phosphide), or combinations thereof. In various embodiments, epitaxial layer 702 is substantially free of dopants (e.g., the concentration of the added dopants deviates from about 0 cm)^-3To about 1x10¹⁷cm^-3). For example, doping is not intentionally performed during the epitaxial growth process. In other embodiments, epitaxial layer 702 or portions thereof may be doped in situ or implanted thereafter. In one embodiment, the epitaxial layer 702 and the epitaxial liner layer 602 are the same composition. In other embodiments, the same composition is silicon.

In one embodiment, the process temperature of step 112 is greater than the growth temperature of step 110. In one embodiment, the growth temperature of step 112 is about 20% to 45% higher than the temperature of step 110. In one embodiment, the first temperature is between approximately 500 ℃ and 650 ℃, and the second temperature is between approximately 675 ℃ and 850 ℃. As shown in fig. 12, the process temperature increases between the growth of step 110 and the growth of step 112. In one embodiment, the process pressure (torr) of step 112 is less than the growth pressure of step 110. In one embodiment, the pressure may be reduced during and/or after the epitaxial growth in step 110 and/or the epitaxial growth in step 112 (e.g., the torr is ramped down). In one embodiment, the pressure of step 112 is reduced to approximately 2% to 10% of the pressure of step 110. For example, the pressure of step 112 of one embodiment drops to approximately 5torr to 25 torr. Although fig. 12 shows a step-like increase in temperature at step 112, the temperature at step 110 may be gradually increased (e.g., during the growth of the second half of the epitaxial layer) in other embodiments.

Step 114 of the method 100 performs a chemical mechanical polishing process. Step 114 of one embodiment relates to the example of fig. 8A and 8B, which may be performed by a chemical mechanical polishing process. In some embodiments, the chemical mechanical polishing process removes the hard mask layer 210 from the first region 212 and planarizes the upper surface of the semiconductor structure 200. The chemical mechanical polishing process may remove the top of the epitaxial layer 702.

In some embodiments, step 116 of the method 100 is followed by patterning and forming the fin cell. As shown in fig. 9A and 9B, step 116 of some embodiments forms a plurality of fin cells 902 and 904 extending from substrate 202 in first region 212 and second region 214, respectively. Fig. 9A shows the first region 212, and fig. 9B shows the second region 214. Specifically, a plurality of fin cells 902 are formed in first region 212 (fig. 9A), and a plurality of fin cells 904 are formed in second region 214 (fig. 9B). In various embodiments, each fin cell 902 includes a substrate portion formed from substrate 202, and a portion of each epitaxial layer of epitaxial stack 204 includes epitaxial layers 206 and 208. In some embodiments, each fin cell 904 includes a substrate portion formed from substrate 202, and a portion of epitaxial layer 702.

The fin elements 902 and 904 may be fabricated using any suitable process, including photolithography and etching processes. The photolithography process may include forming a photoresist layer on the substrate 202 (e.g., on the semiconductor structure 200 of fig. 8A and 8B), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask unit including the photoresist. In some embodiments, the method of patterning the photoresist to form the mask unit may employ an electron beam lithography process. A mask unit may then be used to protect some areas of substrate 202 and the layers formed thereon, and an etch process may (i) form trenches in unprotected areas of first region 212 and through epitaxial layers 206 and 208 into substrate 202, thereby leaving a plurality of extended fin units 902, and (ii) form trenches in unprotected areas of second region 214 and through epitaxial layer 702 into substrate 202, thereby leaving a plurality of extended fin units 904. The trench etching process may be dry etching (e.g., reactive ion etching), wet etching, and/or other suitable processes. In various embodiments, the trench may be filled with a dielectric material to form a shallow trench isolation structure to sandwich the fin.

In some embodiments, the dielectric material filling the trench may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, low-k dielectric layers, combinations thereof, and/or other suitable materials known in the art. In various embodiments, the dielectric material is deposited by a chemical vapor deposition process, an sub-pressure chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, and/or other suitable processes. In some embodiments, the dielectric material (and subsequently formed shallow trench isolation structures) may include a multi-layer structure, such as with one or more liner layers.

In some embodiments where isolation structures such as shallow trench isolations are formed, the deposited dielectric material may be thinned and planarized (e.g., chemical mechanical polishing) after the dielectric material is deposited. The chemical mechanical polishing process may planarize the upper surface of the semiconductor structure 200 to form a shallow trench isolation structure. In various embodiments, the shallow trench isolation structures sandwiching the fin cell are then recessed. After recessing the sti structures 906, the fin cells 902 and 904 may extend above the sti structures 906, as shown in fig. 9A and 9B. In some embodiments, the recess process may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, the etch time may be controlled to control the recess depth, resulting in the exposed upper portions of fin cells 902 and 904 having a desired height. In some embodiments, each layer of the epitaxial stack 204 and substantially all of the epitaxial layer 702 may be exposed.

It is noted that in one embodiment shown in fig. 9A and 9B, a wrap-around gate transistor is formed in the first region 212 and a finfet is formed in the second region 214. However, other device types, such as channel regions without fin dominance, may be used instead or in addition.

Step 118 of the method 100 is followed by forming a sacrificial layer or structure, particularly a dummy gate structure. Although embodiments of the present invention relate to replacement gate processes (e.g., gate post-processing) that form dummy gate structures for wrap-around gate devices and finfets and then replace the dummy gate structures, other arrangements are possible.

As shown in fig. 10A and 10B, step 118 of some embodiments forms a gate stack (e.g., a dummy gate stack) 1002 on fin cell 902 in first region 212 and forms a gate stack (e.g., a dummy gate stack) 1004 on fin cell 904 in second region 214. In one embodiment, gate stacks 1002 and 1004 are sacrificial gate stacks that are later removed, as described below.

Some embodiments may form the dielectric layer 1006 before forming the gate stacks 1002 and 1004. In some embodiments, dielectric layer 1006 is deposited over substrate 202 and fin cells 902 and 904, including in the trenches between adjacent fin cells 902 and 904. In some embodiments, the dielectric layer 1006 may comprise silicon oxide, silicon nitride, a high-k dielectric material, or other suitable materials. In various embodiments, the dielectric layer 1006 may be deposited by a chemical vapor deposition process, an under-pressure chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other suitable processes. For example, dielectric layer 1006 may be used to prevent damage to fin cells 902 and 904 from subsequent processes, such as subsequent dummy gate formation steps.

In some embodiments employing gate post-processing, the gate stacks 1002 and 1004 are dummy gate stacks, and subsequent processing stages of the semiconductor structure 200 may replace the dummy gate stacks with final gate stacks. Specifically, the subsequent process stages may replace the gate stacks 1002 and 1004 with high-k dielectric layers and metal gates, which may be arranged and positioned similarly to the gate stacks 1002 and 1004. The portions of fin cells 902 and 904 under gate stacks 1002 and 1004 may be considered as channel regions. For example, gate stacks 1002 and 1004 may also define source/drain regions of fin cells 902 and 904, such as regions adjacent to and on both sides of the channel region.

After forming the gate stacks 1002 and 1004, step 120 of the method 100 then forms additional structures of the device (as is known in the art). The processes include, but are not limited to, forming spacer cells on sidewalls of the gate stacks and forming source/drain structures adjacent to the channel region of each fin cell 902 and 904. In some embodiments, the source/drain structure may be formed by epitaxially growing a semiconductor layer on the exposed fin cells 902 and 904 in the source/drain regions. Other embodiments may recess fin cells 902 and 904 in the source/drain regions prior to growing the source/drain structures. After forming the source/drain structures, some embodiments method 100 includes forming an interlayer dielectric layer. In one embodiment, step 120 forms an interlayer dielectric 1102 over the substrate 202, as shown in FIGS. 11A and 11B. Some embodiments form a contact etch stop layer on the substrate 202 before forming the ild layer 1102.

In some embodiments, the material of the interlayer dielectric layer 1102 includes an oxide of tetraethoxysilane, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass, fluorosilicate glass, phosphosilicate glass, borosilicate glass, and/or other suitable dielectric materials. The interlayer dielectric 1102 may be deposited by a plasma enhanced chemical vapor deposition process or other suitable deposition technique. Fig. 11A and 11B show a source/drain structure 1104. It is noted that the source/drain structure 1104 may be appropriately doped to provide a p-type transistor or an n-type transistor. For example, the fully-wrapped-gate device of fig. 11A may be a p-type transistor or an n-type transistor, while the finfet device of fig. 11B may be of the same or different device type.

Some embodiments may perform a planarization process to expose the upper surfaces of the gate stacks 1002 and 1004 after depositing the inter-layer dielectric (and/or contact etch stop or other dielectric). Step 120 of the method 100 may then remove the dummy gate stack (see step 118). In some examples, the dummy gate (e.g., polysilicon gate) of the dummy gate stack may be initially removed from the fully-wrapped-around gate device in the first region 212 and the finfet device in the second region 214 by a suitable etch process.

Step 120 of one embodiment and some examples may then selectively remove the epitaxial layer in the channel region of the wrap-around gate device in the first region 212. This can be considered as a channel release step. Embodiments may remove selected epitaxial layers in the fin cell (such as the region of the fin or channel region on which the gate structure will be formed) in the trenches provided by the removal of the dummy gates. For example, the epitaxial layer 206 may be removed from the channel region and the channel region of the substrate 202. In some embodiments, the sige layer, such as the epi layer 206, may be removed by a selective wet etch process. In some embodiments, the selective wet etch includes ammonia and/or ozone. For example, the selective wet etch may comprise tetramethylammonium hydroxide. A silicon layer, such as epitaxial layer 208, remaining in the channel region of fin cell 902 of the wrap-around gate device may form the channel region.

After releasing the silicon layer, such as epitaxial layer 208, in the channel region of the wrap-around gate device, step 120 of method 100 may form the final gate structure. The final gate structure may be a stack of a high-k dielectric layer and a metal gate, although other compositions are possible. In some embodiments, the gate structure may form a gate associated with multiple channels. The multiple nanowires (silicon layer such as epitaxial layers 208, now with a gap between epitaxial layers 208) in the channel region of the wrap-around gate device of the first region 212 may provide the multiple channels. Similarly, the gate structure may be a stack of a high-k dielectric layer and a metal gate, which may be formed on the channel provided by the epitaxial layer 702 in the channel region of the finfet in the second region 214.

As an example, as shown in fig. 11A and 11B, step 120 of some embodiments forms a gate dielectric layer in the trench of the wrap-around gate device in the first region 212. The trenches are formed by removing the dummy gate and/or releasing the nanowire, as described above. In various embodiments, the gate dielectric layer includes an interfacial layer and a high-k gate dielectric layer formed on the interfacial layer. The high-k gate dielectric layer described herein includes a high-k (e.g., about 3.9 k greater than the dielectric constant of thermal silicon oxide) dielectric material.

In some embodiments, the interfacial layer may comprise a dielectric material such as silicon oxide, hafnium silicon oxide, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and/or other suitable methods. The high-k gate dielectric layer may comprise a high-k dielectric layer such as hafnium oxide. In other embodiments, the high-k gate dielectric layer may comprise other high-k dielectric layers, such as titanium dioxide, hafnium zirconium oxide, tantalum trioxide, hafnium silicate, zirconium dioxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum pentoxide, yttrium oxide, strontium titanate, barium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, aluminum trioxide, silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. The high-k gate dielectric layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, oxidation, and/or other suitable methods.

Metal gate 1108 also includes a metal layer formed on the gate dielectric layer of the wrap-around gate device (in first region 212) and on the gate dielectric layer of the finfet device (in second region 214). The metal layer may comprise a metal, a metal alloy, or a metal silicide. In addition, the method of forming the stack of the gate dielectric layer and the metal gate may include depositing a plurality of gate materials and one or more liner layers, and performing one or more cmp processes to remove excess gate materials and planarize the top surface of the semiconductor structure 200.

In some embodiments, the metal layer of the metal gate 1108 may comprise a single layer or a multi-layer structure, such as various combinations of metal layers having a selected work function (work function metal layers), liner layers, wetting layers, adhesion layers, metal alloys, or metal silicides that enhance device performance. For example, the metal layer may comprise titanium, silver, aluminum, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, copper, tungsten, rhenium, iridium, cobalt, nickel, other suitable metallic materials, or combinations thereof. In various embodiments, the metal layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, e-beam evaporation, or other suitable processes. In addition, the metal layers for the n-type field effect transistor and the p-type field effect transistor can be formed separately, so that different metal layers can be used for different types of field effect transistors. The metal layer may provide an n-type or p-type work function as a gate for a transistor, such as a wrap-around gate or a finfet device. In at least some embodiments, the metal layer may comprise a polysilicon layer. As for the step of forming the wrap-around gate device in the first region 212, the gate structure may include portions sandwiching each silicon layer, such as the epitaxial layer 208, and the silicon layers, such as the epitaxial layer 208, may each form a channel of the wrap-around gate device.

Subsequent processing of the semiconductor structure 200 may be performed to form a variety of structures and regions as is known in the art. For example, subsequent processing may form contact openings, contact metals, and various contact/via/line and multilevel interconnect structures (e.g., metal layers and interlevel dielectric layers) on the substrate 202 configured to connect various structures to form a functional circuit including one or more multi-gate devices. In other examples, the multilevel interconnects may include vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. Various interconnect structures may employ various conductive materials including copper, tungsten, and/or silicides. In one example, a damascene and/or dual damascene process may be used to form a copper-related multilevel interconnect structure. In addition, additional processes may be performed before, during, and after the method 100, and various embodiments of the method may replace or omit some of the process steps described above.

The method 100 of some embodiments may reduce and/or eliminate germanium diffusion into adjacent silicon materials, such as the substrate and the epitaxially stacked silicon layers. Without reducing germanium diffusion, germanium may diffuse to form residues on adjacent silicon. In particular, germanium contamination can adversely affect the silicon material (e.g., silicon layer such as epitaxial layer 208) that is then converted into the channel of the wrap-around gate device. For example, high temperatures, such as those used in epitaxial processes, may provide energy to the germanium atoms to overcome the diffusion barrier and bond to the silicon layer. In addition, germanium remaining on the silicon material may oxidize to form germanium oxide on the surface and degrade device performance. The method may be used in one or more steps to reduce the risk of germanium diffusion, such as the passivation step (step 108) and/or the epitaxial liner layer (step 110), which may be performed together or separately. As described above, step 110 may insert a thinner layer of silicon (e.g., at a lower temperature) to avoid germanium diffusion, and/or step 108 may provide a hci treatment to passivate the surface to reduce the presence of dangling bonds, thereby avoiding germanium bonding to the dangling bonds.

Thus, one embodiment of the present invention describes a method for fabricating a semiconductor structure. The method includes epitaxially growing a stack of layers of alternating first and second compositions. The stack of layers extends across the first and second regions of the semiconductor substrate. The method includes etching the stack of layers in the second region of the semiconductor substrate to form an opening. A passivation process is performed to direct chlorine to at least one surface of the opening. After the passivation process is performed, an epitaxial liner layer is grown in the opening.

In other embodiments, the method further comprises forming a channel of the wrap-around gate transistor using a second composition of the stack of layers in the first region of the semiconductor substrate. In one embodiment, the step of epitaxially growing a stack of alternating layers of a first composition and a second composition comprises growing a silicon germanium layer to epitaxially grow a plurality of epitaxial layers of the first composition; and growing the silicon layer to epitaxially grow a plurality of epitaxial layers of the second composition. In one embodiment, the method further comprises: additional epitaxial material is grown on the epitaxial liner layer. In one embodiment, the method further comprises forming a fin of additional epitaxial material, wherein the fin comprises a channel region of a finfet in the second region of the semiconductor substrate. In one embodiment, the step of growing the additional epitaxial material is performed at a first temperature, and the step of growing the epitaxial liner layer is performed at a second temperature, wherein the second temperature is lower than the first temperature. In one embodiment, the step of performing the passivation process includes bonding chlorine to the layer of the first composition and not to the layer of the second composition. In one embodiment, the step of performing the passivation process includes bonding chlorine to the layer of the first composition, and the first composition is silicon. In other embodiments, the second composition is silicon germanium. In some embodiments, the step of etching the opening exposes a surface of the semiconductor substrate in the second region. In some embodiments, the step of performing a passivation process includes directing chlorine toward the exposed surface of the semiconductor substrate.

Another embodiment described herein includes a method of fabricating a semiconductor structure that includes forming a stack including a first silicon germanium layer and a second silicon germanium layer. And forming a first silicon layer between the first silicon-germanium layer and the second silicon-germanium layer. Etching a first region of the stack includes removing portions of each of the first silicon layer, the first silicon germanium layer, and the second silicon germanium layer to provide an opening, and a first sidewall of the opening includes the first silicon germanium layer, the first silicon layer, and the second silicon germanium layer. A passivation process is performed on the first sidewall to form a passivated sidewall. Epitaxially growing a silicon layer on the passivated sidewalls.

In one embodiment, the passivation process includes introducing hydrogen chloride. In one embodiment, the step of epitaxially growing a silicon layer includes growing a first layer of silicon at a first temperature; and growing a second layer of silicon at a second temperature, the second temperature being greater than the first temperature. In one embodiment, the passivation process is performed at a third temperature, and the third temperature is lower than the first temperature and the second temperature. In one embodiment, the passivation temperature during the passivation process is increased from the third temperature to the first temperature.

Yet another embodiment described herein includes a method of fabricating a semiconductor structure that includes growing an epitaxial stack of interleaved layers of silicon and silicon germanium on a substrate. An opening is etched in the epitaxial stack to expose a surface of the substrate. Directing hydrogen chloride toward a substrate having an etched opening; and growing a first portion of the silicon epitaxial material in the opening at a first temperature and a second portion of the silicon epitaxial material on the first portion at a second temperature after introducing the hydrogen chloride, the second temperature being greater than the first temperature.

In other embodiments, at least one of the first portion and the second portion of the silicon epitaxial material is employed to form a fin of a finfet device. In one embodiment, epitaxially stacked silicon layers are employed to form the channel of the all-around gate device. In one embodiment, the step of directing hydrogen chloride to the substrate having the etched opening can bond chlorine atoms to the surface of the substrate.

The features of the embodiments described above are useful for understanding the present invention by those having ordinary skill in the art. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that these equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention, and that they may be changed, substituted, or altered without departing from the spirit and scope of the present invention.