阅读说明：本技术 一种降低抖动的数据发送器 (Data transmitter for reducing jitter ) 是由 不公告发明人 于 2021-07-30 设计创作，主要内容包括：本发明提供一种降低抖动的数据发送器,该降低抖动的数据发送器包括：串并转换模块、可控延时单元、数据驱动器、线性稳压器；串并转换模块的输出端与可控延时单元的第一输入端电连接；可控延时单元的输出端与数据驱动器的第一输入端电连接；可控延时单元的第二输入端与串并转换模块的第二输入端电连接；数据驱动器的输出端与可控延时单元的第三输入端电连接；数据驱动器的第二输入端与线性稳压器的输出端电连接；差分数据信号包括第一差分数据信号和第二差分数据信号。本发明能够降低电路抖动的大小,进而提高电路眼图性能。(The present invention provides a jitter-reduced data transmitter comprising: the device comprises a serial-parallel conversion module, a controllable delay unit, a data driver and a linear voltage stabilizer; the output end of the serial-parallel conversion module is electrically connected with the first input end of the controllable delay unit; the output end of the controllable delay unit is electrically connected with the first input end of the data driver; the second input end of the controllable delay unit is electrically connected with the second input end of the serial-parallel conversion module; the output end of the data driver is electrically connected with the third input end of the controllable delay unit; the second input end of the data driver is electrically connected with the output end of the linear voltage stabilizer; the differential data signals include a first differential data signal and a second differential data signal. The invention can reduce the circuit jitter and further improve the circuit eye pattern performance.)

1. A data transmitter for reducing jitter, comprising: the device comprises a serial-parallel conversion module, a controllable delay unit, a data driver and a linear voltage stabilizer;

the first input end of the serial-parallel conversion module is used for inputting parallel data signals;

the second input end of the serial-parallel conversion module is used for inputting a high-speed clock signal;

the output end of the serial-parallel conversion module is electrically connected with the first input end of the controllable delay unit and is used for outputting a serial data signal to the controllable delay unit according to the parallel data signal and the high-speed clock signal;

the output end of the controllable delay unit is electrically connected with the first input end of the data driver and is used for outputting a delayed serial data signal to the data driver according to the serial data signal;

a second input end of the controllable delay unit is electrically connected with a second input end of the serial-parallel conversion module, and the controllable delay unit is provided with the high-speed clock signal;

the output end of the data driver is electrically connected with the third input end of the controllable delay unit and is used for sampling the differential data signal output by the data driver according to the high-speed clock signal and sending the differential data signal to the controllable delay unit so as to adjust the delay size;

the second input end of the data driver is electrically connected with the output end of the linear voltage stabilizer and is used for transmitting power supply voltage to the data driver;

the differential data signals include a first differential data signal and a second differential data signal.

2. The jitter reduction data transmitter of claim 1, wherein the controllable delay element comprises a high speed comparator, a phase detector, a low pass filter, and a voltage controlled delay line;

a first input end of the high-speed comparator is electrically connected with an output end of the data driver, and a second input end of the high-speed comparator is electrically connected with a second input end of the serial-parallel conversion module;

the output end of the high-speed comparator is electrically connected with the first input end of the phase discriminator, and the second input end of the phase discriminator is electrically connected with the second input end of the serial-parallel conversion module;

the output end of the phase discriminator is electrically connected with the input end of the low-pass filter, and the output end of the low-pass filter is electrically connected with the first input end of the voltage-controlled delay line;

the second input end of the voltage-controlled delay line is electrically connected with the output end of the serial-parallel conversion module, and the output end of the voltage-controlled delay line is electrically connected with the first input end of the data driver.

3. The data transmitter of claim 2, wherein the phase detector comprises a binary phase detector and a time-to-digital converter, an output of the binary phase detector is electrically connected to an input of the low-pass filter, a first input of the binary phase detector is electrically connected to a second input of the serial-to-parallel conversion module, a second input of the binary phase detector is electrically connected to an output of the time-to-digital converter, and an input of the time-to-digital converter is electrically connected to an output of the high-speed comparator.

4. A jitter reducing data transmitter as claimed in claim 3, wherein the output of the data driver comprises a first output terminal and a second output terminal, both of which are electrically connected to the third input terminal of the controllable delay unit.

5. The jitter-reduced data transmitter of claim 4, wherein the third input terminal of the controllable delay unit comprises a first input terminal electrically connected to the first output terminal of the data driver and a second input terminal electrically connected to the second output terminal of the data driver;

the first input end and the second input end are both electrically connected with the first input end of the high-speed comparator.

6. The jitter reduced data transmitter of claim 1, wherein the output of the data driver is further electrically connected to a buffer unit.

7. The jitter reduced data transmitter of claim 1, wherein the circuit configuration of the jitter reduced data transmitter is a closed-loop feedback configuration.

Technical Field

The invention belongs to the technical field of signal processing and transmission in microelectronic technology, and particularly relates to a data transmitter for reducing jitter.

Background

With the continuous development of integrated circuit technology and process level, the sizes of transistors and devices on a chip are made smaller, the integration level of the chip is higher and higher, and the requirement on the data transmission speed of a circuit is higher and higher. These put higher demands on the output jitter of the data transmission circuit, so that the difficulty in designing the transmission circuit of the integrated circuit is greatly increased. Especially after entering a 28nm process node, the withstand voltage of a common IO device is reduced from the former 3.3V to 1.8V, the same power supply ripple means the reduction of the signal-to-noise ratio of a signal, and a new high-speed interface specification often requires higher-speed data transmission, so the requirement on an eye diagram is continuously increased.

ISI introduced by the data transmission circuitry when transmitting data occupies a significant fraction of the eye diagram. In the conventional circuit design as shown in fig. 1, a PLL inputs a clock clk with less jitter and better quality and a parallel data signal data [ x:0] of several bits for parallel-to-serial conversion, and the high-speed serial data signal data after parallel-to-serial conversion is transmitted to a data DRIVER and then differentially transmitted to a PAD through the data DRIVER. In order to meet the requirement of output jitter, the data DRIVER is generally supplied with power by a linear regulator LDO alone, and the quality of an output eye diagram is greatly influenced by whether the output voltage of the linear regulator LDO is stable or not. Because the data sent by the data transmitter is random, unlike the case of a single frequency such as a sending clock, the output voltage of the linear regulator LDO is affected by the pumping of the data DRIVER to generate a large power ripple, and the instability of the output voltage of the linear regulator LDO can cause a large inter-symbol interference ISI to an eye diagram. Because the traditional structure belongs to an open loop structure, no means is provided except for increasing the filter capacitance of the LDO (low dropout regulator), and the size of the ISI (inter-symbol interference) can be suppressed. It can be seen that the existing transmitter has the problem of poor circuit eye diagram performance.

Disclosure of Invention

The invention provides a data transmitter capable of reducing jitter, which aims to reduce the jitter of a circuit and further improve the eye diagram performance of the circuit.

The present invention is thus achieved, providing a data transmitter for reducing jitter, comprising: the device comprises a serial-parallel conversion module, a controllable delay unit, a data driver and a linear voltage stabilizer;

the first input end of the serial-parallel conversion module is used for inputting parallel data signals;

the second input end of the serial-parallel conversion module is used for inputting a high-speed clock signal;

the output end of the serial-parallel conversion module is electrically connected with the first input end of the controllable delay unit and is used for outputting a serial data signal to the controllable delay unit according to the parallel data signal and the high-speed clock signal;

the output end of the controllable delay unit is electrically connected with the first input end of the data driver and is used for outputting a delayed serial data signal to the data driver according to the serial data signal;

a second input end of the controllable delay unit is electrically connected with a second input end of the serial-parallel conversion module, and the controllable delay unit is provided with the high-speed clock signal;

the output end of the data driver is electrically connected with the third input end of the controllable delay unit and is used for sampling the differential data signal output by the data driver according to the high-speed clock signal and sending the differential data signal to the controllable delay unit so as to adjust the delay size;

the second input end of the data driver is electrically connected with the output end of the linear voltage stabilizer and is used for transmitting power supply voltage to the data driver;

the differential data signals include a first differential data signal and a second differential data signal.

Furthermore, the controllable delay unit comprises a high-speed comparator, a phase discriminator, a low-pass filter and a voltage-controlled delay line;

a first input end of the high-speed comparator is electrically connected with an output end of the data driver, and a second input end of the high-speed comparator is electrically connected with a second input end of the serial-parallel conversion module;

the output end of the high-speed comparator is electrically connected with the first input end of the phase discriminator, and the second input end of the phase discriminator is electrically connected with the second input end of the serial-parallel conversion module;

the output end of the phase discriminator is electrically connected with the input end of the low-pass filter, and the output end of the low-pass filter is electrically connected with the first input end of the voltage-controlled delay line;

the second input end of the voltage-controlled delay line is electrically connected with the output end of the serial-parallel conversion module, and the output end of the voltage-controlled delay line is electrically connected with the first input end of the data driver.

Further, the phase detector comprises a binary phase detector and a time-to-digital converter, the output end of the binary phase detector is electrically connected with the input end of the low-pass filter, the first input end of the binary phase detector is electrically connected with the second input end of the serial-parallel conversion module, the second input end of the binary phase detector is electrically connected with the output end of the time-to-digital converter, and the input end of the time-to-digital converter is electrically connected with the output end of the high-speed comparator.

Furthermore, the output end of the data driver comprises a first output end and a second output end, and the first output end and the second output end are both electrically connected with the third input end of the controllable delay unit.

Furthermore, the third input terminal of the controllable delay unit includes a first input terminal and a second input terminal, the first input terminal is electrically connected to the first output terminal of the data driver, and the second input terminal is electrically connected to the second output terminal of the data driver;

the first input end and the second input end are both electrically connected with the first input end of the high-speed comparator.

Furthermore, the output end of the data driver is also electrically connected with the buffer unit.

Further, the circuit configuration of the jitter reduction data transmitter is a closed-loop feedback configuration.

The invention achieves the following beneficial effects: receiving a parallel data signal and a high-speed clock signal through an input end of the serial-parallel conversion module, and outputting a serial data signal after the parallel-serial conversion; the serial data signal passes through the controllable delay unit and then outputs a delayed serial data signal; the delayed serial data signal is changed into a differential data signal (a first differential data signal and a second differential data signal) through the data driver and then is output; the power supply of the data driver is the voltage output by the linear voltage regulator; the controllable delay unit samples differential data signals (a first differential data signal and a second differential data signal) by using the high-speed clock signal, and adjusts the delay according to the sampling result and the phase of the high-speed clock signal. Therefore, the jitter of the circuit can be reduced, and the eye diagram performance of the circuit can be improved.

Drawings

Fig. 1 is a block diagram of a data transmitter provided in the prior art;

FIG. 2 is a block diagram of a data transmitter for reducing jitter according to the present invention;

fig. 3 is a block diagram of another data transmitter for reducing jitter according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the embodiment of the invention, a parallel data signal and a high-speed clock signal are received through the input end of the serial-parallel conversion module, and a serial data signal is output after the parallel-serial conversion; the serial data signal passes through the controllable delay unit and then outputs a delayed serial data signal; the delayed serial data signal is changed into a differential data signal (a first differential data signal and a second differential data signal) through the data driver and then is output; the power supply of the data driver is the voltage output by the linear voltage regulator; the controllable delay unit samples differential data signals (a first differential data signal and a second differential data signal) by using the high-speed clock signal, and adjusts the delay according to the sampling result and the phase of the high-speed clock signal. Therefore, the jitter of the circuit can be reduced, and the eye diagram performance of the circuit can be improved.

Referring to fig. 2, fig. 2 is a block diagram of a data transmitter for reducing jitter according to the present invention.

The jitter reduced data transmitter comprises: the device comprises a serial-parallel conversion module 1, a controllable delay unit 2, a data driver 3 and a linear voltage stabilizer 4; the first input terminal of the serial-to-parallel conversion module 1 is used for inputting a parallel data signal data [ x:0 ]. The second input end of the serial-parallel conversion module 1 is used for inputting a high-speed clock signal clk. The output end of the serial-parallel conversion module 1 is electrically connected with the first input end of the controllable delay unit 2, and is configured to output a serial data signal data to the controllable delay unit 2 according to the parallel data signal data [ x:0] and the high-speed clock signal clk. The output end of the controllable delay unit 2 is electrically connected to the first input end of the data driver 3, and is configured to output the delayed serial data signal datadly to the data driver 3 according to the serial data signal data. A second input end of the controllable delay unit 2 is electrically connected to a second input end of the serial-to-parallel conversion module 1, and provides a high-speed clock signal clk for the controllable delay unit 2. The output end of the data driver 3 is electrically connected to the third input end of the controllable delay unit 2, and is configured to sample the differential data signal output by the data driver 3 according to the high-speed clock signal clk, and provide the differential data signal to the controllable delay unit 2, so as to adjust the delay size. And a second input end of the data driver 3 is electrically connected with an output end of the linear voltage regulator 4 and is used for transmitting power voltage to the data driver 3. The differential data signals include a first differential data signal and a second differential data signal. The output end of the data driver 3 is further electrically connected to the buffer unit for implementing data transmission or storage.

Specifically, the input end of the serial-parallel conversion module 1 receives a parallel data signal data [ x:0] and a high-speed clock signal clk, and outputs a serial data signal data after the parallel-serial conversion; the serial data signal datas passes through the controllable delay unit 2 and then outputs a delayed serial data signal datadly; the delayed serial data signal datadly passes through the data driver 3 and then becomes a differential data signal (a first differential data signal and a second differential data signal) to be output to the PAD; the power supply of the data driver 3 is the voltage output by the linear regulator 4; the controllable delay unit 2 samples differential data signals (a first differential data signal and a second differential data signal) by using the high-speed clock signal clk, and adjusts the delay according to the sampling result and the phase of the high-speed clock signal clk.

In the embodiment of the present invention, as shown in fig. 3, the controllable delay unit 2 includes a high-speed comparator 24, a phase detector 23, a low-pass filter 22, and a voltage-controlled delay line 21; a first input terminal of the high-speed comparator 24 is electrically connected to the output terminal of the data driver 3, and a second input terminal of the high-speed comparator 24 is electrically connected to the second input terminal of the serial-parallel conversion module 1. The output end of the high-speed comparator 24 is electrically connected with the first input end of the phase detector 23, and the second input end of the phase detector 23 is electrically connected with the second input end of the serial-parallel conversion module 1. The output end of the phase detector 23 is electrically connected to the input end of the low-pass filter 22, and the output end of the low-pass filter 22 is electrically connected to the first input end of the voltage-controlled delay line 21. The second input end of the voltage-controlled delay line 21 is electrically connected with the output end of the serial-parallel conversion module 1, and the output end of the voltage-controlled delay line 21 is electrically connected with the first input end of the data driver 3.

Further, the phase Detector 23 includes a binary phase Detector (BBPD) and a Time-to-Digital Converter (TDC), an output end of the binary phase Detector is electrically connected to an input end of the low-pass filter 22, a first input end of the binary phase Detector is electrically connected to a second input end of the serial-parallel conversion module 1, a second input end of the binary phase Detector is electrically connected to an output end of the Time-to-Digital Converter, and an input end of the Time-to-Digital Converter is electrically connected to an output end of the high-speed comparator 24. It should be noted that the phase detection signal vpd output by the phase detector 23 may be an analog signal or a digital signal, which is different according to the structure of the phase detector 23

Further, the output end of the data driver 3 includes a first output end and a second output end, and both the first output end and the second output end are electrically connected to the third input end of the controllable delay unit 2. The first output end is used for transmitting a first differential data signal dp and the second output end is used for transmitting a second differential data signal dn

Further, the third input terminal of the controllable delay unit 2 includes a first input terminal electrically connected to the first output terminal of the data driver 3 and a second input terminal electrically connected to the second output terminal of the data driver 3. The first input terminal and the second input terminal are both electrically connected to a first input terminal of the high-speed comparator 24. The first input terminal is used for inputting the second differential data signal dp and the second input terminal is used for inputting the first differential data signal dn.

It should be noted that the circuit structure of the data transmitter for reducing jitter is a closed-loop feedback structure.

Specifically, the inputs of the high-speed comparator 24 are a first differential data signal dp, a second differential data signal dn, and a high-speed clock signal clk; after comparison, a serial data signal datacmp is output and serves as an input end of the phase detector 23, the other input end of the phase detector 23 is a high-speed clock signal clk, and the phase detector 23 quantizes the input phase difference of the two and outputs a phase detection signal vpd; the phase detection signal vpd is input to the low-pass filter 22 and outputs a control voltage vctrl after filtering operation; the control voltage vctrl controls the delay of the serial data signal data to the delayed serial data signal datadly as an input to the voltage controlled delay line 21.

When the circuit normally works, the high-speed comparator 24 samples the first differential data signal dp and the second differential data signal dn by using the high-speed clock signal clk, the obtained serial data signal datacmp is input to the phase detector 23 and phase-discriminated with the clock of the high-speed clock signal clk, after the phase-discriminated signal vpd passes through the low-pass filter 22, a control voltage vctrl only containing a low-pass component can be output, the control voltage vctrl controls the time delay of the voltage-controlled delay line 21, and the phase alignment of the serial data signal datacmp and the high-speed clock signal clk is realized through feedback control.

Through principle analysis, the closed-loop feedback structure (feedback loop) is a low-pass filter 22 circuit for the serial data signal data, and can filter high-frequency jitter of the serial data signal data; for ISI introduced by the supply voltage vp and random noise of the data driver 3 itself, the closed loop feedback structure is a high pass filter circuit that filters out ISI in the low frequency part and random noise of the data driver 3.

The data transmitter capable of reducing the jitter changes the traditional data transmitter circuit from an open loop to a closed loop feedback structure, and has the advantages that a high-pass filter can be constructed, so that the low-frequency part of ISI (inter-symbol interference) introduced by voltage ripples of the linear voltage regulator 4 and low-frequency noise generated by the data driver 3 are filtered, the circuit supports the filtering bandwidth which is about 10 times of the frequency of the high-speed clock signal clk, the jitter performance of an output eye diagram can be improved to a greater extent, and the circuit has more flexible and wide application.

In the embodiment of the present invention, when the circuit normally works, random data will affect the linear regulator 4 supplying power to the data driver 3, resulting in random power-off, which is expressed as the ripple of the power voltage vp varying with the variation of the data signal. This variation in voltage ripple introduces a certain intersymbol interference ISI in the output differential data signal. In addition, due to the thermal noise and 1/f noise of the data driver 3 itself, the output differential data signal also contains a certain random noise. The controllable delay unit 2 samples the first differential data signal dp and the second differential data signal dn by using the high-speed clock signal clk, the obtained serial data signal datacmp is input to the phase discriminator 23 and phase-discriminated with the clock of the high-speed clock signal clk, and the obtained phase difference is used for dynamically adjusting the delay of the controllable delay unit 2. The delay variation of the controllable delay unit 2 can counteract part of the ISI and the random noise, thereby reducing the circuit jitter and achieving the effect of providing the eye pattern performance.

Compared with the traditional data transmitter, the data transmitter for reducing the jitter introduces a feedback control loop, greatly reduces ISI introduced by power supply ripples and random noise of the data driver 3, can reduce the jitter, effectively improves the eye pattern performance, and can be well applied to various high-speed interfaces.

The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.