阅读说明：本技术 带隙基准电压源电路 (Band-gap reference voltage source circuit ) 是由 卫梦昭 于 2021-08-24 设计创作，主要内容包括：本申请公开了一种带隙基准电压源电路,包括核心电路、信号反馈电路、前置稳压电路和后置稳压电路。其中,前置稳压电路构成核心电路中的运算放大器的外部环路,用来产生前置稳压向核心电路供电,后置稳压电路与核心电路以及前置稳压电路连接,用于根据基准电压设置偏置电压的大小,从而可以提高电路在低功耗条件下对高频电源噪声的抑制能力。(The application discloses band gap reference voltage source circuit, including core circuit, signal feedback circuit, leading voltage stabilizing circuit and rearmounted voltage stabilizing circuit. The post voltage stabilizing circuit is connected with the core circuit and the pre voltage stabilizing circuit and is used for setting the size of bias voltage according to reference voltage, so that the capability of the circuit for inhibiting high-frequency power supply noise under the condition of low power consumption can be improved.)

1. A bandgap reference voltage source circuit comprising:

a core circuit for generating a reference voltage having a zero temperature coefficient;

the signal feedback circuit and an operational amplifier in the core circuit form a feedback loop;

the front voltage stabilizing circuit is used for providing bias voltage for the core circuit and the signal feedback circuit according to power supply voltage; and

and the post voltage stabilizing circuit is connected with the core circuit and the pre voltage stabilizing circuit and is used for setting the magnitude of the bias voltage according to the reference voltage so as to improve the suppression capability of the circuit on the noise of the high-frequency power supply.

2. The bandgap reference voltage source circuit of claim 1, wherein said core circuit comprises:

an operational amplifier;

the first end of the first resistor is connected with the inverting input end of the operational amplifier, and the second end of the first resistor is connected with the non-inverting input end of the operational amplifier;

the second end of the second resistor is connected with the inverting input end of the operational amplifier, and the first end of the second resistor is used for outputting the reference voltage;

the emitter of the first triode is connected with the positive phase input end of the operational amplifier, and the collector and the base are grounded; and

and a first end of the first capacitor is connected with the output end of the operational amplifier, and a second end of the first capacitor is grounded.

3. The bandgap reference voltage source circuit of claim 1, wherein said pre-regulation circuit comprises:

a first transistor having a first terminal connected to the power supply voltage and a control terminal connected to the second terminal;

a second transistor, a first end of which is connected with the power voltage, a control end of which is connected with the control end of the first transistor to form a current mirror, and a second end of which is used for outputting the bias voltage; and

and a first end of the third transistor is connected with the second end of the first transistor, the second end of the third transistor is grounded, and a control end of the third transistor is connected with the output end of the operational amplifier.

4. The bandgap reference voltage source circuit of claim 3, wherein said pre-regulation circuit further comprises:

a fourth transistor having a first terminal connected to the second terminal of the first transistor, a second terminal connected to the first terminal of the third transistor, and a control terminal connected to the second terminal of the second transistor,

wherein the fourth transistor is used for reducing the impedance of the first transistor to the ground.

5. The bandgap reference voltage source circuit of claim 4, wherein said first and second transistors are PMOS transistors respectively,

the third transistor and the fourth transistor are NMOS transistors respectively.

6. The bandgap reference voltage source circuit of claim 1, wherein said signal feedback circuit comprises:

a control end of the fifth transistor is connected with the output end of the operational amplifier, and a second end of the fifth transistor is grounded;

a sixth transistor, a first terminal of which is connected to the bias voltage, a second terminal of which is connected to the first terminal of the fifth transistor, and a control terminal of which is connected to the second terminal;

a seventh transistor, a first end of which is connected to the bias voltage, a control end of which is connected to a control end of the sixth transistor, and a second end of which is connected to a power supply end of the operational amplifier; and

and the first end of the eighth transistor is connected with the bias voltage, the control end of the eighth transistor is connected with the control end of the sixth transistor, and the second end of the eighth transistor is connected with the output end of the reference voltage.

7. The bandgap reference voltage source circuit of claim 6, wherein said fifth transistor is an NMOS transistor,

the sixth transistor, the seventh transistor and the eighth transistor are PMOS tubes respectively.

8. The bandgap reference voltage source circuit of claim 1, wherein said post voltage regulation circuit comprises:

a ninth transistor having a first terminal connected to the bias voltage and a control terminal connected to the reference voltage; and

and an emitter of the second triode is connected with the second end of the ninth transistor, and a collector and a base of the second triode are grounded.

9. The bandgap reference voltage source circuit of claim 8, wherein said ninth transistor is a PMOS transistor.

10. The bandgap reference voltage source circuit of claim 2, wherein the operational amplifier comprises:

a tenth transistor and an eleventh transistor which constitute a differential pair transistor, first ends of which are connected to each other, a control end of the tenth transistor being connected to the second end of the first resistor, and a control end of the eleventh transistor being connected to the first end of the first resistor; and

a twelfth transistor and a thirteenth transistor of which first terminals are connected to the second terminals of the tenth transistor and the eleventh transistor, respectively, control terminals are connected to each other and to the first terminal of the twelfth transistor, and second terminals are connected to each other and to ground.

11. The bandgap reference voltage source circuit of claim 10, wherein the tenth transistor and the eleventh transistor are PMOS transistors respectively,

the twelfth transistor and the thirteenth transistor are NMOS transistors respectively.

Technical Field

The invention relates to the technical field of switching power supplies, in particular to a band-gap reference voltage source circuit.

Background

The bandgap reference is widely used in a/D converter, D/a converter, memory and power converter, and as a key unit of an integrated circuit, its accuracy plays a very important role in the overall performance of the circuit. The bandgap reference voltage source is a dc voltage obtained by adding a voltage proportional to absolute temperature and a voltage difference between the base-emitter of two transistors. An ideal reference voltage source is hardly affected by temperature and supply voltage.

The generation of high performance on-chip reference voltages relies on high performance BJTs (Bipolar Junction transistors), which are rarely compatible with advanced CMOS process nodes. Therefore, another conventional solution generally generates a reference voltage based on a substrate PNP, and generates a PTAT (Proportional to Absolute Temperature) voltage through an N:1 ratio and an operational amplifier, but is limited by non-idealities of the operational amplifier, such as input offset voltage and limited bandwidth, and the initial accuracy and high frequency power supply rejection capability of such a solution are generally weak in low power design. In addition, the β flatness of the BJT also affects the temperature drift of the reference voltage when the collector current density is low, and it is difficult to generate a high-precision reference voltage.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a bandgap reference voltage source circuit, which effectively improves the influence of the operational amplifier input offset voltage and the high-frequency power supply noise on the output accuracy of the reference voltage.

According to the present invention there is provided a bandgap reference voltage source circuit comprising: a core circuit for generating a reference voltage having a zero temperature coefficient; the signal feedback circuit and an operational amplifier in the core circuit form a feedback loop; the front voltage stabilizing circuit is used for providing bias voltage for the core circuit and the signal feedback circuit according to power supply voltage; and the post voltage stabilizing circuit is connected with the core circuit and the pre voltage stabilizing circuit and is used for setting the magnitude of the bias voltage according to the reference voltage so as to improve the suppression capability of the circuit on the noise of the high-frequency power supply.

Optionally, the core circuit includes: an operational amplifier; the first end of the first resistor is connected with the inverting input end of the operational amplifier, and the second end of the first resistor is connected with the non-inverting input end of the operational amplifier; the second end of the second resistor is connected with the inverting input end of the operational amplifier, and the first end of the second resistor is used for outputting the reference voltage; the emitter of the first triode is connected with the positive phase input end of the operational amplifier, and the collector and the base are grounded; and a first end of the first capacitor is connected with the output end of the operational amplifier, and a second end of the first capacitor is grounded.

Optionally, the front voltage stabilizing circuit includes: a first transistor having a first terminal connected to the power supply voltage and a control terminal connected to the second terminal; a second transistor, a first end of which is connected with the power voltage, a control end of which is connected with the control end of the first transistor to form a current mirror, and a second end of which is used for outputting the bias voltage; and a third transistor, a first end of which is connected with the second end of the first transistor, a second end of which is grounded, and a control end of which is connected with the output end of the operational amplifier.

Optionally, the front voltage stabilizing circuit further includes: and a fourth transistor, a first terminal of which is connected to the second terminal of the first transistor, a second terminal of which is connected to the first terminal of the third transistor, and a control terminal of which is connected to the second terminal of the second transistor, wherein the fourth transistor is used for reducing the impedance of the first transistor to ground.

Optionally, the first transistor and the second transistor are PMOS transistors, respectively, and the third transistor and the fourth transistor are NMOS transistors, respectively.

Optionally, the signal feedback circuit includes: a control end of the fifth transistor is connected with the output end of the operational amplifier, and a second end of the fifth transistor is grounded; a sixth transistor, a first terminal of which is connected to the bias voltage, a second terminal of which is connected to the first terminal of the fifth transistor, and a control terminal of which is connected to the second terminal; a seventh transistor, a first end of which is connected to the bias voltage, a control end of which is connected to a control end of the sixth transistor, and a second end of which is connected to a power supply end of the operational amplifier; and the first end of the eighth transistor is connected with the bias voltage, the control end of the eighth transistor is connected with the control end of the sixth transistor, and the second end of the eighth transistor is connected with the output end of the reference voltage.

Optionally, the fifth transistor is an NMOS transistor, and the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors, respectively.

Optionally, the post voltage stabilizing circuit includes: a ninth transistor having a first terminal connected to the bias voltage and a control terminal connected to the reference voltage; and the emitter of the second triode is connected with the second end of the ninth transistor, and the collector and the base of the second triode are grounded.

Optionally, the ninth transistor is a PMOS transistor.

Optionally, the operational amplifier includes: a tenth transistor and an eleventh transistor which constitute a differential pair transistor, first ends of which are connected to each other, a control end of the tenth transistor being connected to the second end of the first resistor, and a control end of the eleventh transistor being connected to the first end of the first resistor; and twelfth and thirteenth transistors of which first ends are connected to second ends of the tenth and eleventh transistors, respectively, of which control ends are connected to each other and to a first end of the twelfth transistor, and of which second ends are connected to each other and to ground.

Optionally, the tenth transistor and the eleventh transistor are PMOS transistors respectively, and the twelfth transistor and the thirteenth transistor are NMOS transistors respectively.

The band-gap reference voltage source circuit comprises a core circuit, a signal feedback circuit, a front voltage stabilizing circuit and a rear voltage stabilizing circuit. The post voltage stabilizing circuit is connected with the core circuit and the pre voltage stabilizing circuit and is used for setting the size of bias voltage according to reference voltage, so that the capability of the circuit for inhibiting high-frequency power supply noise under the condition of low power consumption can be improved.

In addition, the core circuit of the embodiment generates a voltage with a positive temperature coefficient through the input offset voltage of the operational amplifier, and the reference voltage with almost zero temperature coefficient can be generated by adding the emitter voltage with the negative temperature coefficient of the triode.

In addition, the positive temperature coefficient voltage of the embodiment utilizes the ideal factor m of the differential pair transistor in the operational amplifier, so that the value of the multiplier R2/R1 can be minimized, and the sensitivity of the reference voltage Vref to MOS tube mismatch is reduced. Meanwhile, the bandgap reference voltage source circuit of the embodiment does not need to consider the influence of the beta flatness of the BJT in a low current state on the output reference voltage because the BJT transistor pair of N:1 is not provided.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic circuit diagram of a conventional Brokaw bandgap reference voltage source circuit;

FIG. 2 shows a schematic circuit diagram of another bandgap reference voltage source circuit according to the prior art;

FIG. 3 shows a schematic circuit diagram of a bandgap reference voltage source circuit according to an embodiment of the present invention;

fig. 4 shows a schematic circuit diagram of an operational amplifier in a bandgap reference voltage source circuit according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

In the present application, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS fet) includes a first terminal, a second terminal, and a control terminal, and in an on state of the MOS Transistor, a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the PMOS tube are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the NMOS tube are respectively a drain electrode, a source electrode and a grid electrode. A transistor (also referred to as a bipolar transistor) includes a first terminal, a second terminal, and a control terminal, and in a conducting state of the transistor, a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the PNP tube are respectively an emitter, a collector and a base, and the first end, the second end and the control end of the NPN tube are respectively a collector, an emitter and a base.

The invention is further illustrated with reference to the following figures and examples.

Fig. 1 is a schematic circuit diagram of a conventional Brokaw bandgap reference voltage source circuit. The circuit 100 includes an operational amplifier a1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a transistor Q1, and a transistor Q2. Wherein, the resistor R1= R2= R, and the emitter area of the transistor Q1 is N times of the emitter area of the transistor Q2. The Brokaw bandgap reference voltage source is designed based on an operational amplifier a1, and according to the virtual short principle of the operational amplifier, the voltage drop on the resistor R1 and the resistor R2 are equal, and since the resistor R1= R2= R, the current flowing through the transistor Q1 and the transistor Q2 are equal. Suppose the beta 1 of the triode (beta is the AC amplification factor of the triode) neglects the influence of the base current, and has

Wherein I1 and I2 are collector currents of a triode Q1 and a triode Q2 respectively, and V_BE2The base-emitter voltage of transistor Q2. Wherein the content of the first and second substances,

for a device of the bipolar type,can obtain the product

Wherein, I_SIs the saturation leakage current of the triode, V_TIf (= KT/q) is thermoelectric potential, then

Where N represents the ratio of emitter areas of transistors Q1 and Q2.

Substituting formula (4) for formula (2), and then substituting formula (2) for formula (1) to obtain

By deriving the temperature in the above equation and making the equation result zero at room temperature, the desired ratio of R4 to R3 can be determined, resulting in a reference voltage with a zero temperature coefficient at room temperature.

As mentioned above, the Brokaw bandgap reference voltage source structure relies on high performance BJTs (Bipolar Junction transistors), which are rarely compatible with advanced CMOS process nodes. Therefore, as shown in fig. 2, the bandgap reference voltage source circuit 200 includes a transistor M1, a transistor M2, a transistor M3, a transistor Q3, a transistor Q4, a transistor Q5, a resistor R5, resistors R6, R7, and an operational amplifier a 2.

The transistor M1, the transistor M2 and the transistor M3 are PMOS transistors, and the transistor Q3, the transistor Q4 and the transistor Q5 are PNP transistors. The transistor M1 and the transistor Q3 are connected to a first branch between a power supply voltage VDD and the ground, the transistor M2, the resistor R5 and the transistor Q4 are connected to a second branch between the power supply voltage VDD and the ground, the transistor M3, the resistor R6 and the transistor Q5 are connected to a third branch between the power supply voltage VDD and the ground, and the resistor R7 is connected between a middle node of the transistor M3 and the resistor R6 and the ground and used for shunting the current I3 to reduce the voltage value of the output bandgap reference voltage. Control terminals of the transistor M1, the transistor M2, and the transistor M3 are connected to each other to constitute a mirror current source. The control terminals of the transistor Q3, the transistor Q4, and the transistor Q5 are grounded. The inverting input terminal of the operational amplifier a2 is connected to the node a through the transistor M1 and the transistor Q3, the non-inverting input terminal thereof is connected to the node B through the transistor M2 and the resistor R5, and the output terminal thereof is connected to the control terminals of the transistor M1 and the transistor M2.

In the bandgap reference voltage source 200, the transistor M1 and the transistor M2 are the same transistor, so the current I1 and the current I2 flowing through the transistor M1 and the transistor M2 are equal, and because the transistor Q3 and the transistor Q4 have different emitter-base areas, the transistor Q3 and the transistor Q4 operate at different current densities, so the voltage difference between the base-emitter voltages of the transistor Q3 and the transistor Q4 is proportional to the absolute temperature, i.e. the transistor M1 and the transistor M2 are the same transistor. If the voltages of the node a and the node B are not completely equal, the operational amplifier a2 works in a deep negative feedback state, compares the voltages of the node a and the node B, amplifies the difference value, and changes the currents flowing through the transistor Q3 and the transistor Q4 to different degrees, so that the voltages of the node a and the node B are approximately equal, and therefore the base-emitter voltage of the transistor Q3 becomes:(wherein,thermal potentials of transistor Q3 and transistor Q4, k is Boltzmann's constant, T is absolute temperature, and Q is the amount of electric charge of elementary charge), that isThe current I2 is PTAT current, and the transistor M3 and the transistor M2 form a mirror current source, so that the current is obtainedAnd because of the resistance R6 and the resistanceR7 shunts current I3, thus:

wherein, V_BE5Representing the base-emitter voltage of transistor Q5.

Combining the above formula can obtain:

wherein, the base-emitter voltage V of the triode Q5_BE5The band gap reference voltage Vref with zero temperature coefficient can be obtained by properly selecting the ratio of N to the resistor R6 to the resistor R7.

In the prior bandgap reference voltage source circuit 200, the initial accuracy and high frequency power supply rejection capability of this scheme are generally poor in low power design due to the non-idealities of the operational amplifier, such as input offset voltage and limited bandwidth. In addition, the beta flatness of the BJT also affects the temperature drift of the reference voltage when the collector current density is low.

Fig. 3 shows a schematic circuit diagram of a bandgap reference voltage source circuit according to an embodiment of the present invention. Referring to FIG. 3, the circuit 300 includes a front-end regulation circuit 301, a signal feedback circuit 302, a core circuit 303, and a back-end regulation circuit 304. The core circuit 303 is configured to generate a reference voltage Vref having a zero temperature coefficient. The signal feedback circuit 302 is connected to the core circuit 303 to form a feedback loop with the operational amplifier a1 in the core circuit 303. The pre-regulator circuit 301 is connected to the signal feedback circuit 302 and the core circuit 303, and is configured to provide the bias voltage Vpre to the core circuit 303 and the signal feedback circuit 302 according to the power supply voltage VDD. The post-regulator circuit 304 is connected to the core circuit 303 and the pre-regulator circuit 301, and is configured to set the magnitude of the bias voltage Vpre according to the reference voltage Vref, so as to improve the circuit's ability to suppress high-frequency power noise.

Optionally, the core circuit 303 includes an operational amplifier a1, a resistor R1, a resistor R2, a transistor Q1, and a capacitor C1. A first terminal of the resistor R1 is connected to the inverting input terminal of the operational amplifier a1, and a second terminal of the resistor R1 is connected to the non-inverting input terminal of the operational amplifier a 1. The second end of the resistor R2 is connected to the inverting input terminal of the operational amplifier a1, and the first end of the resistor R2 is used for outputting the reference voltage Vref with zero temperature coefficient. The emitter of the transistor Q1 is connected to the non-inverting input of the operational amplifier a1, and the collector and base of the transistor Q1 are grounded. The capacitor C1 has a first terminal connected to the output terminal of the operational amplifier a1 and a second terminal connected to ground.

The front voltage stabilizing circuit 301 comprises a transistor M1, a transistor M2, a transistor M3 and a transistor M4. The transistor M1 and the transistor M2 are selected from PMOS transistors, the transistor M3 and the transistor M4 are respectively selected from NMOS transistors, first terminals of the transistor M1 and the transistor M2 are connected to the power voltage VDD, control terminals of the transistor M1 and the transistor M2 are connected to each other, and the second terminals of the transistor M1 are connected, so that a mirror current source is formed by the transistors. The first terminal of the transistor M4 is connected to the second terminal of the transistor M1, the control terminal is connected to the second terminal of the transistor M2, the first terminal of the transistor M3 is connected to the second terminal of the transistor M4, the control terminal is connected to the output terminal of the operational amplifier a1, and the second terminal is grounded. The transistor M1 and the transistor M2 form a current mirror for generating a bias voltage Vpre according to the power supply voltage VDD, and supplying power to the signal feedback circuit 302 and the core circuit 303, the transistor M3 forms an outer loop of the operational amplifier a1, and is used for generating a pre-regulated voltage, so that the circuit has a high-frequency power supply noise suppression capability under a low power consumption condition, and the transistor M4 is used for reducing the impedance of the transistor M1 to the ground, so that the high-frequency power supply noise suppression capability of the circuit can be further improved.

The signal feedback circuit 302 includes a transistor M5, a transistor M6, a transistor M7, and a transistor M8. The transistor M5 is selected from NMOS transistors, and the transistor M6, the transistor M7, and the transistor M8 are respectively selected from PMOS transistors. The control terminal of the transistor M5 is connected to the output terminal of the operational amplifier a1, and the second terminal of the transistor M5 is grounded. First terminals of the transistor M6, the transistor M7, and the transistor M8 are connected to the bias voltage Vpre, control terminals of the transistor M6, the transistor M7, and the transistor M8 are connected to each other, and a second terminal of the transistor M6 is connected. The second terminal of the transistor M6 is further connected to the first terminal of the transistor M5, the second terminal of the transistor M7 is connected to the power supply terminal of the operational amplifier a1, and the second terminal of the transistor M8 is connected to the first terminal of the resistor R2. Among them, the transistors M5 to M8 not only form an internal feedback loop of the operational amplifier a1 and have a high loop gain, but also the transistor M7 is used to supply power to the operational amplifier a1 according to the bias voltage Vpre. In addition, the transistors M6 to M8 form a current mirror, which can ensure that the current flowing through the resistor R1 and the resistor R2 is equal to the power supply current of the operational amplifier a1, and help reduce the variation of the output reference voltage Vref with the bias voltage Vpre.

The post regulation circuitry 304 includes a transistor M9 and a transistor Q2. The transistor M9 is selected from a PMOS transistor, a first terminal of which is connected to a bias voltage Vpre, a control terminal of which is connected to a reference voltage Vref, an emitter of the transistor Q2 is connected to a second terminal of the transistor M9, and a collector and a base of the transistor are grounded. The transistor M9 is used to set the magnitude of the bias voltage VpreWhere Vgs9 represents the gate-source voltage of transistor M9. In addition, the transistor M9 can also reduce the resistance of the bias voltage Vpre to ground, further improving the circuit's ability to suppress high frequency power supply noise.

During the whole circuit operation, the offset voltage of the operational amplifier a1 generates a current proportional to absolute temperature in the resistor R1, and this current generates a voltage Vptat with positive temperature coefficient in the resistor R1, plus the emitter voltage V of the transistor Q1 with negative temperature coefficient_BEThe reference voltage Vref can be generated with almost zero temperature coefficient. Wherein:

further, the signal feedback circuit 302 constitutes an inner loop of the operational amplifier a1, and the pre-regulator circuit 301 constitutes an outer loop of the operational amplifier a 1. The inner loop is used for generating a voltage with a positive temperature coefficient, and the outer loop is used for generating a pre-regulated voltage so as to improve the suppression capability of the circuit on high-frequency power supply noise under the condition of low power consumption.

Referring to fig. 4, the operational amplifier a1 includes a transistor M10, a transistor M11, a transistor M12, and a transistor M13. The transistor M10 and the transistor M11 are PMOS transistors, respectively, and the transistor M12 and the transistor M13 are NMOS transistors, respectively. The transistor 10 and the transistor M11 form a differential pair transistor, the first terminals of which are connected to each other, the control terminal of the transistor M10 is connected to the second terminal of the resistor R1, and the control terminal of the transistor M11 is connected to the first terminal of the resistor R1. The transistor M12 and the transistor M13 form a cascode transistor, the first terminals of which are connected to the second terminals of the transistor M10 and the transistor M11, respectively, the control terminals of which are connected to each other, and the first terminal of the transistor M12, and the second terminals of which are also connected to each other and to ground. Since the ratio of the width to length ratios of the transistor M10 and the transistor M11 is N:1, the voltage of the positive temperature coefficientWhere Vgs10 and Vgs11 represent the gate-source voltages of transistor M10 and transistor M11, respectively. The positive temperature coefficient voltage of the embodiment utilizes the ideal factor m (m is usually larger than 1) of the differential pair transistors in the operational amplifier, so that the value of the multiplier R2/R1 can be minimized, and the sensitivity of the reference voltage Vref to MOS tube mismatch is reduced. Meanwhile, the bandgap reference voltage source circuit of the embodiment does not need to consider the influence of the beta flatness of the BJT in a low current state on the output reference voltage because the BJT transistor pair of N:1 is not provided.

In summary, the bandgap reference voltage source circuit according to the embodiment of the invention includes a core circuit, a signal feedback circuit, a pre-regulator circuit and a post-regulator circuit. The post voltage stabilizing circuit is connected with the core circuit and the pre voltage stabilizing circuit and is used for setting the size of bias voltage according to reference voltage, so that the capability of the circuit for inhibiting high-frequency power supply noise under the condition of low power consumption can be improved.

In addition, the core circuit of the embodiment generates a voltage with a positive temperature coefficient through the input offset voltage of the operational amplifier, and the reference voltage with almost zero temperature coefficient can be generated by adding the emitter voltage with the negative temperature coefficient of the triode.

In addition, the positive temperature coefficient voltage of the embodiment utilizes the ideal factor m of the differential pair transistor in the operational amplifier, so that the value of the multiplier R2/R1 can be minimized, and the sensitivity of the reference voltage Vref to MOS tube mismatch is reduced. Meanwhile, the bandgap reference voltage source circuit of the embodiment does not need to consider the influence of the beta flatness of the BJT in a low current state on the output reference voltage because the BJT transistor pair of N:1 is not provided.

It should be noted that although the device is described herein as being an N-channel or P-channel device, or an N-type or P-type doped region, one of ordinary skill in the art will appreciate that complementary devices may be implemented in accordance with the present invention. It will be understood by those skilled in the art that conductivity type refers to the mechanism by which conduction occurs, for example by conduction through holes or electrons, and thus does not relate to the doping concentration but to the doping type, for example P-type or N-type. It will be understood by those of ordinary skill in the art that the words "during", "when" and "when … …" as used herein in relation to the operation of a circuit are not strict terms referring to actions occurring immediately upon initiation of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reactive action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.