阅读说明：本技术 一种GaN器件的制作方法以及一种GaN器件 (GaN device and manufacturing method thereof ) 是由 张启华 吴文静 蒋军浩 袁元 张勇为 张洋 江慧英 其他发明人请求不公开姓名 于 2021-09-07 设计创作，主要内容包括：本发明涉及一种GaN器件的制作方法以及一种GaN器件。本发明所述的GaN器件的制作方法包括：提供半导体衬底；在半导体衬底上生长一层缓冲层；在所述缓冲层上生长一层第一GaN层；在所述第一GaN层上生长一层AlGaN层；在所述AlGaN层上再生长一层第二GaN层；将上述步骤得到的晶圆翻转,使得所述半导体衬底朝上；依次移除所述半导体衬底和所述缓冲层；对所述第一GaN层进行减薄处理,并定义所述第一GaN层的图案；在所述第一GaN层上生长一层绝缘层,并对所述绝缘层进行平坦化处理；在所述绝缘层上制备电极。本发明方法通过在原本的晶圆背面制备氮化镓晶体管需要的源极、漏极、栅极,以减少晶体管原生的晶格缺陷,大幅提升最终产品的性能、优良率以及可靠性。(The invention relates to a manufacturing method of a GaN device and the GaN device. The manufacturing method of the GaN device comprises the following steps: providing a semiconductor substrate; growing a buffer layer on a semiconductor substrate; growing a first GaN layer on the buffer layer; growing an AlGaN layer on the first GaN layer; a second GaN layer is grown on the AlGaN layer; turning over the wafer obtained in the step to enable the semiconductor substrate to face upwards; sequentially removing the semiconductor substrate and the buffer layer; thinning the first GaN layer, and defining a pattern of the first GaN layer; growing an insulating layer on the first GaN layer, and carrying out planarization treatment on the insulating layer; and preparing an electrode on the insulating layer. The method reduces the original lattice defects of the transistor by preparing the source electrode, the drain electrode and the grid electrode which are required by the gallium nitride transistor on the back surface of the original wafer, and greatly improves the performance, the excellent rate and the reliability of a final product.)

1. A manufacturing method of a GaN device is characterized by comprising the following steps:

providing a semiconductor substrate;

growing a buffer layer on the semiconductor substrate;

growing a first GaN layer on the buffer layer;

growing an AlGaN layer on the first GaN layer;

a second GaN layer is grown on the AlGaN layer;

turning over the wafer obtained in the step to enable the semiconductor substrate to face upwards;

sequentially removing the semiconductor substrate and the buffer layer;

thinning the first GaN layer, and defining a pattern of the first GaN layer;

growing an insulating layer on the first GaN layer, and carrying out planarization treatment on the insulating layer;

and preparing an electrode on the insulating layer.

2. The method of claim 1, wherein said fabricating an electrode on said insulating layer comprises:

etching the insulating layer, and forming through holes of a source electrode, a drain electrode and a grid electrode in the insulating layer;

depositing a conductive material in the via;

depositing a metal layer on the insulating layer;

and defining the source electrode, the drain electrode and the grid electrode pattern of the metal layer.

3. The method of claim 1, wherein:

the semiconductor substrate is a Si substrate.

4. The method of claim 1, wherein:

the buffer layer is made of materials comprising AlN, AlGaN, GaN and other materials through cross combination.

5. The method of claim 1, wherein:

the composition material of the insulating layer comprises at least one of SiO and SiN.

6. The method of claim 2, wherein:

the conductive material comprises at least one of tungsten, aluminum, copper and titanium.

7. A GaN device, characterized in that the GaN device comprises:

a second GaN layer;

an AlGaN layer on the second GaN layer;

the first GaN layer is positioned on the AlGaN layer and is etched into a required pattern;

an insulating layer on the first GaN layer;

and the source electrode, the drain electrode and the grid electrode of the device are positioned above the insulating layer.

8. The structure of a GaN device of claim 7 wherein:

the insulating layer further comprises a through hole penetrating through the insulating layer, the metal layers of the source electrode, the drain electrode and the grid electrode are connected to the upper portion of the through hole, the first GaN layer or the AlGaN layer is connected to the lower portion of the through hole, and conducting materials are deposited inside the through hole.

Technical Field

The invention relates to the technical field of GaN device preparation, in particular to a manufacturing method of a GaN device and the GaN device.

Background

The third generation semiconductor is a semiconductor material represented by gallium nitride (GaN), silicon carbide (SiC), zinc oxide (ZnO) and diamond, and among them, gallium nitride (GaN) and silicon carbide (SiC) are mainly used for the mature technology. At present, gallium nitride (GaN) is mainly used in the fields of optoelectronic products, high power devices, high frequency microwave devices and communication base stations. The third generation semiconductor has the advantages of high temperature resistance, high pressure resistance, high energy conversion efficiency, low loss, strong conductivity, high working speed, high switching frequency, suitability for high-frequency environment, high power density and the like in performance.

Compared with transistors adopting other semiconductor technology processes, the GaN transistor has the greatest advantage that internal stress is formed due to mismatching of lattice constants of gallium nitride and aluminum gallium nitride, a piezoelectric effect is generated, and a layer of conductive two-dimensional electron gas is formed on the lower surface of the aluminum gallium nitride. But also because of the lattice constant mismatch, gallium nitride and aluminum gallium nitride layers form numerous lattice defects. These lattice defects affect the device performance of the gan transistor, and more seriously, the reliability of the gan transistor.

Gallium nitride materials have relatively poor thermal conductivity. When the gallium nitride transistor is used, the original lattice defects can continuously grow under the action of stress due to the cold and heat impact of the environment, and the performance of the device is degraded. The conductivity of gallium nitride materials is also relatively poor. When the lattice defects in the gallium nitride layer are more and more, the (trap) charges are gathered, and when the electrons of the two-dimensional electron gas layer are more and more gathered at the local lattice defects and cannot flow away, the concentration and the mobility of carriers (two-dimensional electron gas) are greatly influenced, so that the performance of the gallium nitride transistor is rapidly and seriously degraded.

Disclosure of Invention

Accordingly, the present invention is directed to a method for fabricating a GaN device and a GaN device, in which a source, a drain and a gate required for a GaN transistor are fabricated on the back of an original wafer to reduce native lattice defects of the transistor, thereby greatly improving the performance, yield and reliability of the final product.

In a first aspect, the present invention provides a method for fabricating a GaN device, the method comprising the steps of:

providing a semiconductor substrate;

growing a buffer layer on the semiconductor substrate;

growing a first GaN layer on the buffer layer;

growing an AlGaN layer on the first GaN layer;

a second GaN layer is grown on the AlGaN layer;

turning over the wafer obtained in the step to enable the semiconductor substrate to face upwards;

sequentially removing the semiconductor substrate and the buffer layer;

thinning the first GaN layer, and defining a pattern of the first GaN layer;

growing an insulating layer on the first GaN layer, and carrying out planarization treatment on the insulating layer;

and preparing an electrode on the insulating layer.

Further, the preparing an electrode on the insulating layer includes:

etching the insulating layer, and forming through holes of a source electrode, a drain electrode and a grid electrode in the insulating layer;

depositing a conductive material in the via;

depositing a metal layer on the insulating layer;

and defining the source electrode, the drain electrode and the grid electrode pattern of the metal layer.

Further, the semiconductor substrate is a Si substrate;

the conductive material comprises at least one of tungsten, aluminum, copper and titanium.

Furthermore, the composition material of the buffer layer comprises AlN, AlGaN, GaN and other material films which are combined in a crossed manner;

the composition material of the insulating layer comprises at least one of SiO and SiN.

In a second aspect, the present invention also provides a GaN device, wherein the GaN device comprises:

a second GaN layer;

an AlGaN layer on the second GaN layer;

the first GaN layer is positioned on the AlGaN layer and is etched into a required pattern;

an insulating layer on the first GaN layer;

and the source electrode, the drain electrode and the grid electrode of the device are positioned above the insulating layer.

Furthermore, the insulating layer also comprises a through hole penetrating through the insulating layer, the upper part of the through hole is connected with the metal layers of the source electrode, the drain electrode and the grid electrode, the lower part of the through hole is connected with the first GaN layer or the AlGaN layer, and conductive materials are deposited in the through hole.

Compared with the prior art, the invention improves the manufacturing method of the GaN device, utilizes the more perfect gallium nitride and aluminum gallium nitride single crystals manufactured on the front surface of the growth substrate to manufacture the gallium nitride transistor, prepares the source electrode, the drain electrode and the grid electrode required by the gallium nitride transistor on the back surface of the original wafer, reduces the original lattice defects of the transistor, and greatly improves the performance, the yield and the reliability of the final product.

For a better understanding and practice, the invention is described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a schematic structural view of a GaN device fabricated by a conventional GaN device fabrication method;

FIG. 2 is a schematic structural diagram corresponding to steps S1-S5 in the method for fabricating a GaN device according to the embodiment of the invention;

FIG. 3 is a schematic structural diagram of a GaN device according to an embodiment of the invention after the wafer is turned over;

FIG. 4 is a schematic structural view of a GaN device according to an embodiment of the invention after removing the semiconductor substrate and the buffer layer;

FIG. 5 is a schematic structural diagram of a GaN layer after a first GaN layer is thinned and a pattern is defined in the method for manufacturing a GaN device according to the embodiment of the invention;

FIG. 6 is a schematic structural diagram of an insulating layer formed in the method for fabricating a GaN device according to the embodiment of the invention;

FIG. 7 is a schematic structural diagram of a via hole formed in an insulating layer in a method for fabricating a GaN device according to an embodiment of the invention;

FIG. 8 is a schematic structural diagram of a source, a drain and a gate formed in the method for fabricating a GaN device according to the embodiment of the invention;

fig. 9 is a schematic structural view of a gallium nitride transistor manufactured by the method for manufacturing a GaN device according to the embodiment of the present invention.

Wherein the reference numerals are:

1. a semiconductor substrate; 2. a buffer layer; 3. a first GaN layer; 31. a processed first GaN layer; 4. an AlGaN layer; 5. a second GaN layer; 6. an insulating layer; 61. a through hole; 71. a source electrode; 72. a gate electrode; 73. and a drain electrode.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that the embodiments described are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the embodiments in the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims. In the description of the present application, it is to be understood that the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not necessarily used to describe a particular order or sequence, nor are they to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

When growing a gallium nitride (GaN) layer on a silicon (Si) or silicon carbide (SiC) substrate, in order to alleviate and release lattice defects caused by stress due to mismatch of lattice constants, technicians usually grow Buffer layers (Buffer layers) layer by layer on a silicon or silicon carbide substrate, and finally grow a gallium nitride layer and an aluminum gallium nitride layer required for a gallium nitride transistor.

The applicants have found through a large amount of experimental data that there are many more lattice defects at the bottom, and the more the epitaxial layer is up, the less lattice defects and the lower the density. As shown in fig. 1, the white lines are lattice defects, and the defect density of the underlying buffer layer is very high, while the defect density of the gan layer immediately above the underlying buffer layer is gradually reduced but not completely disappeared. And the lattice defects of the aluminum gallium nitride layer grown on the gallium nitride layer and the gallium nitride layer on the surface layer completely disappear.

The fewer lattice defects that are grown in, the less the probability of new lattice defects being subsequently formed. The less the grown-in lattice defects, the slower the growth rate of the lattice defects. Therefore, the use of near-perfect gallium nitride and aluminum gallium nitride single crystals for fabricating gallium nitride transistors will greatly improve the performance, yield and reliability of the final product.

The idea of the invention is to use the original surface more perfect gallium nitride and aluminum gallium nitride single crystal to make gallium nitride transistor. And manufacturing a source electrode, a drain electrode and a grid electrode which are required by the gallium nitride transistor on the back surface of the original wafer.

As shown in fig. 2, according to the above inventive concept, the present invention provides a method for fabricating a GaN device, the method comprising the steps of:

s1: a semiconductor substrate 1 is provided.

The semiconductor substrate 1 serves only as a growth substrate, an epitaxial layer is grown thereon, and the epitaxial layer does not serve as a working substrate. In the present embodiment, the semiconductor substrate 1 is a Si substrate, and in other embodiments, the semiconductor substrate 1 may be a SiC substrate or a sapphire substrate.

S2: a buffer layer 2 is grown on the semiconductor substrate 1.

Specifically, the buffer layer 2 may be formed by alternately combining thin films of materials such as AlN, AlGaN, and GaN.

S3: a first GaN layer 3 is grown on the buffer layer 2.

The buffer layer 2 serves to separate the first GaN layer 3 from the semiconductor substrate 1, reducing lattice defects.

S4: an AlGaN layer 4 is grown on the first GaN layer 3.

S5: a second GaN layer 5 is grown on the AlGaN layer 4.

S6: and turning over the wafer obtained in the above step so that the semiconductor substrate 1 faces upwards.

After turning the wafer obtained in the above step over, the semiconductor substrate 1 of the original wafer is facing upward, the second GaN layer 5 is used as a new base, and the subsequent operations of removing, epitaxially growing, preparing electrodes, etc. are all performed on the back side of the original wafer, as shown in fig. 3.

S7: sequentially removing the semiconductor substrate 1 and the buffer layer 2;

the structure of the semiconductor substrate 1 and the buffer layer 2 after being removed is shown in fig. 4, wherein the removing process technology may be a dry etching method, in which the semiconductor substrate 1 is removed by a physical or chemical reaction (or a combination of the physical and chemical reactions) between plasma gas and a silicon wafer, and then the buffer layer 2 is removed by the same technology. In other embodiments, a wet etching or chemical mechanical polishing removal process may be used.

S8: the first GaN layer 3 is thinned, and the pattern of the first GaN layer 3 is defined.

The structure is shown in fig. 5. The thinning process may be dry etching, wet etching, or chemical mechanical polishing, and the like, and a geometric pattern structure is etched on the photoresist layer by exposure and development through a photolithography process, and then a pattern on the photomask is transferred onto the substrate through an etching process to define a pattern of the first GaN layer 3, thereby obtaining the processed first GaN layer 31.

S9: an insulating layer 6 is grown on the processed first GaN layer 31, and planarization processing is performed.

The structure after the planarization process is shown in fig. 6. An insulating layer 6 is grown on the processed first GaN layer 31, and the insulating layer 6 is planarized by chemical mechanical polishing. Preferably, the constituent material of the insulating layer 6 includes silicon oxide or silicon nitride.

S10: a source electrode 71, a gate electrode 72 and a drain electrode 73 are prepared on the insulating layer 6.

In the present embodiment, the step of preparing the source electrode 71, the gate electrode 72, and the drain electrode 73 on the insulating layer 6 includes:

s101: forming a via hole 61 for the source electrode 71, the gate electrode 72 and the drain electrode 73 in the insulating layer 6;

s102: depositing a conductive material in the via 61;

conductive materials, including tungsten, aluminum, copper, titanium, etc., may be deposited within the via 61 by using a thin film deposition process.

S103: depositing a metal layer on the insulating layer 6;

the metal layer is used to electrically connect the source electrode 71, the gate electrode 72, the drain electrode 73 and an external circuit.

S104: the source 71, the gate 72 and the drain 73 of the metal layer are patterned.

Through the photolithography process, the metal layer patterns of the source electrode 71, the gate electrode 72, and the drain electrode 73 are defined according to the functions required by the electrodes, and the structure is as shown in fig. 8.

Preferably, the thickness of each epitaxial layer is in the range of 0.001-10 μm.

As shown in fig. 9, the GaN transistor fabricated by the method of fabricating a GaN device according to the present invention uses near-perfect GaN and algan single crystals, and the two-dimensional electron gas layer formed between the algan layer and the GaN layer is greatly improved in concentration, mobility, reliability, and the like.

The present invention also provides a GaN device, wherein the GaN device is preferably manufactured by the GaN device manufacturing method of the present invention, and the structure of the GaN device is shown in fig. 7, which includes:

a second GaN layer 5;

an AlGaN layer 4 on the second GaN layer 5;

a first GaN layer 3 on the AlGaN layer 4, the first GaN layer 3 being subjected to thinning treatment and patterning treatment;

an insulating layer 6 on the processed first GaN layer 31;

a source 71, a drain 73 and a gate 72 of the device, located above said insulating layer 6;

the insulating layer 6 includes a via 61 penetrating the insulating layer 6, and a conductive material is deposited in the via 61 to form a source electrode 71, a gate electrode 72, and a drain electrode 73, respectively.

Compared with the prior art, the invention improves the manufacturing method of the GaN device, utilizes the more perfect gallium nitride and aluminum gallium nitride single crystals manufactured on the front surface of the growth substrate to manufacture the gallium nitride transistor, prepares the source electrode, the drain electrode and the grid electrode required by the gallium nitride transistor on the back surface of the original wafer, reduces the original lattice defects of the transistor, and greatly improves the performance, the yield and the reliability of the final product.

The above-mentioned embodiments only express one embodiment of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.