阅读说明：本技术 一种FinFET制造方法 (FinFET manufacturing method ) 是由 张峰溢 于 2020-05-27 设计创作，主要内容包括：本发明公开了一种FinFET制造方法,包括：采用多重图形化掩膜工艺形成包括衬底、第一氧化层、硬掩膜层、第二氧化层和多个间隔件的结构；对上述图形化的结构进行蚀刻,在与多个间隔件位置对应的部分形成多个鳍片,每个鳍片上方形成有第一氧化层、硬掩膜层和第二氧化层；在相邻两个鳍片之间形成浅沟道隔离区,浅沟道隔离区的高度与鳍片的高度相同；对每个浅沟道隔离区进行凹陷处理在相邻两个鳍片之间形成凹槽,以露出鳍片的上部；在每个鳍片和每个凹槽表面沉积ALD薄膜；对沉积有ALD薄膜的多个鳍片和凹槽进行切割处理。由此,可以看到通过本发明方法制得的FinFET结构的鳍片并无倾斜、凹槽边缘对称、凹槽深度相同且鳍片特征尺寸相同。(The invention discloses a FinFET manufacturing method, which comprises the following steps: forming a structure comprising a substrate, a first oxide layer, a hard mask layer, a second oxide layer and a plurality of spacers by adopting a multiple patterning mask process; etching the patterned structure, forming a plurality of fins at the parts corresponding to the spacers, and forming a first oxide layer, a hard mask layer and a second oxide layer above each fin; forming a shallow trench isolation region between two adjacent fins, wherein the height of the shallow trench isolation region is the same as that of the fins; carrying out a recess treatment on each shallow trench isolation region to form a groove between two adjacent fins so as to expose the upper parts of the fins; depositing an ALD thin film on the surface of each fin and each groove; and cutting the plurality of fins and grooves on which the ALD thin films are deposited. Thus, it can be seen that the fin of the FinFET structure made by the method of the present invention has no tilt, symmetric groove edges, the same groove depth and the same fin feature size.)

1. A method of FinFET fabrication, comprising:

forming a structure comprising a substrate, a first oxide layer, a hard mask layer, a second oxide layer and a plurality of spacers by adopting a multiple patterning mask process;

etching the patterned structure, forming a plurality of fins at the parts corresponding to the positions of the spacers, and forming the first oxide layer, the hard mask layer and the second oxide layer above each fin;

forming a shallow trench isolation region between two adjacent fins, wherein the height of the shallow trench isolation region is the same as that of the fins;

carrying out recess treatment on each shallow trench isolation region to form a groove between two adjacent fins so as to expose the upper parts of the fins;

depositing an ALD thin film on the surface of each fin and each groove;

and cutting the plurality of fins and grooves on which the ALD thin film is deposited.

2. The FinFET manufacturing method of claim 1, wherein the ALD thin film is one of SiN, SiOCN, TiN, TaN.

3. The method of claim 1, wherein the substrate is Si and the hard mask layer is SiN.

4. The method of manufacturing a FinFET in claim 1, wherein said step of forming shallow trench isolation regions between two adjacent fins comprises:

uniformly covering a liner oxide layer between every two adjacent fins and above the fins;

and carrying out chemical mechanical polishing treatment to enable the upper surface of the liner oxide layer and the top of the fin to be flat, so that the first oxide layer, the hard mask layer and the second oxide layer are removed.

5. The method of claim 4, wherein a liner oxide layer is uniformly coated between adjacent two of the fins and over the plurality of fins by one of ISSG, ALD-Ox, FCVD.

6. The method of FinFET fabrication of claim 1, wherein the step of cutting the plurality of fins and grooves with the ALD thin film deposited thereon comprises:

removing the dummy fins and the corresponding grooves at the edge part;

depositing an oxide layer between and above the remaining fins and grooves;

performing oxygen etch-back treatment to expose the ALD thin film;

removing the ALD thin film.

7. The FinFET fabrication method of claim 6, wherein the ALD thin film is removed by one of plasma isotropic etching, chemical isotropic etching, or wet etching.

8. A FinFET formed in accordance with the FinFET fabrication method of claims 1-7.

9. The FinFET of claim 8, wherein different gate bottom structures are formed by controlling oxygen etch back process depth.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a FinFET manufacturing method.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and the integration degree of the semiconductor device are improved, the gate size of the planar transistor is shorter and shorter, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.

A Fin Field effect transistor (FinFET) is a new type of mosfet, which includes narrow and isolated silicon strips (i.e., vertical channel structures, also called fins) with gate structures on both sides of the Fin. The FinFET structure makes the device smaller and has higher performance.

The existing FinFET manufacturing method comprises the following flows: forming a structure comprising a substrate, a first oxide layer, a mask layer, a second oxide layer and a spacer by adopting a multiple patterning mask process; etching the patterned structure to form a fin; preliminarily cutting the structure with the fins; forming a shallow trench isolation region on the cut structure; and forming a groove in the shallow channel isolation region.

FIG. 1 is a cross-sectional view of a prior art FinFET structure formed by a fabrication method; as shown in fig. 1, the FinFET manufactured by the above method has the disadvantages of fin tilt, asymmetric groove edges, different fin recess depths, and non-uniform fin feature sizes.

Disclosure of Invention

The invention aims to provide a FinFET manufacturing method.

The technical scheme adopted by the invention is as follows: a FinFET fabrication method is constructed, comprising the steps of:

forming a structure comprising a substrate, a first oxide layer, a hard mask layer, a second oxide layer and a plurality of spacers by adopting a multiple patterning mask process;

etching the patterned structure, forming a plurality of fins at the parts corresponding to the positions of the spacers, and forming the first oxide layer, the hard mask layer and the second oxide layer above each fin;

forming a shallow trench isolation region between two adjacent fins, wherein the height of the shallow trench isolation region is the same as that of the fins;

carrying out recess treatment on each shallow trench isolation region to form a groove between two adjacent fins so as to expose the upper parts of the fins;

depositing an ALD thin film on the surface of each fin and each groove;

and cutting the plurality of fins and grooves on which the ALD thin film is deposited.

In the FinFET manufacturing method provided by the invention, the ALD thin film is one of SiN, SiOCN, TiN and TaN.

In the FinFET manufacturing method provided by the invention, the substrate is Si, and the hard mask layer is SiN.

In the FinFET manufacturing method provided in the present invention, the step of forming a shallow trench isolation region between two adjacent fins includes:

uniformly covering a liner oxide layer between every two adjacent fins and above the fins;

and carrying out chemical mechanical polishing treatment to enable the upper surface of the liner oxide layer and the top of the fin to be flat, so that the first oxide layer, the hard mask layer and the second oxide layer are removed.

In the FinFET manufacturing method provided by the invention, a liner oxide layer is uniformly covered between two adjacent fins and above the plurality of fins through one of ISSG, ALD-Ox and FCVD.

In the FinFET manufacturing method provided by the invention, the step of cutting the plurality of fins and grooves deposited with the ALD thin film comprises the following steps:

removing the dummy fins and the corresponding grooves at the edge part;

depositing an oxide layer between and above the remaining fins and grooves;

performing oxygen etch-back treatment to expose the ALD thin film;

removing the ALD thin film.

In the FinFET fabrication method provided by the present invention, the ALD thin film is removed by one of plasma isotropic etching, chemical isotropic etching or wet etching.

There is also provided in accordance with another aspect of the present invention a FinFET fabricated in accordance with the method described above.

In the FinFET provided by the invention, different gate bottom structures are formed by controlling the depth of oxygen etch-back treatment.

The FinFET manufacturing method has the following beneficial effects: the FinFET manufacturing method provided by the invention can avoid the generation of inclined fins by carrying out shallow trench isolation treatment on all the fins; by carrying out recess treatment on the shallow trench isolation regions between the fins, the problems of different fin recess depths and uneven fin characteristic sizes in the finally formed FinFET structure can be avoided; protecting the groove depth in a subsequent cutting process by depositing an ALD thin film; the FinFET structure has no inclined fin, symmetrical notch edge, and the same notch depth and fin characteristic size.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:

FIG. 1 is a cross-sectional view of a prior art FinFET structure formed by a fabrication method;

FIG. 2 is a flow chart of a method of fabricating a FinFET in accordance with an embodiment of the present invention;

fig. 3-12 are schematic device structures during a method of fabricating a FinFET in accordance with an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the FinFET fabrication method of the present invention. It will be apparent that the invention may be practiced without limitation to specific details that are within the skill of one of ordinary skill in the semiconductor arts. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In order to solve the technical problems of the defects of the FinFET manufactured by the existing method, such as the inclination of the fin, the asymmetry of the edge of the groove, the different depth of the sunken part of the fin and the non-uniform characteristic dimension of the fin, the invention provides a FinFET manufacturing method, as shown in FIG. 2, the manufacturing method provided by the invention comprises the following steps:

step S1, forming a structure including a substrate, a first oxide layer, a hard mask layer, a second oxide layer and a plurality of spacers by using a multiple patterning mask process;

step S2, etching the patterned structure, forming a plurality of fins on portions corresponding to the spacers, and forming the first oxide layer, the hard mask layer, and the second oxide layer over each of the fins;

step S3, forming a shallow trench isolation region between two adjacent fins, wherein the height of the shallow trench isolation region is the same as that of the fins;

step S4, performing a recess process on each shallow trench isolation region to form a groove between two adjacent fins, so as to expose the upper portions of the fins;

step S5, depositing an ALD thin film on the surface of each fin and each groove;

and step S6, performing cutting processing (Fin cut) on the plurality of fins and grooves on which the ALD thin film is deposited.

Specifically, as shown in fig. 3 and 4, in step S1, a core component is first formed by using a multiple patterning mask process, where the core component includes the substrate 10, the first oxide layer 20, the hard mask layer 30, the second oxide layer 40, and the plurality of features 50; then, the plurality of features 50 are replaced with a plurality of spacers 60 over the second oxide layer 40, and the formation locations of subsequent fins are determined by the spacers 60. The substrate 10 may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), or the like. By way of example, in the present embodiment, the substrate 10 and features 50 are formed from a single crystal silicon material, and the hard mask layer 30 and spacers 60 are formed from a SiN material. It will be appreciated by those skilled in the art that the formation of the oxide layer, the hard mask layer and the spacers on the substrate may be performed according to conventional processes and will not be described in detail. Further, the multiple patterning mask process comprises: a Self-aligned Double patterning (SADP) process, or a Self-aligned quad patterning (SAQP) process.

Specifically, as shown in fig. 5, in step S2, the patterned structure is sequentially etched to form a plurality of fins 70 at portions corresponding to the spacers 60, and the first oxide layer 20, the hard mask layer 30 and the second oxide layer 40 are formed over each of the fins 70. The etching can also be carried out by conventional technical means by those skilled in the art, and will not be described herein.

Specifically, as shown in fig. 6, in step S3, a plurality of shallow trench isolation regions 80 having the same height as the fin height are formed between two adjacent fins 70. Firstly, a liner oxide layer is uniformly covered between two adjacent fins 70 and above the fins, and can be implemented by one of an In-Situ Vapor Generation (ISSG) process, an Atomic Layer Deposition (ALD) process, and a Fluid Chemical Vapor Deposition (FCVD) process; and then, carrying out chemical mechanical polishing treatment to flatten the upper surface of the liner oxide layer and the top of the fin so as to remove the first oxide layer, the hard mask layer and the second oxide layer. In the invention, the generation of inclined fins can be avoided by carrying out shallow trench isolation treatment on all the fins.

Specifically, as shown in fig. 7, in step S4, each of the shallow trench isolation regions 80 is recessed to form a groove 90 between two adjacent fins, so as to expose the upper portion of the fin. In the invention, by carrying out the recess treatment on the shallow trench isolation region between the fins, the problems of different fin recess depths and uneven fin characteristic sizes in the finally formed FinFET structure can be avoided.

Specifically, as shown in fig. 8, in step S5, an ALD thin film 100, which is one of SiN, SiOCN, TiN, TaN, is deposited on the surface of each fin 70 and each groove 90 to protect the groove depth in the subsequent cutting process.

Specifically, as shown in fig. 9 to 12, in step S6, a cutting process is performed on the plurality of fins and grooves on which the ALD thin film is deposited to remove dummy fins at the edges. As shown in fig. 9, the dummy fins and the corresponding grooves of the edge portion are removed first; as shown in fig. 10, an oxide layer 110 is deposited between and over the remaining fins and grooves; as shown in fig. 11, performing an oxygen etch-back process to expose the ALD film, which may be removed by one of plasma isotropic etching, chemical isotropic etching or wet etching, forming different gate bottom structures by controlling the depth of the oxygen etch-back process; the ALD thin film is removed as shown in fig. 12.

Fig. 12 is a cross-sectional view of a resulting FinFET structure in accordance with the present invention. Thus, it can be seen that the fin of the FinFET structure made by the method of the present invention has no tilt, symmetric groove edges, the same groove depth and the same fin feature size.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.