阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 任烨 胡建强 郑凯 杨芸 高颖 于 2020-05-28 设计创作，主要内容包括：本申请提供一种半导体结构及其形成方法,所述形成方法包括：提供半导体衬底,所述半导体衬底上依次形成有栅介质层、栅极层；去除部分所述栅极层、栅介质层及半导体衬底,形成沟槽；在所述沟槽中形成绝缘层,所述绝缘层的顶面低于所述半导体衬底的顶面；向所述半导体衬底的侧壁注入离子,形成源极和漏极。采用本申请的形成方法可以节省光罩成本,减少工艺步骤,避免半导体结构水平方向上无效面积的增加,在同等性能的情况下,可以大幅度缩小器件尺寸。(The application provides a semiconductor structure and a forming method thereof, wherein the forming method comprises the following steps: providing a semiconductor substrate, wherein a gate dielectric layer and a gate electrode layer are sequentially formed on the semiconductor substrate; removing part of the gate layer, the gate dielectric layer and the semiconductor substrate to form a groove; forming an insulating layer in the trench, wherein the top surface of the insulating layer is lower than the top surface of the semiconductor substrate; and implanting ions into the side wall of the semiconductor substrate to form a source electrode and a drain electrode. By adopting the forming method, the photomask cost can be saved, the process steps can be reduced, the increase of the invalid area of the semiconductor structure in the horizontal direction can be avoided, and the size of the device can be greatly reduced under the condition of the same performance.)

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein a gate dielectric layer and a gate electrode layer are sequentially formed on the semiconductor substrate;

removing part of the gate layer, the gate dielectric layer and the semiconductor substrate to form a groove;

forming an insulating layer in the trench, wherein the top surface of the insulating layer is lower than the top surface of the semiconductor substrate;

and implanting ions into the side wall of the semiconductor substrate to form a source electrode and a drain electrode.

2. The method as claimed in claim 1, wherein the gate layer is further formed with a patterned photoresist.

3. The method for forming a semiconductor structure according to claim 2, wherein the photoresist is used as a mask, and a dry etching process or a wet etching process is used to remove a part of the gate layer, the gate dielectric layer and the semiconductor substrate.

4. The method of claim 1, wherein the step of forming an insulating layer in the trench comprises:

depositing an insulating material layer in the groove and on the surface of the gate layer;

planarizing the insulating material layer to make the top surface of the planarized insulating material layer coplanar with the top surface of the gate layer;

and removing part of the insulating material layer in the groove to form an insulating layer, wherein the top surface of the insulating layer is lower than the top surface of the semiconductor substrate.

5. The method as claimed in claim 4, wherein the insulating material layer is partially removed by a dry or wet etching process.

6. The method according to claim 1, wherein a height difference between the top surface of the insulating layer and the top surface of the semiconductor substrate is greater than 0 and less than or equal to 50 nm.

7. The semiconductor structure of claim 1, wherein the insulating layer has a height of 150nm to 300 nm.

8. The semiconductor structure of claim 1, wherein the trench has an aspect ratio of (15-3) to 1.

9. The method of claim 1, wherein a source and a drain are formed in a portion of the semiconductor substrate above the insulating layer by tilted ion implantation.

10. The method as claimed in claim 9, wherein the step of performing the tilted ion implantation comprises:

performing first inclined ion implantation on one side of the part of the semiconductor substrate higher than the insulating layer;

and performing second inclined ion implantation on the other side of the part of the semiconductor substrate higher than the insulating layer.

11. The method according to claim 10, wherein an angle between the first and second tilted ion implantations is greater than 0 ° and less than or equal to 60 ° with respect to a vertical plane perpendicular to a surface of the semiconductor substrate.

12. The method as claimed in claim 10, wherein the first and second tilted ion implantations are provided at a concentration of 1E13 atoms/cm to 5E15 atoms/cm.

13. The method of claim 1, further comprising, after forming the source and drain electrodes: and forming an interlayer dielectric layer on the surfaces of the insulating layer and the grid layer, wherein the top surface of the interlayer dielectric layer on the surface of the insulating layer is coplanar with the top surface of the interlayer dielectric layer on the surface of the grid layer.

14. A semiconductor structure, comprising:

a semiconductor substrate;

the insulating layer is positioned in the semiconductor substrate, and the top surface of the insulating layer is lower than that of the semiconductor substrate;

the grid structure is positioned on the surface of the semiconductor substrate;

and the source electrode and the drain electrode are respectively positioned on two side walls of part of the semiconductor substrate and extend inwards.

15. The semiconductor structure of claim 14, wherein a height difference between the top surface of the insulating layer and the top surface of the semiconductor substrate is greater than 0 and less than or equal to 50 nm.

16. The semiconductor structure of claim 14, wherein the insulating layer has a height of 150nm to 300 nm.

17. The semiconductor structure of claim 14, wherein the trench has an aspect ratio of (15-3) to 1.

18. The semiconductor structure of claim 14, wherein the source and drain are located below the gate structure.

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

The conventional gate structure is spaced from the isolation trench by a certain distance, and when ion implantation is performed, ions can vertically penetrate through the surface of the semiconductor substrate in the spacing region, so that the ions are implanted into the semiconductor substrate.

However, as the size of the semiconductor device is smaller and smaller, there is no space between the gate structure and the isolation trench, so that the space for ion implantation is occupied, and ions are blocked by the polysilicon layer when implanted perpendicular to the semiconductor substrate, and cannot be directly implanted into the semiconductor substrate.

Disclosure of Invention

The technical problem that this application was solved is that the ion implantation space of small-size semiconductor device is crowded to be taken up the back, can't directly pour into the ion into semiconductor substrate.

In order to solve the technical problem, the application provides a method for forming a semiconductor structure, which comprises the steps of providing a semiconductor substrate, wherein a gate dielectric layer and a gate electrode layer are sequentially formed on the semiconductor substrate; removing part of the gate layer, the gate dielectric layer and the semiconductor substrate to form a groove; forming an insulating layer in the trench, wherein the top surface of the insulating layer is lower than the top surface of the semiconductor substrate; and implanting ions into the side wall of the semiconductor substrate to form a source electrode and a drain electrode.

In the embodiment of the present application, a patterned photoresist is further formed on the surface of the gate layer.

In the embodiment of the application, the photoresist is used as a mask, and a dry etching process or a wet etching process is adopted to remove part of the gate layer, the gate dielectric layer and the semiconductor substrate.

In an embodiment of the present application, the process of forming the insulating layer in the trench includes: depositing an insulating material layer in the groove and on the surface of the gate layer; planarizing the insulating material layer to make the top surface of the planarized insulating material layer coplanar with the top surface of the gate layer; and removing part of the insulating material layer to form an insulating layer, wherein the top surface of the insulating layer is lower than the top surface of the semiconductor substrate.

In the embodiment of the application, a dry etching process or a wet etching process is adopted to remove part of the insulating material layer.

In the embodiment of the present application, a height difference between the top surface of the insulating layer and the top surface of the semiconductor substrate is greater than 0 and less than or equal to 50 nm.

In the embodiment of the application, the height of the insulating layer is 150 nm-300 nm.

In the embodiment of the application, the depth-to-width ratio of the groove is (15-3): 1.

In the embodiment of the present application, a source electrode and a drain electrode are formed in a portion of a semiconductor substrate higher than an insulating layer by using an oblique ion implantation method.

In an embodiment of the present application, the process of the tilted ion implantation method includes: performing first inclined ion implantation on one side of the part of the semiconductor substrate higher than the insulating layer; and performing second inclined ion implantation on the other side of the part of the semiconductor substrate higher than the insulating layer.

In the embodiment of the present application, the angle of the first and second tilt ion implantations is greater than 0 ° and less than or equal to 60 ° with respect to a vertical plane perpendicular to the surface of the semiconductor substrate and with respect to a vertical plane perpendicular to the surface of the semiconductor substrate.

In the embodiment of the application, the concentration of the first inclined ion implantation and the second inclined ion implantation is 1E13 atoms/square centimeter to 5E15 atoms/square centimeter.

In the embodiment of the present application, after the forming the source and the drain, the method further includes: and forming an interlayer dielectric layer on the surfaces of the insulating layer and the grid layer, wherein the top surface of the interlayer dielectric layer on the surface of the insulating layer is coplanar with the top surface of the interlayer dielectric layer on the surface of the grid layer.

The present application further provides a semiconductor structure comprising: a semiconductor substrate; the insulating layer is positioned in the semiconductor substrate, and the top surface of the insulating layer is lower than that of the semiconductor substrate; the grid structure is positioned on the surface of the semiconductor substrate; and the source electrode and the drain electrode are respectively positioned on two side walls of a part of the semiconductor substrate and extend inwards.

In the embodiment of the present application, a height difference between the top surface of the insulating layer and the top surface of the semiconductor substrate is greater than 0 and less than or equal to 50 nm.

In the embodiment of the application, the height of the insulating layer is 150 nm-300 nm.

In the embodiment of the application, the depth-to-width ratio of the groove is (15-3): 1.

In the embodiment of the application, the source electrode and the drain electrode are positioned below the gate structure.

Compared with the prior art, the method for forming the semiconductor structure has the following excellent effects:

the height of the insulating layer is reduced, so that the top surface of the insulating layer is lower than the top surface of the semiconductor substrate, and partial side walls of the semiconductor substrate are exposed, thereby providing an implantation space for ion implantation; and injecting ions into the side wall of the semiconductor substrate to form a source electrode and a drain electrode, wherein the formed source electrode and the formed drain electrode are positioned below the gate dielectric layer, so that the increase of an invalid area of the semiconductor structure in the horizontal direction is avoided compared with the source electrode and the drain electrode in the semiconductor substrate positioned at two sides of the gate structure in the past, and the size of the device can be greatly reduced under the condition of the same performance.

Furthermore, a gate dielectric layer and a gate electrode layer are sequentially formed on the semiconductor substrate, and then the groove and the gate electrode structure can be formed only through one-time etching, so that the photomask cost is saved, and the process steps are reduced.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic diagram of a semiconductor structure corresponding to a method for forming a semiconductor structure;

FIG. 2 is a schematic diagram of another semiconductor structure;

FIG. 3 is a schematic flow chart illustrating a method of forming a semiconductor structure according to an embodiment of the present disclosure;

fig. 4 to 8 are schematic structural views of a semiconductor structure corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical solution of the present application will be described in detail below with reference to the embodiments and the accompanying drawings.

Referring to fig. 1, a method of forming a semiconductor structure includes: providing a semiconductor substrate 100, forming a gate dielectric layer 110 on the surface of the semiconductor substrate 100, then etching a part of the gate dielectric layer 110 and the semiconductor substrate 100, and forming a trench isolation structure 120 in the semiconductor substrate 100.

Then, a gate layer 130 is formed on the surface of the gate dielectric layer 110, and there is enough space between the gate layer 130 and the trench isolation structure 120, where ion implantation can be performed to form a source 140 and a drain 150.

However, the above-mentioned forming method requires two etching steps when forming the trench isolation structure 120 and the gate layer 130, so the mask cost is high. Meanwhile, in the case of the same size, in order to make sufficient space for ion implantation, the size of the gate layer 130 is relatively reduced, which increases the difficulty and precision of the process.

Referring to fig. 2, as device dimensions are further reduced, another semiconductor structure is presented. In the semiconductor structure, on the basis of the above semiconductor structure, a space between the gate layer 130 and the shallow trench isolation structure 120 is not reserved, that is, the sidewall of the trench isolation structure 120 and the sidewall of the gate layer 130 are in the same plane, which causes that ions are blocked by the gate layer 130 during vertical implantation and cannot be directly implanted into the semiconductor substrate 100.

Based on this, according to the method for forming the semiconductor structure in the technical scheme of the application, the structural relationship between the gate structure and the trench isolation structure is changed by changing the process steps, so that a small-sized device has a sufficient injection space during ion injection, the increase of an invalid area in the horizontal direction is avoided, and the process difficulty is reduced.

Referring to fig. 3, a method for forming a semiconductor structure according to an embodiment of the present application includes:

step S1, providing a semiconductor substrate, wherein a gate dielectric layer and a gate electrode layer are sequentially formed on the semiconductor substrate;

step S2, removing part of the grid layer, the grid dielectric layer and the semiconductor substrate to form a groove;

step S3, forming an insulating layer in the trench, wherein a top surface of the insulating layer is lower than a top surface of the semiconductor substrate;

step S4, implanting ions into the sidewalls of the semiconductor substrate to form a source and a drain.

Referring to fig. 3 and 4, a semiconductor substrate 200 is provided, and a gate dielectric layer 210 and a gate layer 220 are sequentially formed on the semiconductor substrate 200.

Wherein the semiconductor substrate 200 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and further includes a multilayer structure composed of the material layers or silicon-on-insulator (SOI), stacked-on-insulator (SSOI), or the like. In the embodiment of the present application, the constituent material of the semiconductor substrate 200 is single crystal silicon or silicon on insulator.

Sequentially forming a gate dielectric layer 210 and a gate electrode layer 220 on the semiconductor substrate 200, wherein the specific forming process comprises the following steps: forming a gate dielectric layer 210 on the semiconductor substrate 200 by a thermal oxidation method or a chemical vapor deposition method; the gate layer 220 is then formed on the gate dielectric layer 210 by cvd or lpcvd or pecvd processes.

The material of the gate dielectric layer 210 may be silicon oxide (SiO)₂) Or silicon oxynitride (SiON), etc. At smaller process nodes, the feature size of the gate layer 220 is small, and the gate dielectric layer 210 is preferably a high dielectric constant (high-K) material. The high-K material may include hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, among others. In some embodiments, hafnium oxide, zirconium oxide, or aluminum oxide. The thickness of the gate dielectric layer 210 may be 1nm to 10 nm.

The gate layer 220 may be a multi-layer structure comprising a semiconductor material, such as silicon, germanium, metal, or a combination thereof. In some embodiments, polysilicon. The thickness of the gate layer 220 may be 50 to 150 nm.

In some embodiments, a patterned photoresist (not shown) may be formed on the surface of the gate layer 220 to define a gate layer pattern.

Referring to fig. 5, a portion of the gate layer 220, the gate dielectric layer 210 and the semiconductor substrate 200 are removed to form a trench 230. In some embodiments, the photoresist layer is used as a mask, a dry etching process or a wet etching process is used to etch a portion of the gate layer 220, the gate dielectric layer 210 and the semiconductor substrate 200, and the photoresist layer on the surface of the gate layer 220 is removed by an ashing process. When a dry etch process is used, the etch gas may comprise CF₄、CHF₃、C₂F₆、C₄F₈、C₅F₈The flow of each etching gas can be designed according to the actual process conditions. When a wet etching process is used, the etching solvent may include HF and NH₄F, and the temperature during etching can be adjusted according to the actual process condition. In some embodiments, the depth-to-width ratio of the trench is (15-3): 1. The gate layer, the gate dielectric layer and the groove formed in the method can be formed only by one-step etching, so that the photomask cost is saved, and the process flow is simplified.

Referring to fig. 6, an insulating layer 240 is formed in the trench 230, and a top surface of the insulating layer 240 is lower than a top surface of the semiconductor substrate 200. In some embodiments, a layer of insulating material may be first deposited on the surface of the gate layer 220 and within the trench 230, for example, the layer of insulating material may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). The insulating material layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low dielectric constant material, and/or other suitable insulating material.

The layer of insulating material is then planarized, which may be by chemical mechanical polishing, so that the top surface of the layer of insulating material is coplanar with the top surface of the gate layer 220. Then, a portion of the insulating material layer is removed to form an insulating layer 240, and a top surface of the insulating layer 240 is lower than a top surface of the semiconductor substrate 200. In some embodiments, a portion of the insulating material layer may be removed by a dry etching process, and a gas of the dry etching process may include CF₄、CHF₃、C₂F₆、C₄F₈、C₅F₈The etching solvent can comprise HF and NH₄F, the gas flow of the dry etching and the temperature of the wet etching can be adjusted according to the actual process condition.

The height difference is formed between the insulating layer 240 and the semiconductor substrate 200, which provides an implantation space for the ion implantation process, so that the ion implantation process can be implanted along the vertical direction, and the size of the device in the horizontal direction is reduced. The "horizontal direction" as referred to herein means a direction along the channel, and the "vertical direction" means a direction perpendicular to the channel. In some embodiments, the height of the insulating layer 240 is 150nm to 300nm, and the height difference between the top surface of the insulating layer 240 and the top surface of the semiconductor substrate is greater than 0 and less than or equal to 50 nm.

Referring to fig. 7, ions are implanted into sidewalls of the semiconductor substrate 200 to form a source electrode 250 and a drain electrode 260. In the embodiment of the present application, two tilted ion implantations are performed, wherein a first tilted ion implantation is performed on one side of the portion of the semiconductor substrate 200 higher than the insulating layer 240, and then a second tilted ion implantation is performed on the other side. The order of forming the source 250 and the drain 260 is not limited, and in some embodiments, the first angled ion implantation forms the source 250 and the second angled ion implantation forms the drain 260.

In some embodiments, the first and second angled ion implantations are angled at greater than 0 ° and less than or equal to 60 ° with respect to a vertical plane perpendicular to the surface of the semiconductor substrate. The concentration of the first and second angled ion implantations is from 1E13 atoms/cm to 5E15 atoms/cm. The ion types of the first and second tilted ion implantations may be N-type or P-type, N-type ions such as phosphorus, arsenic, etc., P-type ions such as boron, boron fluoride, etc.

The source 250 and the drain 260 formed in the prior art are located in the semiconductor substrate on both sides of the gate structure, and the source 250 and the drain 260 formed in the embodiment of the present application are located below the gate dielectric layer 210, so that the size of the device formed in the embodiment of the present application can be greatly reduced in the case of achieving the same device efficiency.

Referring to fig. 8, after the source electrode 250 and the drain electrode 260 are formed, an interlayer dielectric layer 270 may be further formed on the surfaces of the insulating layer 240 and the gate layer 230, and a top surface of the interlayer dielectric layer 270 on the surface of the insulating layer 240 is coplanar with a top surface of the interlayer dielectric layer 270 on the surface of the gate layer 230. The material of the interlayer dielectric layer 270 may include SiO₂、SiN、HfO₂、HfN、Al₂O₃At least one of AlN, SiCN or SiOC.

In summary, the gate structure and the trench can be formed by only one etching in the forming method of the embodiment of the present application, so that the mask cost is saved, and the process steps are reduced. And horizontal direction ion implantation is improved into vertical direction ion implantation, and the formed source electrode and drain electrode are positioned in the semiconductor substrate below the gate dielectric layer, so that the increase of an invalid area of the semiconductor structure in the horizontal direction is avoided, and the size of the device can be greatly reduced under the condition of the same performance.

With continuing reference to fig. 7, embodiments of the present application further provide a semiconductor structure, comprising: a semiconductor substrate 200; an insulating layer 240 located in the semiconductor substrate 200, and a top surface of the insulating layer 240 is lower than a top surface of the semiconductor substrate; the gate structure is positioned on the surface of the semiconductor substrate 200 and comprises a gate dielectric layer 220 positioned on the surface of the semiconductor substrate 200 and a gate layer 230 positioned on the surface of the gate dielectric layer 220; and a source 250 and a drain 260 respectively located on two sidewalls of a portion of the semiconductor substrate 200 and extending inward. The source 250 and the drain 260 are located under the gate structure, specifically, under the gate dielectric layer 220.

In some embodiments, a height difference between a top surface of the insulating layer and a top surface of the semiconductor substrate is greater than 0 and less than or equal to 50 nm. The height of the insulating layer is 150 nm-300 nm. The depth-to-width ratio of the groove is (15-3) to 1.

In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.

It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.

Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.