阅读说明：本技术 超结晶体管器件和用于形成超结晶体管器件的方法 (Super junction transistor device and method for forming super junction transistor device ) 是由 H·韦伯 I·穆里 D·图图克 于 2021-05-26 设计创作，主要内容包括：公开了一种用于形成超结晶体管的漂移区域和超结晶体管器件的方法。该方法包括：在半导体主体中形成第一掺杂类型的多个第一区域和第二掺杂类型的多个第二区域,从而在半导体主体中交替布置第一区域和第二区域,其中,形成第一区域和第二区域包括：在至少一个半导体层中形成多个沟槽；将第一类型掺杂剂原子和第二类型掺杂剂原子注入到多个沟槽的相对侧壁中的每个中；用半导体材料填充多个沟槽；以及在热工艺中扩散第一类型掺杂剂原子和第二类型掺杂剂原子,使得第一类型掺杂剂原子形成第一区域,并且第二类型掺杂剂原子形成第二区域。多个沟槽中的每个具有第一宽度,沟槽被台面区域间隔开,台面区域均具有第二宽度,并且第一宽度大于第二宽度。(A method for forming a drift region of a superjunction transistor and superjunction transistor devices is disclosed. The method comprises the following steps: forming a plurality of first regions of a first doping type and a plurality of second regions of a second doping type in the semiconductor body so as to alternately arrange the first regions and the second regions in the semiconductor body, wherein forming the first regions and the second regions comprises: forming a plurality of trenches in at least one semiconductor layer; implanting first-type dopant atoms and second-type dopant atoms into each of opposing sidewalls of the plurality of trenches; filling the plurality of trenches with a semiconductor material; and diffusing the first type dopant atoms and the second type dopant atoms in a thermal process such that the first type dopant atoms form a first region and the second type dopant atoms form a second region. Each of the plurality of trenches has a first width, the trenches are separated by mesa regions, the mesa regions each have a second width, and the first width is greater than the second width.)

1. A method, comprising:

forming a plurality of first regions (21) of a first doping type and a plurality of second regions (22, 23) of a second doping type in a semiconductor body (100) such that the first regions (21) and the second regions (22, 23) are alternately arranged in the semiconductor body (100),

wherein forming the first and second regions (21, 22, 23) comprises:

forming a plurality of trenches (131) in at least one semiconductor layer (130);

implanting dopant atoms of a first type and dopant atoms of a second type into each of opposing sidewalls (133, 134) of the plurality of trenches (131);

filling the plurality of trenches (131) with a semiconductor material; and

diffusing the first type of dopant atoms and the second type of dopant atoms in a thermal process such that the first type of dopant atoms forms the first region (21) and the second type of dopant atoms forms the second region (22, 23),

wherein each of the plurality of trenches (131) has a first width (w131),

wherein the trenches (131) are spaced apart by mesa regions (135) each having a second width (w135), and

wherein the first width (w131) is greater than the second width (w 135).

2. The method of claim 1, wherein the first width (w131) is at least 1.05 times, at least 1.1 times, at least 1.2 times, or at least 1.5 times the second width (w 135).

3. The method according to claim 1 or 2, wherein the first width (w131) is less than 3 times the second width (w 135).

4. The method according to any one of claims 1 to 3, wherein the trench (131) has an aspect ratio in the range of 2: 1 and 3: 1.

5. The method according to any of the preceding claims, wherein the dopant atoms of the second type are implanted deeper into the sidewalls (133, 134) than the dopant atoms of the first type.

6. The method according to any one of the preceding claims,

wherein the first type of dopant atoms includes at least one of arsenic (As) and antimony (Sb) atoms, and

wherein the second type of dopant atoms include boron (B) atoms.

7. The method according to any of the preceding claims, wherein a deviation of a total amount of dopant atoms of the first type implanted into each of the sidewalls (133, 134) from a total amount of dopant atoms of the second type implanted into the respective sidewall is less than 5%, less than 2%, or less than 1%.

8. The method according to any one of the preceding claims, wherein filling the trench (131) comprises: an epitaxial layer is formed in the trench (131) and on top of the mesa region (135).

9. The method of any one of the preceding claims, wherein forming a plurality of trenches (131) in at least one semiconductor layer (130) comprises:

forming a plurality of semiconductor layers (130) one over the other₁、130_n) And forming the plurality of semiconductor layers (130)₁、130_n) Before the next semiconductor layer in the plurality of semiconductor layers (130)₁、130_n) A plurality of trenches (131) are formed in each of the plurality of grooves.

10. The method of any of the preceding claims, further comprising:

forming a control structure (3) having a plurality of source regions (32) of the first doping type and a plurality of body regions (31) of the second doping type such that:

each of the first regions (21) adjoins at least one of the plurality of body regions (31), and

each of the second regions (22) adjoins at least one of the plurality of body regions (31).

11. A super junction transistor device comprising:

a drift region having a plurality of first regions (21) of a first doping type and a plurality of second regions (22, 23) of a second doping type in a semiconductor body (100),

wherein the first regions (21) and the second regions (22, 23) are alternately arranged in the semiconductor body (100),

wherein the second regions (22, 23) comprise wide regions (22) having a first width (w22) and narrow regions (23) having a second width (w23),

wherein the wide regions (22) and the narrow regions (23) are alternately arranged, and

wherein the first width (w22) is at least 1.05 times the second width (w 23).

12. The superjunction transistor device of claim 11, wherein the first width (w22) is at least 1.1 times, at least 1.2 times, or at least 2 times the second width (w 23).

13. The superjunction transistor device of claim 11 or 12, wherein the first width (w22) is less than 5 times the second width (w23), less than 4 times the second width (w23), or less than 2 times the second width (w 23).

14. The superjunction transistor device of any of claims 11 to 13, wherein the effective dopant dose of the second type of dopant atoms in the wide region (22) deviates from the effective dopant dose of the second type of dopant atoms in the narrow region (23) by less than 10%, less than 5%, or less than 1%.

Technical Field

The present disclosure relates generally to superjunction transistor devices and methods for forming superjunction transistor devices, and in particular for forming drift regions of superjunction transistor devices.

Background

The superjunction device includes a drift region having at least one first region of a first doping type (conductivity type) and at least one second region of a second doping type (conductivity type) complementary to the first doping type. In some publications, at least one first doping type region is referred to as a drift region and at least one second doping type region is referred to as a compensation region.

The drift region of the superjunction device may include a plurality of first regions and second regions alternately arranged in the semiconductor body. There is a need to form such drift regions in a cost effective manner.

Disclosure of Invention

One example relates to a method. The method includes forming a plurality of first regions of a first doping type and a plurality of second regions of a second doping type in the semiconductor body such that the first regions and the second regions are alternately arranged in the semiconductor body. In this method, forming the first region and the second region includes: forming a plurality of trenches in at least one semiconductor layer; implanting dopant atoms of a first type and dopant atoms of a second type into each of opposing sidewalls of the plurality of trenches; filling the plurality of trenches with a semiconductor material; and diffusing the first type of dopant atoms and the second type of dopant atoms in a thermal process such that the first type of dopant atoms forms a first region and the second type of dopant atoms forms a second region. Each of the plurality of trenches has a first width and the trenches are separated by mesa regions each having a second width, wherein the first width is greater than the second width.

Another example relates to a superjunction transistor device. The transistor device comprises a drift region having a plurality of first regions of a first doping type and a plurality of second regions of a second doping type in a semiconductor body, wherein the first regions and the second regions are alternately arranged in the semiconductor body. The second regions comprise wide regions having a first width and narrow regions having a second width, wherein the wide regions and the narrow regions are alternately arranged, and wherein the first width is at least 1.05 times the second width.

Drawings

Examples are explained below with reference to the figures. The drawings are intended to illustrate certain principles and therefore only illustrate aspects necessary to understand these principles. The figures are not drawn to scale. In the drawings, like reference numerals designate similar features.

Fig. 1 shows a vertical cross-sectional view of a superjunction transistor device according to an example;

fig. 2 shows a horizontal cross-sectional view of one example of a drift region of a superjunction transistor device;

fig. 3 shows a flow chart of one example of a method for forming a drift region;

fig. 4A and 4B show vertical cross-sectional views of a first semiconductor layer during different process steps of a method for forming a drift region;

FIGS. 5A and 5B illustrate the first semiconductor layer shown in FIGS. 4A and 4B after another process step including forming a top layer;

FIG. 6 shows an example of a semiconductor body including a first semiconductor layer and a top layer;

figures 7A and 7B show an example of a semiconductor body comprising several first semiconductor layers and a top layer;

fig. 8 shows one example of a method for implanting dopant atoms of a first type and dopant atoms of a second type into sidewalls of a trench in a first semiconductor layer;

fig. 9A and 9B illustrate another example of a method for implanting dopant atoms of a first type and dopant atoms of a second type into sidewalls of a trench in a first semiconductor layer;

10A-10C illustrate doping profiles of first and second semiconductor regions of a drift region and associated electric fields in a blocking state of a transistor device;

fig. 11 shows doping profiles of first and second semiconductor regions according to another example;

fig. 12 illustrates one example of a control structure for the transistor device illustrated in fig. 1;

fig. 13 illustrates another example of a control structure for the transistor device shown in fig. 1; and is

Fig. 14 shows a perspective cross-sectional view of a superjunction transistor device according to another example.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form a part of the specification and are included to illustrate examples of how the invention may be used and practiced. It is to be understood that features of the various embodiments described herein may be combined with each other, unless explicitly stated otherwise.

Fig. 1 schematically shows a cross-sectional view of one section of a superjunction transistor device. The transistor device comprises a semiconductor body 100, wherein the semiconductor body 100 may comprise a conventional semiconductor material, such as silicon (Si) or silicon carbide (SiC). The transistor device comprises a drift region 20 in a semiconductor body 100, the drift region 20 having a plurality of first regions 21 of a first doping type (conductivity type) and a plurality of second regions 22, 23 of a second doping type (conductivity type) complementary to the first doping type. The first regions 21 and the second regions 22, 23 are alternately arranged in the semiconductor body 100 and a pn-junction is formed between each first region 21 and the corresponding adjacent second region 22, 23. For illustrative purposes only, in the example shown in fig. 1, the first regions 21 and the second regions 22, 23 are arranged alternately in the first lateral direction x of the semiconductor body 100.

Referring to fig. 1, the second regions 22, 23 include two different types of second regions, i.e., wide regions 22 and narrow regions 23, wherein the wide regions 22 and the narrow regions 23 are alternately arranged. In each case, the wide regions 22 and the adjacent narrow regions 23 are separated by a respective first region 21. Transistor devices having wide regions 22 and narrow regions 23 of the second doping type can be produced in a highly efficient manner, as will be explained in further detail herein below.

The wide region 22 has a first width w22 and the narrow region 23 has a second width w23 that is less than the first width w 22. According to an example, the first width w22 is at least 1.05 times the second width w23, w22 ≧ 1.05 xw 23. According to an example, the first width w22 is at least 1.1 times or at least 1.2 times the second width w 23. According to an example, the first width w22 is less than 5, 4 or 2 times the second width w 23.

Referring to fig. 1, each of the first region 21 and the second regions 22, 23 extends in a vertical direction z of the semiconductor body, wherein the vertical direction z is substantially perpendicular to the first lateral direction x. For example, the dimensions of the first and second regions 21, 22, 23 in the vertical direction depend inter alia on the desired voltage blocking capability of the transistor device and are selected between a few tens of micrometers and a few hundreds of micrometers.

The respective width w22, w23 of each of the second regions 22, 23 may vary along the vertical direction z, which may be due to manufacturing processes. Further, the widths w22 of the individual wide regions 22 may be slightly offset from each other, and the widths w23 of the individual narrow regions 23 may be slightly offset from each other. Thus, according to one example, the width w22 of a single wide region 22 represents the average width of such a wide region, and the widths w22 of multiple wide regions 22 represent the average width of the wide regions 22. In other words, the width w23 of a single narrow region 23 represents the average width of this narrow region, and the widths w23 of a plurality of narrow regions 23 represent the average width of the narrow regions 23. Thus, the width w21 of a single first region 21 represents the average width of that first region, and the width w21 of a plurality of first regions 21 represents the average width of the first regions 21.

According to an example, the transistor device is implemented such that at each vertical position of the semiconductor body 100, the effective dopant dose of the second type of dopant atoms in the wide regions 22 deviates from the effective dopant dose of the second type of dopant atoms in the narrow regions 23 by less than 10%, less than 5% or less than 1%. The "effective dopant dose" at the vertical position of the second regions 22, 23 is the integral of the effective (net) doping concentration of the second regions 22, 23 in a direction perpendicular to one of the pn-junctions formed between the second regions 22, 23 and the adjacent first region 21.

The first and second regions 21, 22, 23 may be elongated in the second lateral direction y of the semiconductor body 100. This is illustrated in fig. 2, which fig. 2 shows a horizontal cross-section of the semiconductor body in a horizontal cross-section a-a, which is a cross-section perpendicular to the vertical cross-section shown in fig. 1. According to an example, the second lateral direction y is substantially perpendicular to the first lateral direction x. By "elongate" is meant that the length of the first and second regions 21, 22, 23 is significantly greater than the respective width w21, w22, w 23. In the example shown in fig. 1 and 2, the widths w21, w22, w23 are dimensions in the first lateral direction x and the "length" is a dimension in the second lateral direction y of the semiconductor body 100. According to one example, "substantially greater" means that the ratio of the length to the width is greater than 10, greater than 100, or even greater than 1000.

Referring to fig. 1, the first region 21 is connected to a drain node D of the transistor device, and the second regions 22, 23 are connected to a source node S of the transistor device. The connections between the second regions 22, 23 and the source node S are only schematically shown in fig. 1. Examples of how these connections can be implemented are explained further below with reference to examples herein. The first region 21 is connected to the drain node D via the drain region 11 of the first doping type. The drain region 11 may adjoin the first region 21. However, it is not shown in fig. 1.

Optionally, as shown in fig. 1, a buffer region 12 of the first doping type is arranged between the drain region 11 and the first region 21. The buffer region 12 has a first doping type, i.e. the doping type of the drift region 21 and the drain region 11. According to an example, the doping concentration of the buffer region 12 is lower than the doping concentration of the drain region 11. The doping concentration of the drain region 11 is selected from, for example, 1E17(═ 10)¹⁷) cm^-3And 1E20 cm^-3And the doping concentration of the buffer region 12 is selected from, for example, 1E14 cm^-3And 1E17 cm^-3In the middle range. According to one example, the buffer region 12 comprises two or more differently doped sub-regions (not shown). One of these sub-regions may have 1E14 cm^-3And 5E15 cm^-3And another of these sub-regions may have a doping concentration of 5E15 cm^-3And 1E17 cm^-3With the doping concentration in between.

Referring to fig. 1, the transistor device further comprises a control structure 3 connected between the source node S and the first region 21. The control structure 3 is at least partially integrated in the semiconductor body 100. Examples of how the control structure 3 may be implemented are explained further below with reference to examples herein. The control structure further comprises a gate node G and is configured to be dependent on a voltage V between the gate node G and a source node S_GSTo control the conduction channel between the source node S and the first region 21. In the example shown in fig. 1, this function of the control structure 3 is represented by a switch connected between the source node S and the first region 21. Furthermore, the control structure 3 comprises a pn-junction between the first region 21 and the source node S. In the example shown in fig. 1, this pn-junction is represented by a bipolar diode connected between the first region 21 and the source node S.

The transistor device has a current flow direction, i.e. a direction in which a current can flow between a source node S and a drain node D inside the semiconductor body 100. In the example shown in fig. 1, the current flow direction corresponds to the vertical direction z of the semiconductor body 100, so that the drain region 11 is spaced apart from the control structure 3 in the vertical direction. The vertical direction z is a direction perpendicular to the first surface (not shown in fig. 1) and the second surface 102 formed by the drain region 11. The "vertical sectional view" shown in fig. 1 is a sectional view in a section perpendicular to the first surface and the second surface 102 and parallel to the vertical direction z. A section perpendicular to the vertical section shown in fig. 1 is referred to as a horizontal section.

The transistor device can be operated in a forward biased state and a reverse biased state. Whether the device is in a forward-biased state or a reverse-biased state depends on the drain-source voltage V_DSIs the drain node DAnd the source node S. In a reverse bias state, a drain-source voltage V_DSSuch that the diode (which may also be referred to as body diode) of the control structure 3 is reverse biased such that in this operating state the transistor device conducts current in accordance with the operating state of the control structure 3. In a forward biased state, the drain-source voltage V_DSSuch that the diode of the control structure 3 is reverse biased. In this forward biased state, the transistor device may be operated in an on-state or an off-state by the control structure 3. In the on-state, the control structure 3 creates a conductive channel between the source node S and the first region 21, so that a current can flow between the source node S and the drain node D via the control structure 3 and the first region 21 of the first doping type. In the off-state, the conductive channel is interrupted.

In the off state, the space charge region (depletion region) expands in the first region 21 and the second regions 22, 23, so that the first region 21 and the second regions 22, 23 can follow the drain-source voltage V_DSBecomes depleted of charge carriers. In this way, charge carriers in the first region 21 are "compensated" by charge carriers in the second regions 22, 23. Thus, the first region 21 may be implemented with a higher doping concentration, and thus, a lower resistance, than a conventional transistor device without the second region, without reducing the voltage blocking capability of the transistor device.

With reference to the above, the drift region 20 can be produced in a highly efficient manner, and therefore, a semiconductor device of the type shown in fig. 1 can be produced in a highly efficient manner. An example of a method for producing the drift region 20 is explained below.

Fig. 3 shows a flow diagram of a method according to an example. Referring to fig. 3, the method includes forming a plurality of trenches in at least one semiconductor layer, wherein each of the plurality of trenches has a first width, wherein the trenches are spaced apart by mesa regions each having a second width, and wherein the first width is greater than the second width (201). The method further comprises the following steps: implanting (202) dopant atoms of a first type and dopant atoms of a second type into each of opposing sidewalls of a plurality of trenches; filling the plurality of trenches (203) with a semiconductor material; and diffusing the first type of dopant atoms and the second type of dopant atoms in a thermal process such that the first type of dopant atoms form a first region and the second type of dopant atoms form a second region (204).

One example of forming a plurality of trenches and implanting dopant atoms of a first type and dopant atoms of a second type into sidewalls of the trenches is shown in fig. 4A and 4B. Each of these features shows a vertical cross-sectional view of a section of the semiconductor layer 130 during the fabrication process. This semiconductor layer 130 is also referred to as first semiconductor layer in the following. The first semiconductor layer 130 forms part of the semiconductor body 100 of the completed transistor device. At the moment of processing the first semiconductor layer 130, other regions of the semiconductor body 100 (for example the drain region 11 and the optional buffer region 12) may already have been formed. However, these other sections are not shown in fig. 4A and 4B.

Referring to fig. 4A, the method includes forming a plurality of trenches 131 in the first surface 132 of the semiconductor layer 130 such that each of the trenches 131 extends from the first surface 132 into the semiconductor layer 130. Forming the trench 131 may include: forming an etch mask 301 on top of the first surface 132; and etching those sections of the semiconductor layer 130 not covered by the etch mask 301. For example, etching the trench includes using an anisotropic etch process. Fig. 4A shows the first semiconducting layer 130 after etching the trench 131.

According to one example, the grooves 131 are elongated grooves. That is, the length of the trench 131 (i.e., the dimension of the trench 131 in the second lateral direction y) is significantly larger than the width w131 of the trench 131 (i.e., the dimension thereof in the first lateral direction x).

Each of the trenches 131 has a first sidewall 133 and an opposite second sidewall 134, wherein these sidewalls extend in the longitudinal direction (second transverse direction y) of the trench 131 and at least substantially in the vertical direction z. By "at least substantially" is meant that the sidewalls 133, 134 are at least substantially perpendicular to the first surface 132. That is, the sidewalls 133, 134 may be perpendicular to the first surface 101 or may be tapered. The tapered sidewalls are shown in dashed lines in fig. 4A. According to an example, the angle between each of the sidewalls 133, 134 and the first surface 132 (inside the first semiconductor layer 130) is between 90 ° and 100 °, in particular between 92 ° and 95 °.

Referring to fig. 4A, trenches 131 are spaced apart by mesa regions 135 such that each mesa region 135 is located between a respective pair of two adjacent trenches 131. Each of the mesa regions 135 has a width w135, i.e. the dimension of the respective mesa region 135 in the first lateral direction x. The width w131 of the trench 131 is also referred to as a first width hereinafter, and the width w135 of the mesa region 135 is also referred to as a second width hereinafter. With reference to the above, the trenches 131, and thus also the mesa regions 135, may be tapered. According to an example, the first width w131 of one groove represents an average width of the respective grooves 131, and the first widths w131 of the plurality of grooves 131 represent an average of the average widths of the grooves 131. In other words, the width w135 of one mesa region 135 represents an average width of the corresponding mesa region 135, and the widths w135 of a plurality of mesa regions 135 represents an average of the average widths of the mesa regions 135.

The first width w131 is greater than the second width w135, w131> w 135. According to an example, the first width w131 is at least 1.1 times, at least 1.2 times or at least 1.5 times the second width w135, such that the trench 131 is wider than the mesa region 135 in the first lateral direction x. According to an example, the first width w131 is less than three times the second width w135, w131<3 × w 135. According to an example, the first width w131 is between 0.5 micrometer (μm) and 6 micrometer, in particular between 1.5 micrometer and 3.5 micrometer.

The aspect ratio a131 of the trench 131 is given by the ratio between the depth d131 (i.e. the dimension of the trench in the vertical direction z) and the first width w131,

although it may be desirable to form trenches 131 having a large aspect ratio, the aspect ratio is generally limited by the process of filling trenches 131 with semiconductor material. It may be desirable to produce the semiconductor material filling the trenches 131 as a single crystal layer without any defects, such as voids. The larger the aspect ratio, the more difficult it is to fill the trench 131 with defect-free semiconductor material. Thus, according to an example, the trench 131 is formed such that its aspect ratio a131 is in the range of 2: 1 and 3: 1.

The pitch p of the trench structure shown in fig. 4A is given by the first width w131 plus the second width w135, i.e., the pitch is defined by one of the trenches 131 and the adjacent mesa region 135,

p＝w131+w135 (2)

this pitch of the trench structures is substantially equal to the center distance between two adjacent narrow regions 23 or the center distance between two adjacent wide regions 22 in the completed superjunction transistor device.

At a given pitch p of the trench structure and at a given aspect ratio a131 of the trench 131, implementing the trench 131 such that the first width w131 is greater than the second width w135 has the following effect: a deeper trench can be formed compared to the case where the first width w131 is equal to the second width w 135. The benefits of forming deeper trenches 131 are further explained below.

Referring to fig. 4B, the method further includes implanting dopant atoms of the first type and dopant atoms of the second type into each of the opposing first and second sidewalls 133, 134 to form implant regions 24 in the mesa region 135 along the sidewalls 133, 134 such that each of these implant regions 24 includes both dopant atoms of the first doping type and dopant atoms of the second doping type. Forming the implant region 24 may include a tilted implant process, wherein the implant mask 401 formed on top of the mesa region 135 may prevent dopant atoms from being implanted into the first surface 132. According to one embodiment, the implantation mask 401 is an etch mask 301.

Filling the plurality of trenches 131 with a semiconductor material and diffusing the first type of dopant atoms and the second type of dopant atoms according to process steps 202 and 203 (see fig. 2) is explained with reference to fig. 5A and 5B. Each of these figures shows the structure shown in fig. 4B after other process steps.

Fig. 5A shows the semiconductor layer 130 after filling the trench 131 with a semiconductor material. Filling the trench may include epitaxially growing the second semiconductor layer 140 on top of the first semiconductor layer 130 such that the trench is completely filled. Referring to fig. 5A, the second semiconductor layer 140 may be formed such that it fills the trench and additionally covers the first surface 131 of the first semiconductor layer 130 on top of the mesa region 135. Optionally, filling the trench comprises a planarization process, wherein the surface 141 of the second semiconductor layer 140 is planarized and/or wherein the thickness of the second semiconductor layer 140 above the mesa regions 135 is reduced. According to one example (not shown), the second semiconductor layer 140 is planarized or etched back down to the mesa region 135 such that only some sections of the second semiconductor layer 140 that fill the trenches 131 remain. Thus, the semiconductor layer 140 is formed such that it fills at least the trench 131 and, optionally, also on top of the mesa region 135.

Epitaxially growing the second semiconductor layer 140 results in a single crystal layer arrangement comprising the first layer 130 and the second layer 140. In this arrangement, there is no visible boundary between the first and second layers 130, 140. However, the boundary between the two semiconductor layers 130, 140 is shown in dashed lines in fig. 5A for illustrative purposes only.

Fig. 5B shows the layer arrangement shown in fig. 5A after a thermal process in which the dopant atoms of the first type and the dopant atoms of the second type comprised in the implanted regions 24 are diffused such that the dopant atoms of the first type form the first regions 21 and the dopant atoms of the second type form the second regions 22, 23. The dopant atoms of the first type and the dopant atoms of the second type are selected such that they have different diffusion coefficients, such that the annealing process results in a first region 21 having an effective doping concentration of the first doping type and a second region 22, 23 having an effective doping concentration of the second doping type. In the example shown in fig. 5B, the dopant atoms of the first type have a lower diffusion coefficient than the dopant atoms of the second type, so that the first region 21 is formed close to the position of the implantation region 24, and thus to the positions of the first and second sidewalls 133, 134, while the second regions 22, 23 are spaced apart from the previous positions of the sidewalls 133, 134.

According to one example, the first region 21 comprises n-type dopant atoms and the second regions 22, 23 comprise p-type dopant atoms. According to one example, the n-type dopant atoms include at least one of arsenic (As) atoms or antimony (Sb) atoms, and the p-type dopant atoms include boron (B) atoms, such that the first type of dopant atoms may include As atoms and/or Sb atoms, and the second type of dopant atoms may include B atoms. For example, in silicon, B atoms can diffuse up to four times faster than As atoms.

Due to the different diffusion coefficients, segregation of the dopant atoms of the first type and the dopant atoms of the second type may occur, resulting in a first region with an effective doping of the first doping type (net doping) and a second region 22, 23 with an effective doping of the second doping type. The first region 21 may include doping atoms of a second doping type in addition to the doping atoms of the first doping type. In the first region 21, however, dopant atoms of the first doping type predominate, so that an effective doping of the first dopant type is obtained. In other words, the second regions 22, 23 may comprise dopant atoms of the first doping type in addition to dopant atoms of the second doping type, wherein dopant atoms of the second doping type predominate.

Referring to fig. 5B, the narrow regions 23 of the second doping type are those regions formed in the previous mesa region 135. The wide regions 22 are those regions formed in the section of the second layer 140 of the trench 131 before filling.

It may be desirable to adjust the number of dopant atoms of the first type and the number of dopant atoms of the second type comprised in the layer arrangement precisely after the annealing process. According to an example, the first semiconductor layer 130 and the second semiconductor layer 140 are substantially "undoped" such that the number of dopant atoms of the first type and dopant atoms of the second type is substantially only limited byAnd defining an injection process. According to an example, undoped means that the base doping concentration of each of the first and second semiconductor layers 130, 140 is less than 1E14 cm^-3Or even less than 2E13 cm^-3。

After the annealing process, the first region 21 and the second regions 22, 23 form the drift region 20 of the superjunction transistor device. The drift region 20 may include only one first semiconductor layer 130 and one second semiconductor layer 140, which may also be referred to as a top layer. A semiconductor body 100 with a drift region 20 of this type is shown in fig. 6.

Fig. 6 shows the semiconductor body 100 of the superjunction transistor device after the annealing process and before the formation of the control structure 3. In this example, the semiconductor body 100 comprises a carrier 110 forming a drain region 11 and an optional buffer region 12, a first semiconductor layer 130 formed on top of the carrier 110, and a second semiconductor layer 140 formed on top of the first semiconductor layer 130. In this example, the surface 141 of the second semiconductor layer forms the surface 101 of the semiconductor body 100. According to an example, the first semiconductor layer 130 is epitaxially grown on the carrier 110. The carrier may comprise a highly doped semiconductor substrate forming the drain region 11 and optionally an epitaxial layer grown on the substrate forming the buffer region 12.

The drift region 20 is formed on the basis of only one first semiconductor layer 130 and the top layer 140, wherein trenches are formed only in the first semiconductor layer 130 and not in the top layer 140, which is merely an example. Basically, any number of first semiconductor layers may be formed on the carrier one above the other, wherein trenches are formed in each of the first semiconductor layers and the dopant atoms of the first and second type are implanted into opposite sidewalls of the trenches before the next or top layer of the first semiconductor layer is formed. The results of such a process are shown in fig. 7A.

Fig. 7A shows an example of a semiconductor body 100 comprising a carrier 110, a plurality of first semiconductor layers 130 formed one above the other on top of the carrier 110₁、130_nAnd formed on the first semiconductor layer 130₁、130_n130 of the top_nUpper top layer 140. According to an example, the carrier 110 comprises a drain region 11 and an optional buffer region 12. A plurality of first semiconductor layers 130₁、130_nFurther comprising a bottom-most layer 130 formed on top of the carrier 110₁. This bottommost semiconductor layer 130₁Has been processed in the same manner as the semiconductor layer 130 explained with reference to fig. 4A and 4B. I.e., in the bottommost semiconductor layer 130₁In which a plurality of trenches are formed and an implant region 24 has been formed in the mesa region along opposite sidewalls of the trenches.

A plurality of first semiconductor layers 130₁、130_nFurther comprising a further semiconductor layer 130_n. Other semiconductor layer 130_nFormed on the lowermost semiconductor layer 130₁Upper and fill the bottommost semiconductor layer 130₁Of the substrate. Other semiconductor layer 130_nHas been processed in the same manner as the semiconductor layer 130 shown in fig. 4A and 4B. That is, in the semiconductor layer 130_nTrenches have been formed and implanted regions 24 have been created along the opposing sidewalls of these trenches.

In the example shown in fig. 7A, the semiconductor body comprises two first semiconductor layers 130₁、130_nSo that the other semiconductor body 130_nForming a first semiconductor layer 130₁、130_nThe uppermost one of which forms a top layer 140 on top thereof. It goes without saying that the semiconductor layers 130 may be formed one above the other before the top-most layer 140 is formed₁、130_nAny number of first semiconductor layers 130 of the same type₁、130_nEspecially, more than 2, more than 5 or more than 10 first semiconductor layers 130 are formed₁-130_n。

Fig. 7B shows the arrangement shown in fig. 7A after an annealing process. As can be seen from fig. 7B, the annealing process results in a plurality of first regions 21 extending continuously in the vertical direction z and a plurality of second regions 22, 23 extending continuously in the vertical direction z of the semiconductor body 100.

In a superjunction transistor device, the voltage blocking capability depends strongly on the length d20 of drift region 20, where length d20 is the dimension of drift region 20 in vertical direction z. Furthermore, a reduction in the pitch of the trench structures (which also results in a reduction in the pitch of the completed superjunction transistor devices) may result in a reduction in the on-resistance of the transistor devices. On the other hand, reducing the pitch of the trench structure has the following effects: at a given aspect ratio of the trench, a trench having a smaller depth d131 is produced. For example, if the trench width w131 is equal to the mesa width w135, and the aspect ratio of the trench 131 is 2: 1, the trench depth is substantially given by the pitch p of the trench structure (p ═ w131+ w 135). Thus, as the pitch p decreases, the number of first semiconductor layers to be produced in order to achieve the desired length d20 of the drift region 20 increases. However, each additional semiconductor layer adds to the cost of the overall superjunction transistor device.

At a given pitch p of the trench structure and a given aspect ratio a131 of the trench 131, producing the trench 131 such that its width w131 is larger than the width w135 of the mesa region 135 has the following effect: to achieve the desired length d20 of the drift region 20, fewer first semiconductor layers are required than in the case where w131 is w 135. Thus, the method explained herein before is suitable for producing the drift region 20 of a superjunction transistor device in a very cost-effective manner.

With reference to the above, forming the drift region 20 of the superjunction transistor device includes: forming at least one first semiconductor layer 130; forming a plurality of trenches 131 in the at least one first semiconductor layer 130; forming implant region 24 in the mesa region along opposing sidewalls 133, 134 of trench 131; filling the trench 131 with a semiconductor material; and an annealing process. The implant region 24 may be formed in various ways.

According to one example shown in fig. 8, implanting dopant atoms of a first type and dopant atoms of a second type into each of the first and second sidewalls 133, 134 comprises: implanting molecules including both the first type of dopant atoms and the second type of dopant atoms into the first sidewall 133 in a first implantation process; and implanting molecules including both the first type of dopant atoms and the second type of dopant atoms into the second sidewall 134 in a second implantation process.

According to another example, the method includes implanting dopant atoms of the first type and dopant atoms of the second type into one sidewall in separate implantation processes. Referring to fig. 9A and 9B, this may include: as shown in fig. 9A, dopant atoms of the first type are implanted into the first sidewall 133 in a first implantation process, and dopant atoms of the first type are implanted into the second sidewall 134 in a second implantation process; and as shown in fig. 9B, the second type dopant atoms are implanted into the first sidewall 133 in a third implantation process, and the second type dopant atoms are implanted into the second sidewall 134 in a fourth implantation process.

Fig. 10A-10C show one example of doping concentrations of the first and second type of dopant atoms in the horizontal layer of the drift region 20 after an annealing process (fig. 10A), effective first type of dopant charges in the first region 21 and effective second type of dopant charges in the second regions 22, 23 after an annealing process (fig. 10B), and an effective drain-source voltage V after application of a drain-source voltage V_DSThe strength of the electric field in the first region 21 and the second regions 22, 23 in the off state of the superjunction transistor device. The "effective dopant charge" is the integral of the effective doping concentration in a vertical plane parallel to the pn-junction formed between the first and second regions 21, 22, 23.

In the example shown in fig. 10, although the transistor device comprises a wide second region 22 and a narrow second region 23, the maximum field strengths in the individual semiconductor regions 21, 22, 23 are substantially the same. This is highly desirable as it ensures that the voltage blocking capability is substantially the same for the pn junction formed between the first region 21 and the narrow second region 23, and for the pn junction formed between the first region 21 and the wide second region 22. This is basically achieved by: the annealing process is controlled such that the total number of dopant atoms in the narrow regions 23 is substantially equal to the total number of dopant atoms in the wide regions 22. The total number of dopant atoms is essentially given by the integral of the dopant charge. According to one example, the number of dopant atoms in the narrow regions 23 and the wide regions 22 may be balanced, for example, by appropriately selecting the duration and temperature of the annealing process. According to one example, the temperature is selected from between 1050 ℃ and 1100 ℃, and the duration is selected from between 250 minutes and 1000 minutes. For example, the duration may be selected according to the pitch of the previous trench structure, wherein the larger the pitch, the longer the diffusion time.

With reference to the above, the carrier 110 may include a semiconductor substrate. The substrate may include oxygen and/or COP (crystal oriented particles), which may diffuse into the at least one semiconductor layer 130. The diffusion of oxygen and/or COP into the at least one semiconductor layer 130 may have an effect on the diffusion of the first and second type dopant atoms. Thus, according to one example, the conditions of the temperature process (temperature, duration, … …) are selected depending on the concentration of oxygen and/or COP in the substrate.

According to one example, the process of forming the second regions 22, 23 such that each of these regions (in the same horizontal layer) has substantially the same number of dopant atoms may be supported by: the dopant atoms of the second type, which diffuse more rapidly, are implanted deeper into the first and second sidewalls 133, 134 than the dopant atoms of the first type, which diffuse more slowly. This is illustrated in fig. 11, which shows the concentration of the first type of dopant atoms and the second type of dopant atoms in the mesa region 135 after the implantation process and after the diffusion process. The implantation depth of the dopant atoms of the first and second types can be adjusted by appropriately adjusting the implantation energy.

The control structure 3 may be implemented in various ways, the control structure 3 being only schematically shown in fig. 1. Some examples are explained below. Typically, the control structure is formed in the semiconductor body 100 after the top layer 140 is formed and at least partially in the top layer. The control structure may be formed after the annealing process that forms the first and second regions 21, 22, 23. According to another example, the control structure 3 is at least partially formed before the annealing process, so that dopant atoms of the first and second regions 21, 22, 23 and dopant atoms of doped regions in the control structure can be diffused and activated using the same annealing process.

Fig. 12 shows an example of the control structure 3 in more detail. In addition to the control structure 3, a portion of the drift region 20 adjacent to the control structure 3 is also shown in fig. 12. In the example shown in fig. 12, the control structure 3 comprises a plurality of control units 30, which control units 30 may also be referred to as transistor units. Each of these control cells 30 comprises a body region 31 of the second doping type, a source region 32 of the first doping type, a gate electrode 33 and a gate dielectric 34. A gate dielectric 34 dielectrically insulates the gate electrode 33 from the body region 31. The body region 31 of each control cell 30 separates a respective source region 32 of the control cell 30 from at least one of the plurality of first regions 21. The source region 32 and the body region 31 of each of the plurality of control units 30 are electrically connected to the source node S. In this context "electrically connected" means an ohmic connection. That is, there is no rectifying junction between the source node S and the source region 32 and the body region 31. Only the source node S of the individual control cell 30 and the electrical connection between the source region 32 and the body region 31 are schematically shown in fig. 2. The gate electrode 33 of each control unit 30 is electrically connected to the gate node G.

With reference to the above, the main body area 31 of each control unit 30 adjoins at least one first area 21. Since the body region 31 belongs to the second doping type and the first regions 21 belong to the first doping type, a pn-junction exists between the body region 31 and at least one of the first regions 21 of each control unit 30. These pn-junctions form part of the pn-junction of the control structure 3 represented by a bipolar diode in the equivalent circuit diagram of the control structure 3 shown in fig. 1.

In the example shown in fig. 2, the gate electrode 33 of each control structure 30 is a planar electrode arranged on top of the first surface 101 of the semiconductor body 100 and is dielectrically insulated from the semiconductor body 100 by a gate dielectric 34. In this example, a section of the first region 21 adjacent to the individual body region 31 extends to the first surface 101.

Fig. 13 shows a control structure 3 according to another example. The control structure 3 shown in fig. 3 differs from the control structure 3 shown in fig. 2 in that: the gate electrode 33 of each control unit 30 is a trench electrode. This gate electrode 33 is arranged in a trench extending from the first surface 101 into the semiconductor body 100. As in the example shown in fig. 2, the gate dielectric 34 dielectrically insulates the gate electrode 33 from the respective body region 31. The body region 31 and the source region 32 of each control unit 30 are electrically connected to the source node S. Furthermore, the body region 31 adjoins at least one first region 21 and forms a pn-junction with the respective first region 21.

In the examples shown in fig. 12 and 13, the control structures 3 each comprise one gate electrode 33, wherein the gate electrode 33 of each control cell 30 is configured to control the conductive channel between the source region 32 and one first region 21 of the respective control cell 30 such that each control cell 30 is associated with one first region 21. Further, as shown in fig. 12 and 13, the body region 31 of each control unit 30 adjoins the at least one second region 22, 23 such that the at least one second region 22, 23 is electrically connected to the source node S via the body region 31 of the control unit 30. For illustrative purposes only, in the example shown in fig. 2 and 3, the body region 31 of each control unit 30 adjoins one second region 22, 23, so that each control unit 30 is associated with one second region. Further, in the example shown in fig. 2 and 3, the source regions 32 of two (or more) adjacent control cells 30 are formed of one doping region of the first doping type, the body regions 31 of two (or more) adjacent control cells 30 are formed of one doping region of the second doping type, and the gate electrodes 33 of two (or more) control cells 30 are formed of one electrode. The gate electrode 33 may include doped polysilicon, metal, or the like.

According to one example, the doping concentration of the source region 32 is selected from 1E18 cm^-3And 1E21 cm^-3And the doping concentration of the body region 31 is selected from 1E16 cm^-3And 5E18 cm^-3Within the range of (a).

As shown in fig. 12 and 13, associating one control unit 30 of the plurality of control units with one first area 21 and one second area 22 is merely an example. The embodiment and arrangement of the control unit 30 of the control structure 3 is to a large extent independent of the specific embodiment and arrangement of the first region 21 and the second regions 22, 23.

An example is shown in fig. 14, which shows that the embodiment and the arrangement of the control structure 3 are to a large extent independent of the embodiment and the arrangement of the first and second regions 21, 22. In the present example, the first region 21 and the second region 22 are elongated in the second lateral direction y of the semiconductor body 100, while the source region 32, the body region 31 and the gate electrode 33 of the individual control cells 30 of the control structure 3 are elongated in the first lateral direction x perpendicular to the second lateral direction y. In the present example, the body region 31 of one control unit 30 adjoins a plurality of first regions 21 and second regions 22.

The transistor device may be implemented as an n-type transistor device or a p-type transistor device. In an n-type transistor device, the first doping type, i.e. the doping type of the first region 21, the source region 32, the drain region 11 and the optional buffer region 12, is n-type, and the second doping type, i.e. the doping type of the second regions 22, 23 and the body region 31, is p-type. In a p-type transistor device, the aforementioned device regions have a doping type that is complementary to the doping type of the corresponding device region in an n-type transistor device.