阅读说明：本技术 形成半导体器件的方法 (Method of forming semiconductor device ) 是由 沙哈吉·B·摩尔 于 2021-03-09 设计创作，主要内容包括：形成半导体器件的方法包括形成具有多个半导体鳍的第一鳍组以及第二鳍组。多个半导体鳍包括在第一鳍组中最远离第二鳍组的第一半导体鳍、第二半导体鳍以及在第一鳍组中最靠近第二鳍组的第三半导体鳍。该方法还包括执行外延工艺以基于多个半导体鳍形成外延区域。外延区域包括第一部分和第二部分。第一部分位于第一半导体鳍和第二半导体鳍之间的中间。第一部分具有第一顶面。第二部分位于第二半导体鳍和第三半导体鳍之间的中间。第二部分具有比第一顶面低的第二顶面。(A method of forming a semiconductor device includes forming a first fin group having a plurality of semiconductor fins and a second fin group. The plurality of semiconductor fins includes a first semiconductor fin in the first group of fins furthest from the second group of fins, a second semiconductor fin, and a third semiconductor fin in the first group of fins closest to the second group of fins. The method also includes performing an epitaxial process to form an epitaxial region based on the plurality of semiconductor fins. The epitaxial region includes a first portion and a second portion. The first portion is located midway between the first semiconductor fin and the second semiconductor fin. The first portion has a first top surface. The second portion is located intermediate between the second semiconductor fin and the third semiconductor fin. The second portion has a second top surface lower than the first top surface.)

1. A method of forming a semiconductor device, comprising:

recessing isolation regions on opposing sides of the first, second, and third semiconductor strips to form first, second, and third semiconductor fins;

forming a gate stack on the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin;

forming gate spacers on sidewalls of the gate stack;

forming fin spacers on sidewalls of the first, second, and third semiconductor strips;

performing a recess process to recess the first, second, and third semiconductor strips to form first, second, and third grooves, respectively; and

performing an epitaxial process to form an epitaxial region starting from the first, second, and third grooves, wherein the epitaxial region includes a top surface comprising:

a convex portion above and laterally between the first and second semiconductor fins; and

a concave portion higher than and laterally between the second and third semiconductor fins.

2. The method of claim 1, wherein the fin spacer further comprises:

a first outer fin spacer having a first height;

a second outer fin spacer having a second height less than the first height; and

an interior spacer located between the first exterior fin spacer and the second exterior fin spacer, wherein a height of the interior spacer is less than the first height and the second height.

3. The method of claim 2, wherein the fin spacers are etched simultaneously during the recessing process, and further comprising, after the recessing process, further recessing the fin spacers.

4. The method of claim 2, wherein the first, second, and third semiconductor fins form a first fin group, wherein the first fin group is adjacent to a second fin group, and the second outer fin spacer faces toward the second fin group, and the first outer fin spacer faces away from the second fin group.

5. The method of claim 2, wherein top surfaces of the first, second, and third semiconductor fins are higher than top ends of the fin spacers after recessing the first, second, and third semiconductor fins.

6. The method of claim 1, wherein the epitaxial region comprises a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the third epitaxial layer comprises a first portion having the convex portion of the top surface and a second portion having the concave portion of the top surface, and wherein the method further comprises:

etching through the first portion of the third epitaxial layer to expose a recessed top surface of the second epitaxial layer.

7. The method of claim 6, further comprising forming a silicide region on the second epitaxial layer, wherein the silicide region comprises:

a first portion directly on the concave top surface of the second epitaxial layer; and

a second portion directly over the third semiconductor fin, wherein the first portion of the silicide region is higher than the second portion of the silicide region.

8. The method of claim 6, wherein the third epitaxial layer comprises a lower boron concentration than the second epitaxial layer.

9. A method of forming a semiconductor device, comprising:

forming a first fin group and a second fin group, wherein the first fin group comprises a plurality of semiconductor fins having an intra-group spacing, wherein the inter-group spacing of the first fin group and the second fin group is greater than the intra-group spacing, and wherein the plurality of semiconductor fins comprises:

a first semiconductor fin, wherein the first semiconductor fin is furthest away from the second set of fins in the first set of fins;

a second semiconductor fin; and

a third semiconductor fin, wherein the third semiconductor fin is closest to the second set of fins in the first set of fins; and

performing an epitaxial process to form an epitaxial region based on the plurality of semiconductor fins, wherein the epitaxial region comprises:

a first portion intermediate between the first and second semiconductor fins, wherein the first portion has a first top surface; and

a second portion located intermediate between the second semiconductor fin and the third semiconductor fin, wherein the second portion has a second top surface lower than the first top surface.

10. A method of forming a semiconductor device, comprising:

forming a first fin group and a second fin group, wherein the first fin group includes a plurality of semiconductor fins having an intra-group spacing, and the first fin group includes a first semiconductor fin furthest from the second fin group, a second semiconductor fin, and a third semiconductor fin closest to the second fin group;

forming a gate stack on the first set of fins;

forming gate spacers on sidewalls of the gate stack;

forming a fin spacer, the fin spacer comprising:

a first outer fin spacer facing the second set of fins, wherein the first outer fin spacer has a first height;

a second outer fin spacer facing away from the second set of fins, wherein the second outer fin spacer has a second height greater than the first height; and

an inner spacer located between the first outer fin spacer and the second outer fin spacer;

performing an epitaxy process to form a first epitaxy region based on the first set of fins and a second epitaxy region based on the second set of fins; and

forming source/drain contact plugs electrically interconnecting the first epitaxial region and the second epitaxial region.

Technical Field

Embodiments of the invention relate to methods of forming semiconductor devices.

Background

In the formation of a finfet, source/drain regions are typically formed by forming a semiconductor fin, recessing the semiconductor fin to form a recess, and growing an epitaxial region from the recess. The epitaxial regions grown from the grooves of adjacent semiconductor fins may merge with each other, and the resulting epitaxial regions may have a planar top surface. Source/drain contact plugs are formed to be electrically connected to the source/drain regions.

Disclosure of Invention

An embodiment of the present invention provides a method of forming a semiconductor device, including: recessing isolation regions on opposing sides of the first, second, and third semiconductor strips to form first, second, and third semiconductor fins; forming a gate stack on the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin; forming gate spacers on sidewalls of the gate stack; forming fin spacers on sidewalls of the first, second, and third semiconductor strips; performing a recess process to recess the first, second, and third semiconductor strips to form first, second, and third grooves, respectively; and performing an epitaxial process to form an epitaxial region starting from the first, second, and third grooves, wherein the epitaxial region includes a top surface comprising: a convex portion above and laterally between the first and second semiconductor fins; and a concave portion higher than and laterally between the second and third semiconductor fins.

Another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a first fin group and a second fin group, wherein the first fin group comprises a plurality of semiconductor fins having an intra-group spacing, wherein the inter-group spacing of the first fin group and the second fin group is greater than the intra-group spacing, and wherein the plurality of semiconductor fins comprises: a first semiconductor fin, wherein the first semiconductor fin is furthest away from the second set of fins in the first set of fins; a second semiconductor fin; and a third semiconductor fin, wherein the third semiconductor fin is closest to the second set of fins in the first set of fins; and performing an epitaxial process to form an epitaxial region based on the plurality of semiconductor fins, wherein the epitaxial region comprises: a first portion intermediate between the first and second semiconductor fins, wherein the first portion has a first top surface; and a second portion located intermediate between the second semiconductor fin and the third semiconductor fin, wherein the second portion has a second top surface lower than the first top surface.

Yet another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a first fin group and a second fin group, wherein the first fin group includes a plurality of semiconductor fins having an intra-group spacing, and the first fin group includes a first semiconductor fin furthest from the second fin group, a second semiconductor fin, and a third semiconductor fin closest to the second fin group; forming a gate stack on the first set of fins; forming gate spacers on sidewalls of the gate stack; forming a fin spacer, the fin spacer comprising: a first outer fin spacer facing the second set of fins, wherein the first outer fin spacer has a first height; a second outer fin spacer facing away from the second set of fins, wherein the second outer fin spacer has a second height greater than the first height; and an interior spacer located between the first exterior fin spacer and the second exterior fin spacer; performing an epitaxy process to form a first epitaxy region based on the first set of fins and a second epitaxy region based on the second set of fins; and forming source/drain contact plugs electrically interconnecting the first epitaxial region and the second epitaxial region.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1, 2A, 2B, 3A, 3B, 3C, 4A, 4B, 4C, 5-7, 8A, 8B, 9, 10, 11A, 11B, and 11C illustrate perspective and cross-sectional views of intermediate stages in the formation of a fin field effect transistor (FinFET), according to some embodiments.

Fig. 12 illustrates a process flow for forming an n-type FinFET and a p-type FinFET, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fin field effect transistors (finfets) and methods of forming the same are provided. According to some embodiments of the invention, a merged epitaxial region is formed based on a plurality of semiconductor fins forming a fin group, which may be a source/drain region of a FinFET. The merged epitaxial region includes at least a corrugated portion and a non-corrugated portion, where the term "corrugated" means that a middle portion of the top surface is lower than a top surface of an opposing portion grown from the semiconductor fin. The non-wavy portion has a function of preventing the fins of the entire fin group from being bent, while the wavy portion has an increased contact area with respect to the portion formed non-wavy, thus reducing contact resistance. Thus, with a merged epitaxial region including both non-corrugated and corrugated portions, reliability and contact resistance issues are both addressed. The embodiments discussed herein will provide examples to enable or use the subject matter of the present disclosure, and one of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the intended scope of the various embodiments. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Fig. 1, 2A, 2B, 3A, 3B, 3C, 4A, 4B, 4C, 5-7, 8A, 8B, 9, 10, 11A, 11B, and 11C illustrate cross-sectional views of an intermediate stage in the formation of a FinFET and corresponding source/drain regions according to some embodiments of the present invention. The corresponding process is also schematically reflected in the process flow shown in fig. 12.

Fig. 1 shows a perspective view of the initial structure. The initial structure includes a wafer 10, the wafer 10 further including a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The top surface of the substrate 20 may have a (100) surface plane. The substrate 20 may be doped with p-type or n-type impurities. Isolation regions 22, such as Shallow Trench Isolation (STI) regions, may be formed to extend from the top surface of the substrate 20 into the substrate 20. The corresponding process is shown as process 202 in the process flow shown in fig. 12. The portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. According to some embodiments, the top surface of the semiconductor strip 24 and the top surface of the STI region 22 may be substantially flush with each other.

The STI region 22 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). The STI region 22 may also include a dielectric material over the pad oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin coating, or the like. STI regions 22 may include STI regions 22O on the outside of the fin group (as will be discussed in subsequent paragraphs) and STI regions 22I formed at intra-group spacing in the fin group, according to some embodiments. STI region 22O may have a greater height than STI region 22I.

According to some embodiments, the top portions 24T of the semiconductor strips 24 are formed of a material different from that of the bulk portion of the semiconductor substrate 20. For example, the top 24T may be formed of silicon germanium, which may have a germanium atomic percentage in a range between about 15% to about 30%. According to some embodiments, the top portion 24T is formed prior to forming the STI region 22 and is formed by an epitaxial process to deposit silicon germanium on the substrate 20. The top portion 24T may also include a bottom portion formed of the same material as the underlying bulk portion of the semiconductor substrate 20. STI regions 22 are then formed by etching the epitaxial silicon germanium layer and portions of the underlying substrate 20 and depositing dielectric material. According to an alternative embodiment, the top portion 24T is formed after the STI regions 22 are formed, and is formed by etching the portion of the substrate 20 between the STI regions 22, and then performing an epitaxial process to grow a semiconductor material, such as silicon germanium, in the resulting recess.

Referring to fig. 2A and 2B, the STI region 22 is recessed. Fig. 2B shows a cross-sectional view of the reference cross-section B-B in fig. 2A. However, fig. 2A shows the left side portion of the structure shown in fig. 2B. The top of the semiconductor strip 24 protrudes above the top surface 22A of the STI region 22 to form protruding fins 24 ', which protruding fins 24' include protruding fins 24A '(fig. 2B) in the device region 100A and protruding fins 24B' (fig. 2B) in the device region 100B. The corresponding process is shown as process 204 in the process flow shown in fig. 12. The portion of the semiconductor strip 24 located in the STI region 22 is still referred to as a semiconductor strip.

Referring to fig. 2B, the protruding fins 24A 'are collectively referred to as a fin group 25A, and the protruding fins 24B' are collectively referred to as a fin group 25B. According to some embodiments, the internal spacing S1 between adjacent fins in the same fin group 25A and 25B is less than the inter-group spacing S2, e.g., the ratio S2/S1 is greater than about 2, or greater than about 5. The recessing of the STI region 22 may be performed using a dry etch process, in which HF and NH may be implanted₃The mixture of (a) is used as an etching gas. NF may also be used₃And NH₃The mixture of (a) is used as an etching gas to perform etching. During the etching process, plasma may be generated. Argon may also be included. According to an alternative embodiment of the present invention, the recessing of the STI regions 22 is performed using a wet etch process. The etch chemistry may include, for example, an HF solution.

According to some embodiments, the fins used to form the finfets may be formed/patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing for the generation of patterns with, for example, a pitch that is less than that obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fin may then be patterned using the remaining spacers or mandrels.

As shown in fig. 2B, the wafer 10 includes a first device region 100A and a second device region 100B, each for forming a FinFET therein. The finfets formed in the first device region 100A may be p-type finfets, and the finfets formed in the second device region 100B may be n-type finfets or p-type finfets. In order to distinguish the components in the device region 100A and the device region 100B from each other, the components formed in the device region 100A may be denoted by reference numerals followed by the letter "a", and the components formed in the device region 100B may be denoted by reference numerals followed by the letter "B". For example, the semiconductor strips 24 in the device region 100A are referred to as 24A, collectively referred to as a strip group 25A, while the semiconductor strips 24 in the device region 100B are referred to as 24B, collectively referred to as a strip group 25B.

According to some embodiments, the top surface 22A of the STI region 22 may be higher, lower, or flush with the bottom surface of the top portion 24T (fig. 1). Thus, after recessing the STI regions 22, the entire protruding fin 24A' may be formed of silicon germanium and may or may not extend down into the space between the remaining STI regions 22. Alternatively, the bottom of the protruding fin 24A 'may be formed of silicon, and the top of the protruding fin 24A' may be formed of silicon germanium.

Referring to fig. 3A, 3B, and 3C, a dummy gate stack 30 is formed on the top surface and sidewalls of the protruding fins 24A 'and 24B'. The corresponding process is shown as process 206 in the process flow shown in fig. 12. The cross-sections shown in fig. 3B and 3C are taken from reference cross-sections B-B and C-C, respectively, in fig. 3A. In fig. 3C and subsequent fig. 11C, the level of the top surface 22A of the STI region 22 may be shown (see also fig. 3A), and the semiconductor fins 24A 'and 24B' are higher than the top surface 22A. The bottom surface 22B (also refer to fig. 3A) of the STI region 22I is also shown in the cross-sectional view. The STI regions 22I are located at a level between 22A and 22B, and are not shown in fig. 3C and 11C because they are in a different plane from that shown in the figure.

The dummy gate stack 30 may include a dummy gate dielectric 32 (fig. 3C) and a dummy gate electrode 34 over the dummy gate dielectric 32. The dummy gate electrode 34 may be formed using, for example, amorphous silicon or polysilicon, and other materials may also be used. Each dummy gate stack 30 may also include one (or more) hard mask layer(s) 36 located over dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon carbonitride, or the like. The longitudinal direction of the dummy gate stack 30 is also perpendicular to the longitudinal direction of the protruding fins 24A 'and 24B'. According to some embodiments, the dummy gate stack 30 on the protruding fin 24A 'and the dummy gate stack 30 on the protruding fin 24B' are discrete dummy gate stacks that are physically separated from each other. According to an alternative embodiment, the same dummy gate stack 30 may extend over the protruding fins 24A 'and 24B'.

Next, gate spacers 38 are formed on sidewalls of the dummy gate stack 30 (fig. 3A and 3C). The corresponding process is shown as process 208 in the process flow shown in fig. 12. According to some embodiments of the present invention, the gate spacer 38 is formed of a dielectric material such as carbon nitride (SiCN), silicon nitride, silicon oxycarbonitride (SiOCN), or the like, and may have a single layer structure or a multi-layer structure including a plurality of dielectric layers. The formation process includes depositing a conformal spacer layer and then performing an anisotropic etch process to form the gate spacers 38 (and fin spacers 39). According to some embodiments of the present invention, the gate spacer 38 is a multi-layer gate spacer. For example, each gate spacer 38 may include a SiN layer and a SiOCN layer over the SiN layer. Fig. 3A and 3C also show fin spacers 39 formed on the sidewalls of the protruding fins 24'. The corresponding process is shown as process 208 in the process flow shown in fig. 12.

According to some embodiments of the present invention, fin spacers 39 (including 39A, 39B, 39C, 39D, 39E, 39F, 39A ', 39B', 39C 'and 39D' (fig. 3B)) are formed by the same process used to form gate spacers 38, for example, in the process used to form gate spacers 38, when etched, the blanket dielectric layer deposited to form gate spacers 38 may have portions left on the sidewalls of protruding fins 24A 'and 24B', thus forming fin spacers 39. according to some embodiments, fin spacers 39 include outer fin spacers located on the outside of the outermost fins in the set of fins, such as fin spacers 39A, 39F, 39A 'and 39D' (fig. 3B). With the internal fin spacers 39B, 39C, 39D, 39E located between the fins 24A 'and the internal fin spacers 39B' and 39C 'located between the fins 24B'.

Referring to fig. 4A, 4B, and 4C, portions of the protruding fins 24A 'and 24B' not covered by the dummy gate stack 30 and the gate spacers 38 are recessed, thus forming grooves 40A and 40B (fig. 4B). The corresponding process is shown as process 210 in the process flow shown in fig. 12. Fig. 4B and 4C show sectional views taken from reference cross sections B-B and C-C in fig. 4A, respectively. The recess may be anisotropic, so that the portion of the fin 24' directly under the dummy gate stack 30 and the gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor fin 24' may be higher than the top surface 22A of the STI region 22 and may be higher than the remaining fin spacers 39.

According to some embodiments, during the etching of the protruding fins 24', the fin spacers 39 are also etched such that their height is reduced. Fin spacers 39A, 39B, 39C, 39D, 39E, 39F have heights H1, H2, H3, H4, H5, and H6, respectively (fig. 4B). The etching of the fin spacers 39 may be performed while recessing the fins 24 ', wherein an etching gas for etching the fin spacers 39 is added to the etching gas for recessing the protruding fins 24'.

According to some embodiments of the present invention, the recessing of the protruding fins 24' is performed by a dry etching step. May use a signal such as C₂F₆；CF₄；SO₂；HBr、Cl₂And O₂A mixture of (a); HBr, Cl₂、O₂And CF₂The mixture of (2) and the like. The etching may be anisotropic. According to some embodiments of the present invention, as shown in fig. 4C, the sidewalls of the protruding fin 24' facing the recess 40 are substantially vertical and substantially flush with the outer sidewalls of the gate spacer 38. The sidewalls of the protruding fins 24A 'and 24B' facing the recess 40 may be located on the (110) surface plane of the respective protruding fins 24A 'and 24B'. Referring to fig. 4B, the locations of the recesses 40A and 40B, which are also the locations of the removed portions of the protruding fin 24', are shown using dashed lines. The dashed lines also represent protruding fins 24' located directly below the dummy gate stack 30 (fig. 4C) in a different plane than that shown.

In the recess of the protruding fin 24 ', a recess for the protruding fin 24' is also addedThe process gas etching the fin spacers 39 to recess the fin spacers 39. According to some embodiments, the process gas and process conditions used to etch the fin spacers 39 are adjusted (when recessing the protruding fins 24') such that the following relationship is achieved: (H1)>H6)、(H1>(H2&H3)>(H4&H5) And ((H6))>(H2&H3)>(H4&H5) ). Heights H2 and H3 may also be equal to or near heights H4 and H5. In other words, height H1 of left outer fin 39A is greater than height H6 of right outer fin 39F, and heights H1 and H6 of the outer fins are greater than heights H2, H3, H4, and H5 of the inner fins, and heights H2 and H3 of the left inner fins may also be greater than or equal to heights H4 and H5 of the right inner fins. Such as CF may be used₄、O₂And N₂NF of₃And O₂Mixture of (1), SF₆、SF₆And O₂The mixture of (a) and (b), and the like, and the etching of the fin spacers 39 may include a gas, such as argon, for bombarding the outer spacers 39A. The process conditions for obtaining the desired fin spacer height adjustment include, but are not limited to, partial pressures of the etching gas and the bombardment gas, bias voltages, and the like. In addition, a loading effect may be used to help achieve a desired height of the fin spacers. For example, the ratio S2/S1, i.e., the ratio of inter-group spacing S2 to intra-group spacing S1, may be adjusted to adjust the load effect such that the heights H1, H2, H3, H4, H5, and H6 may be adjusted.

According to some embodiments, after etching the protruding fins 24', wherein the fin spacers 39 are also recessed, an additional etching process is performed to further etch the fin spacers 39, and adjust the height of the protruding fins 39. In this process, the protruding fins 24' are not recessed. According to an alternative embodiment, the additional etching process is skipped. The additional etch process, if performed, may also be performed using an anisotropic etch process using, for example, a process gas similar to that used in the formation of the fin spacers. According to some embodiments, previous processes may not be able to achieve the following relationship: (H1> H6), (H1> (H2& H3) > (H4& H5)) and ((H6> (H2& H3) > (H4& H5)). for example, in the formation of the previous fin spacer 39, height H1 may be disadvantageously less than height H6, so an etching process is performed to adjust the height of the fin spacer such that height H1 is greater than H6. optionally, the above relationship may have been achieved by the formation of the previous fin spacer 39, but the ratios between fin spacer heights H1, H2, H3, H4, H5 and H6 are not satisfactory, so an additional etching process may be performed to adjust the ratios to desired values.

In the process discussed above, heights H1 ', H2', H3 ', and H4' of respective fin spacers 39A ', 39B', 39C ', and 39D' may also be adjusted such that height H1 'is greater than H4' and heights H1 'and H4' are both greater than heights H2 'and H3'.

Referring to fig. 5, epitaxial layer 48-1 (also referred to as epitaxial layer L1 and including 48-11, 48-12, and 48-13) is deposited by an epitaxial process. The corresponding process is shown as process 212 in the process flow shown in fig. 12. According to some embodiments, the deposition is performed by a non-conformal deposition process such that the bottom portion (fig. 11C) of the first layer 48-1 is thicker than the sidewall portions. Deposition may be performed using RPCVD, PECVD, or the like. According to some embodiments, epitaxial layer 48-1 is formed of or includes SiGeB. Depending on the desired composition of epitaxial layer 48-1, the process gases used to deposit epitaxial layer 48-1 may include, for example, silane, disilane (Si)₂H₆) Silicon-containing gases such as Dichlorosilane (DCS), germane (GeH)₄) Digermane (Ge)₂H₆) And a germanium-containing gas such as B₂H₆A process gas containing a dopant. In addition, an etching gas such as HCl may be added to achieve selective deposition on the semiconductor rather than on the dielectric. The boron concentration of epitaxial layer 48-1 may be about 5 x 10¹⁹/cm³And about 8X 10²⁰/cm³Within the range of (1). The atomic percent of germanium may be in a range between about 15% and about 45%. The atomic percent of germanium may be graded, with higher portions having a higher atomic percent of germanium than corresponding lower portions.

As shown in fig. 5, epitaxial layers 48-1 laterally expand and grow on top of each other. On the other hand, the epitaxial layers 48-1 grown from the different protruding fins 24A 'and 24B' are still separated from each other and do not merge. The top end of the epitaxial layer 48-1 is controlled to be, for example, a difference in a range between about 5nm and about 10nm below the top surface of the original non-recessed protruding fin 24'. According to some embodiments, the top of epitaxial layer 48-11 is higher than the top of epitaxial layer 48-13 due to the aforementioned relationship between heights H1 through H6. In addition, the top of the epitaxial layer 48-11 may be flush with or higher than the top of the epitaxial layer 48-12.

Referring to fig. 6, epitaxial layer 48-2 (also referred to as epitaxial layer L2) is deposited. The corresponding process is shown as process 214 in the process flow shown in fig. 12. The deposition process may be performed using RPCVD, PECVD, or the like. According to some embodiments, epitaxial layer 48-2 comprises SiGeB, wherein the second boron concentration of boron is higher than the boron concentration in epitaxial layer 48-1. For example, according to some embodiments, the boron concentration in epitaxial layer 48-2 may be about 5 x 10²⁰/cm³And about 3X 10²¹/cm³Within the range of (1). In addition, the atomic percent of germanium in epitaxial layer 48-2 is higher than the atomic percent of germanium in epitaxial layer 48-1. For example, according to some embodiments, the atomic percent of germanium in epitaxial layer 48-2 may be in a range between about 40% and about 65%. The process gases used to form epitaxial layer 48-2 may be similar to the process gases used in the formation of epitaxial layer 48-1, except that the flow of the process gases used to form epitaxial layer 48-2 may be different from the flow of the corresponding process gases used in the formation of epitaxial layer 48-1.

After the epitaxial process to deposit the epitaxial layer 48-2, an etching (etch back) process is performed. According to some embodiments of the invention, the etch-back process is isotropic. According to some embodiments, an etching gas such as HCl and a gas such as H are used₂And/or N₂The etching process is performed with the carrier gas. In addition, a material such as germane (GeH) may be added to the etching gas₄) The germanium-containing gas of (a). A silicon-containing gas such as silane (SiH4) may or may not be added to the etch gas. The addition of the germanium-containing gas (and possibly the silicon-containing gas) produces a deposition effect that occurs simultaneously with the etching effect. However, the etch rate is greater than the deposition rate, so the net effect is an etch back of epitaxial layer 48-2. The addition of the germanium-and silicon-containing gases reduces the net etch rate so that the thickness of epitaxial layer 48-2 is not as thick as when reshaping the surface profile of epitaxial layer 48-2It is significantly reduced. Deposition and etching are optimized so that epitaxial layer 48-2 has a desired thickness. Also, as shown in fig. 6, the top surface of epitaxial layer 48-2 is reshaped such that (111) facets are generated, particularly on the portion of epitaxial layer 48-2 grown from the rightmost protruding fin in fin set 25A and the leftmost protruding fin in fin set 25B.

The top end of the epitaxial layer 48-2 is controlled to be flush with or at least close to (e.g., differing by less than about 5nm or about 3nm) the top end of the original unrecessed protruding fin 24A'. Fig. 11C illustrates a cross-sectional view of reference cross-section C-C in fig. 6, showing that the opposite ends of epitaxial layer 48-2 are flush with the top surface of protruding fin 24A ', while the middle portion of the top surface of epitaxial layer 48-2 may be flush with or slightly below the top surface of the respective protruding fins 24A ' and 24B '.

Referring again to fig. 6, the epitaxial layers 48-2 grown from adjacent trenches merge and the air gap 44 is sealed below the epitaxial layers 48-2. The top surface of the merged epitaxial layer 48-2 may have a non-planar profile (also referred to as having a wavy shape) with intermediate portions located laterally between adjacent fins 24A' being lower than portions on opposite sides of the intermediate portions. The non-recessed portion may be located directly above the protruding fin 24A'. Recesses 46A and 46B are formed due to the differences in fin spacer heights H1, H2, H3, H4, H5, and H6. The groove 46A is located laterally between the two projecting fins 24A 'on the left (and higher than the two projecting fins 24A' on the left), and the groove 46B is located laterally between the two projecting fins 24A 'on the right (and higher than the two projecting fins 24A' on the right). According to some embodiments, the recess depth D1 of the groove 46A is less than the recess depth D2 of the groove 46B, e.g., the ratio D2/D1 is greater than about 1.5, greater than about 2, or in a range between about 1.5 and about 5.

Fig. 7 illustrates an epitaxial process for depositing epitaxial layer 48-3 (also referred to as epitaxial layer L3 or a cap layer). The corresponding process is shown as process 216 in the process flow shown in fig. 12. The deposition process may be performed using RPCVD, PECVD, or the like. According to some embodiments, epitaxial layer 48-3 comprises SiGeB. The boron concentration in epitaxial region 48-3 may be about 5 x 10²⁰/cm³And about 1X 10²¹/cm³Within the range of (1). In addition to this, the present invention is,the atomic percent of germanium in epitaxial layer 48-3 may be greater than, equal to, or less than the atomic percent of germanium in epitaxial layer 48-2. For example, according to some embodiments, the atomic percent of germanium in epitaxial layer 48-3 may be in a range between about 45% and about 55%.

After the epitaxial process to deposit the epitaxial layer 48-3, an etching (etch back) process is performed. According to some embodiments of the invention, the etch-back process is isotropic. According to some embodiments, an etching gas such as HCl and a gas such as H are used₂And/or N₂The etching process is performed with the carrier gas. In addition, a material such as germane (GeH) may be added to the etching gas₄) The germanium-containing gas of (a). Such as Silane (SiH) may or may not be added to the etching gas₄) The silicon-containing gas of (1). The addition of the germanium-containing gas results in a deposition effect that occurs simultaneously with the etching effect. However, the etch rate is greater than the deposition rate, so that the net effect is an etch back of epitaxial layer 48-3. The addition of the germanium-containing gas reduces the net etch rate so that the thickness of epitaxial layer 48-3 is not significantly reduced when the surface profile of epitaxial layer 48-3 is reshaped. Deposition and etching are optimized so that epitaxial layer 48-3 has a desired thickness. Also, as shown in fig. 7, the top and sidewall surfaces of epitaxial layer 48-3 are reshaped to have more (111) facets created, particularly the portion of epitaxial layer 48-3 that is grown from the rightmost protruding fin in fin set 25A and the leftmost protruding fin in fin set 25B. Furthermore, as more and better (111) facets are formed, sharper corners are formed. Throughout the specification, epitaxial layers 48-1, 48-2 and 48-3 are collectively and individually referred to as epitaxial layer (region) 48, and hereinafter collectively referred to as source/drain regions 48A and 48B.

According to some embodiments, the epitaxial region 48A has a convex portion that is higher than the top surface 24 'TS of the protruding fin 24A'. The convex height RH1 directly above the leftmost protruding fin 24A 'is greater than the convex height RH3 directly above the rightmost protruding fin 24A', and may be equal to or slightly greater (e.g., by less than about 2nm) than the convex height RH 2.

Epitaxial layer 48-3 has a top surface 48-3TS, and top surface 48-3TS is also the top surface of source/drain region 48. According to some embodiments, the portion 45A of the source/drain region 48 formed based on the left two protruding fins 24A' has a conical shape, and the top surface of the portion 45A is generally flat and may have a convex top surface. For example, the top surface of the epitaxial layer 48-3 may be flat from the right edge (from the left) of the first protruding fin to the right edge (from the left) of the second protruding fin 24'. Alternatively, the portion of the top surface may be rounded (as shown by dashed line 47) and have a convex shape with a highest point between (and may be intermediate) the first and second protruding fins. In other words, the convexity height RH4 is greater than the convexity heights RH1, RH2, and RH 3. On the other hand, the top surface of the right portion of the source/drain region 48 formed based on the right two protruding fins 24A' is wavy (concave), and the right protruding portion includes the right portions of the portion 45B and the portion 45A. Forming distinct grooves 46C. According to some embodiments, the depth D3 of the groove 46C is greater than about 3nm, and may be in a range between about 3nm and about 15 nm. Thus, in general, the left side of the top surface of source/drain region 48 is flatter and higher than the right side, where the left side is the side further from the adjacent set of fins 25B and the right side is the side closer to the set of fins 25B.

Epitaxial region 48B may include layers 48-1, 48-2, and 48-3. According to some embodiments, epitaxial region 48B is p-type and may be formed in the same process used to form epitaxial region 48A. According to an alternative embodiment, epi region 48B is n-type and belongs to an n-type FinFET, and is thus formed in a different process than the formation of epi region 48A. For example, when the epitaxial region 48B is p-type, the epitaxial region 48B may have a conical shape (the top surface is convex). Alternatively, the epitaxial region 48B may have a corrugated top surface, as indicated by the dashed line 50, which may occur when the epitaxial region 48B is n-type. According to some embodiments, the top surface of epitaxial region 48B may be flat or may be slightly sloped, with portions closer to group of fins 25A being lower than portions further from group of fins 25A.

Referring to fig. 8A and 8B, a Contact Etch Stop Layer (CESL)66 and an interlayer dielectric (ILD)68 are formed over the epitaxial regions 48A and 48B. The corresponding process is shown as process 218 in the process flow shown in fig. 12. A planarization, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the CESL 66 and the ILD 68 until the dummy gate stack 30 is exposed (fig. 4A and 4C).

Then, the dummy gate stack 30 is removed in an etching process (fig. 4A and 4C) and replaced with a replacement gate stack 56, as shown in fig. 8A. The corresponding processes are shown as processes 220 and 222 in the process flow shown in fig. 12. The replacement gate stack 56 includes a gate dielectric 58, the gate dielectric 58 further including an interfacial layer on the top surface and sidewalls of the protruding fin 24' and a high-k dielectric over the interfacial layer. The replacement gate stack 56 also includes a gate electrode 60 over the gate dielectric 58. After forming the replacement gate stack 56, the replacement gate stack 56 is recessed to form trenches between the gate spacers 38. A dielectric material such as silicon nitride, silicon oxynitride, or the like is filled into the resulting trench to form a dielectric hard mask 62. The corresponding process is shown as process 224 in the process flow shown in fig. 12.

Next, referring to fig. 9, the ILD 68 and CESL 66 are etched to form source/drain contact openings 70. The corresponding process is shown as process 226 in the process flow shown in fig. 12. An etch is also made through epitaxial layer 48-3 and the top surface of epitaxial layer 48-2 is exposed. The openings 70 may extend into the epitaxial regions 48A and 48B to a depth in a range between about 5nm and about 10 nm. The etch may be controlled to stop on epitaxial layer 48-2 while a small overetch (e.g., less than about 2nm) is performed on epitaxial layer 48-2. The exposed top surface of epitaxial layer 48-2 is corrugated and recesses 46A and 46B may be exposed such that the exposed top surface of epitaxial layer 48-2 includes a portion having a V-shape in cross-sectional view. It will be appreciated that although the left portion of the epitaxial region is no longer non-corrugated, but also has a corrugated top surface, the entire structure, including CESL 66 and ILD 68, will prevent bowing of the protruding fins at this stage of the fabrication process.

Since the flat portion of epitaxial layer 48-2 has a slower etch rate than the portion having the corners, the right side portion 48-2R having more corners than the left side portion is etched more than the portion 48-2L having a flatter surface. Thus, the top of portion 48-2R is lower than the top of portion 48-2L, e.g., their top surfaces have a height difference Δ H1 of greater than about 3nm, and may range between about 2nm and about 10 nm. In general, the side of the epitaxial region 48A facing the epitaxial region 48B is lower than the side facing away from the epitaxial region 48B. The exposed top surface of epitaxial layer 48-2 has recesses (concavities) 46A 'and 46B'.

Next, as shown in fig. 10, source/drain silicide regions 72A and 72B are formed. The corresponding process is shown as process 228 in the process flow shown in fig. 12. According to some embodiments of the present invention, the formation of the source/drain silicide regions 72A and 72B includes depositing a metal layer, such as a titanium layer, a cobalt layer, or the like, that extends into the opening 70, and then performing an annealing process such that the bottom of the metal layer reacts with the epitaxial layer 48-2 to form the silicide regions 72A and 72B. The remaining unreacted metal layer may be removed.

Fig. 11A, 11B, and 11C illustrate the formation of one or more contact plugs 74. The corresponding process is shown as process 230 in the process flow shown in fig. 12. As shown in fig. 11B, source/drain contact plugs 74 are formed to fill the openings 70 and electrically interconnect the source/drain silicide regions 72A and 72B. Finfets 76A and 76B (fig. 11B) are thereby formed, and the source/drain regions 48A and 48B are electrically interconnected by the contact plugs 74. Fig. 11B shows reference cross section BB in fig. 11A, and fig. 11C shows reference cross section C-C in fig. 11A. As shown in fig. 11B, the top surface of epitaxial region 48A is asymmetric and sloped, with the inner portion closer to epitaxial region 48B being lower than the outer portion further from epitaxial region 48B. The silicide regions 72A and 72B are correspondingly sloped. According to some embodiments, the top surface of the interior of the silicide region 72A is lower than the corresponding exterior by a height difference Δ H2, which height difference Δ H2 may be greater than about 2nm, and may be in a range between about 2nm and about 10 nm. Silicide regions 72A may have recesses (concavities) 46A 'and 46B'. In addition, the silicide regions 72A and 72B extend on the sidewalls of the epitaxial regions 48A and 48B such that the contact area between the silicide regions 72A and 72B and the respective epitaxial regions 48A and 48B is increased and the contact resistance is reduced.

Embodiments of the present invention have some advantageous features. By forming the first portion of the epitaxial region to be non-corrugated (having a conical shape), the curvature of all of the semiconductor fins in the fin group based on which the epitaxial region is formed may be reduced since the non-corrugated portion serves as an anchor to prevent the remaining semiconductor fins from bending. By forming the second portion of the epitaxial region to have a corrugated top surface, the contact area is reduced. In addition, more epitaxial regions have sharper corners due to the wavy shape, wherein the corners are etched when forming the source/drain silicide regions and the contact plugs, so that the corresponding silicide regions extend on the sidewalls of the epitaxial regions, and the contact resistance is further reduced.

According to some embodiments of the present invention, a method includes recessing isolation regions on opposing sides of a first semiconductor strip, a second semiconductor strip, and a third semiconductor strip to form a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin; forming a gate stack on the first, second, and third semiconductor fins; forming gate spacers on sidewalls of the gate stack; forming fin spacers on sidewalls of the first, second, and third semiconductor strips; performing a recess process to recess the first, second and third semiconductor strips to form first, second and third grooves, respectively; and performing an epitaxial process to form an epitaxial region starting from the first, second, and third grooves, wherein the epitaxial region includes a top surface including: a convex portion higher than and laterally between the first and second semiconductor fins; and a concave portion higher than and laterally between the second and third semiconductor fins. In an embodiment, the fin spacer further comprises: a first outer fin spacer having a first height; a second outer fin spacer having a second height less than the first height; and an interior spacer located between the first exterior fin spacer and the second exterior fin spacer, wherein a height of the interior spacer is less than the first height and the second height. In an embodiment, the fin spacers are simultaneously etched during the recess process, and the method further comprises, after the recess process, also recessing the fin spacers. In an embodiment, the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin form a first fin group, wherein the first fin group is adjacent to the second fin group, and the second outer fin spacer faces toward the second fin group, and the first outer fin spacer faces away from the second fin group. In an embodiment, after recessing the first, second, and third semiconductor fins, top surfaces of the first, second, and third semiconductor fins are higher than top ends of the fin spacers. In an embodiment, the epitaxial region includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the third epitaxial layer includes a first portion having a convex portion of a top surface and a second portion having a concave portion of the top surface, and wherein the method further comprises etching through the first portion of the third epitaxial layer to expose the concave top surface of the second epitaxial layer. In an embodiment, the method further includes forming a silicide region on the second epitaxial layer, wherein the silicide region includes a first portion directly on the recessed top surface of the second epitaxial layer; and a second portion directly over the third semiconductor fin, wherein the first portion of the silicide region is higher than the second portion of the silicide region. In an embodiment, the third epitaxial layer includes a lower boron concentration than the second epitaxial layer. In an embodiment, the epitaxial process includes depositing silicon germanium boron.

According to some embodiments of the invention, a method includes forming a first fin group and a second fin group, wherein the first fin group includes a plurality of semiconductor fins having an intra-group spacing, wherein the inter-group spacing of the first fin group and the second fin group is greater than the intra-group spacing, and wherein the plurality of semiconductor fins includes a first semiconductor fin, wherein the first semiconductor fin is furthest away from the second fin group in the first fin group; a second semiconductor fin; and a third semiconductor fin, wherein the third semiconductor fin is closest to the second fin group in the first fin group; and performing an epitaxy process to form an epitaxy region based on the plurality of semiconductor fins, wherein the epitaxy region includes a first portion located in the middle between the first semiconductor fin and the second semiconductor fin, wherein the first portion has a first top surface; and a second portion located intermediate between the second semiconductor fin and the third semiconductor fin, wherein the second portion has a second top surface lower than the first top surface. In an embodiment, the first portion includes a first highest point located laterally between the first and second semiconductor fins, and the epitaxial region further includes a third portion located directly above the third semiconductor fin, wherein the third portion has a second highest point, and the first highest point is higher than the second highest point. In an embodiment, the top surface of the epitaxial region has a recess laterally between the second semiconductor fin and the third semiconductor fin. In an embodiment, the depth of the recess is in a range between about 3nm to about 15 nm. In an embodiment, a portion of the epitaxial region between the first semiconductor fin and the second semiconductor fin has a convex top surface. In an embodiment, the method further comprises forming a silicide region, wherein forming the silicide region comprises: removing a portion of the epitaxial region having a convex top surface to form a concave top surface of the epitaxial region; and forming a silicide region on the recessed top surface of the epitaxial region.

According to some embodiments of the invention, a method includes forming a first fin group and a second fin group, wherein the first fin group includes a plurality of semiconductor fins having an intra-group spacing, and the first fin group includes a first semiconductor fin furthest from the second fin group, a second semiconductor fin, and a third semiconductor fin closest to the second fin group; forming a gate stack on the first fin group; forming gate spacers on sidewalls of the gate stack; forming a fin spacer comprising a first outer fin spacer facing the second set of fins, wherein the first outer fin spacer has a first height; a second outer fin spacer facing away from the second set of fins, wherein the second outer fin spacer has a second height greater than the first height; and an interior spacer located between the first exterior fin spacer and the second exterior fin spacer; performing an epitaxy process to form a first epitaxy region based on the first fin group and a second epitaxy region based on the second fin group; and forming source/drain contact plugs electrically interconnecting the first epitaxial region and the second epitaxial region. In an embodiment, the fin spacers are formed as interior spacers having a height less than the first height and the second height. In an embodiment, the inter-group spacing of the first set of fins and the second set of fins is greater than the intra-group spacing. In an embodiment, the source/drain contact plug has a bottom portion having a portion overlapping the first epitaxial region, wherein the bottom portion is sloped, and a portion of the bottom portion near the second fin group is lower than a portion of the bottom portion farther from the second fin group. In an embodiment, the first epitaxial region includes a top surface, and the top surface includes: a first portion laterally between and above the first and second semiconductor fins, wherein the first portion has a convex top surface; and a second portion laterally between the second semiconductor fin and the third semiconductor fin, wherein the second portion has a concave top surface.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent arrangements do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.