阅读说明：本技术 一种rc振荡电路 (RC oscillating circuit ) 是由 任小娇 郭嘉帅 于 2021-11-05 设计创作，主要内容包括：本发明提供了一种RC振荡电路,包括：第一组反相器、第二组反相器、锁存器、延时电路、以及第三组反相器；第一组反相器连接至延时电路,其用于产生两个电位相反的第一信号A和第二信号B；第二组反相器的输入端接使能信号EN,其输出端连接至锁存器；延时电路的输出端与锁存器的连接,用于对第一信号A和第二信号B进行延时；锁存器与第三组反相器连接,其包括第一输出端和第二输出端,其接收第一延时信号DA和第二延时信号DB、并接收自身产生的第一时钟信号FB和第二时钟信号FA；第一时钟信号FB经所述第三组反相器进行驱动后由其输出端输出输出信号CLK。本发明可避免电路进入死态后不可恢复的情形,且电路成本较低。(The invention provides an RC oscillation circuit, comprising: a first set of inverters, a second set of inverters, a latch, a delay circuit, and a third set of inverters; the first group of inverters are connected to the delay circuit and are used for generating a first signal A and a second signal B with opposite potentials; the input end of the second group of inverters is connected with an enable signal EN, and the output end of the second group of inverters is connected to the latch; the output end of the delay circuit is connected with the latch and is used for delaying the first signal A and the second signal B; the latch is connected with the third group of inverters, comprises a first output end and a second output end, receives the first delay signal DA and the second delay signal DB, and receives the first clock signal FB and the second clock signal FA generated by the latch; the first clock signal FB is driven by the third group of inverters and then outputs an output signal CLK by an output end of the first clock signal FB. The invention can avoid the situation that the circuit can not be recovered after entering the dead state, and the circuit cost is lower.)

1. An RC oscillating circuit, comprising: a first set of inverters, a second set of inverters, a latch, a delay circuit, and a third set of inverters;

the first group of inverters are connected to the delay circuit, are used for generating a first signal A and a second signal B with opposite potentials, and are input to the delay circuit;

the input end of the second group of inverters is connected with an enable signal EN, and the output end of the second group of inverters is connected to the latch, and is used for generating an inverted signal ENB opposite to the enable signal EN and inputting the inverted signal ENB to the latch;

the output end of the delay circuit is connected with the latch and is used for delaying the first signal A and the second signal B and outputting a first delay signal DA and a second delay signal DB to the latch;

the latch is connected with the third group of inverters and comprises a first output end and a second output end, the first output end and the second output end receive the first delay signal DA and the second delay signal DB and receive a first clock signal FB and a second clock signal FA generated by the latch, the first output end is connected with the third group of inverters, the first clock signal FB is input into the third group of inverters, the first output end is also connected with the input end of the first group of inverters, and the first clock signal FB is used as the input end of the first group of inverters;

and the first clock signal FB is driven by the third group of inverters and then outputs an output signal CLK from an output end of the first clock signal FB.

2. The RC oscillation circuit of claim 1, wherein the first set of inverters comprises two inverters connected in series, and the first signal a and the second signal B having an opposite potential are respectively outputted through output terminals of the two inverters.

3. The RC oscillation circuit of claim 2, wherein the delay circuit comprises a first delay circuit and a second delay circuit, the first delay circuit and the second delay circuit being connected to the output terminals of the two inverters, respectively.

4. The RC oscillator circuit of claim 3, wherein the latch comprises a three-input nor gate and a two-input nor gate, the output of the first delay circuit being connected to the DA input of the three-input nor gate, the outputs of the second set of inverters being connected to the ENB input of the three-input nor gate, the outputs of the two-input nor gate being connected to the FA input of the three-input nor gate;

and the FB input end of the two-input NOR gate is connected with the output end of the three-input NOR gate, and the DB input end of the two-input NOR gate is connected with the output end of the second delay circuit.

5. The RC oscillation circuit of claim 1 wherein the second set of inverters comprises a single number of inverters.

6. The RC oscillation circuit of claim 1 wherein the number of inverters of the third set of inverters is determined by the load connected.

7. The RC oscillation circuit of claim 1, wherein the number of inverters of the third group of inverters is determined according to a phase of the output signal CLK.

8. An RC oscillating circuit, comprising: a first set of inverters, a latch, a delay circuit, and a third set of inverters;

the first group of inverters are connected to the delay circuit, are used for generating a first signal A and a second signal B with opposite potentials, and are input to the delay circuit;

the output end of the delay circuit is connected with the latch and is used for delaying the first signal A and the second signal B and outputting a first delay signal DA and a second delay signal DB to the latch;

one input end of the latch is further connected to an enable signal EN port, an output end of the latch is connected with the third group of inverters, the latch comprises a first output end and a second output end, the first output end and the second output end receive the first delay signal DA and the second delay signal DB and receive a first clock signal FB and a second clock signal FA generated by the latch, the first output end is connected with the third group of inverters, the first clock signal FB is input to the third group of inverters, the first output end is further connected with input ends of the first group of inverters, and the first clock signal FB is used as input of the first group of inverters;

and the first clock signal FB is driven by the third group of inverters and then outputs an output signal CLK from an output end of the first clock signal FB.

9. The RC oscillation circuit of claim 8, wherein the first group of inverters comprises two inverters connected in series, and the first signal a and the second signal B having opposite potentials are outputted through output terminals of the two inverters, respectively, and the delay circuit comprises a first delay circuit and a second delay circuit, and the first delay circuit and the second delay circuit are connected to output terminals of the two inverters, respectively.

10. The RC oscillation circuit of claim 9, wherein the latch comprises a three-input nor gate and a two-input nor gate, the output terminal of the first delay circuit is connected to the DA input terminal of the three-input nor gate, the output terminals of the second group of inverters are connected to the EN input terminal of the three-input nor gate, and the output terminal of the two-input nor gate is connected to the FA input terminal of the three-input nor gate;

and the FB input end of the two-input NOR gate is connected with the output end of the three-input NOR gate, and the DB input end of the two-input NOR gate is connected with the output end of the second delay circuit.

Technical Field

The invention relates to the technical field of electronics, in particular to an RC oscillating circuit.

Background

At present, the basic principle of the RC oscillator is to charge and discharge a capacitor periodically through a resistor. When the voltage on the capacitor reaches a certain level, the charging switch is controlled to be switched off through feedback, and the discharging switch is switched on. If only one capacitor is charged and discharged, it is generally controlled by a hysteresis comparator. If two groups of capacitors are charged and discharged, two comparators are adopted for feedback control. However, basically, the comparator is required to determine the level and control the charge/discharge switch.

In addition, the mode of judging the level by adopting the comparator has the problem of outputting a dead state, for example, when an output node of the comparator reaches an intermediate level due to external force, the whole loop may stop vibrating and enter a steady state, and when the external force is removed, the circuit cannot automatically recover starting vibration. Therefore, a dead-state recovery circuit is required to be added for different circuits. Increase circuit area and power consumption costs, and increase design difficulty.

Disclosure of Invention

It is an object of the present invention to overcome at least one of the above technical problems and to provide an RC oscillation circuit.

In order to achieve the above object, in one aspect, the present invention provides an RC oscillation circuit comprising: a first set of inverters, a second set of inverters, a latch, a delay circuit, and a third set of inverters;

the first group of inverters are connected to the delay circuit, are used for generating a first signal A and a second signal B with opposite potentials, and are input to the delay circuit;

the input end of the second group of inverters is connected with an enable signal EN, and the output end of the second group of inverters is connected to the latch, and is used for generating an inverted signal ENB opposite to the enable signal EN and inputting the inverted signal ENB to the latch;

the output end of the delay circuit is connected with the latch and is used for delaying the first signal A and the second signal B and outputting a first delay signal DA and a second delay signal DB to the latch;

the latch is connected with the third group of inverters, and comprises a first output end and a second output end, the first output end and the second output end receive the first delay signal DA and the second delay signal DB and receive a first clock signal FB and a second clock signal FA generated by the latch, the first output end is connected with the third group of inverters, the first clock signal FB is input to the third group of inverters, the first output end is also connected with the input end of the first group of inverters, and the first clock signal FB is used as the input end of the first group of inverters;

and the first clock signal FB is driven by the third group of inverters and then outputs an output signal CLK from an output end of the first clock signal FB.

Preferably, the first group of inverters comprises two inverters connected in series, and the first signal a and the second signal B with opposite potentials are output through output ends of the two inverters respectively.

Preferably, the delay circuit includes a first delay circuit and a second delay circuit, and the first delay circuit and the second delay circuit are respectively connected to the output ends of the two inverters.

Preferably, the latch comprises a three-input nor gate and a two-input nor gate, the output end of the first delay circuit is connected with the DA input end of the three-input nor gate, the output ends of the second group of inverters are connected with the ENB input end of the three-input nor gate, and the output end of the two-input nor gate is connected with the FA input end of the three-input nor gate;

and the FB input end of the two-input NOR gate is connected with the output end of the three-input NOR gate, and the DB input end of the two-input NOR gate is connected with the output end of the second delay circuit.

Preferably, the second set of inverters comprises a single number of inverters.

Preferably, the number of inverters of the third group of inverters is determined according to a load connected.

Preferably, the number of inverters of the third group of inverters is determined according to the phase of the output signal CLK.

In a second aspect, the present invention further provides an RC oscillation circuit, including: a first set of inverters, a latch, a delay circuit, and a third set of inverters;

the first group of inverters are connected to the delay circuit, are used for generating a first signal A and a second signal B with opposite potentials, and are input to the delay circuit;

the output end of the delay circuit is connected with the latch and is used for delaying the first signal A and the second signal B and outputting a first delay signal DA and a second delay signal DB to the latch;

one input end of the latch is further connected to an enable signal EN port, an output end of the latch is connected with the third group of inverters, the latch comprises a first output end and a second output end, the first output end and the second output end receive the first delay signal DA and the second delay signal DB and receive a first clock signal FB and a second clock signal FA generated by the latch, the first output end is connected with the third group of inverters, the first clock signal FB is input to the third group of inverters, the first output end is further connected with input ends of the first group of inverters, and the first clock signal FB is used as input of the first group of inverters;

and the first clock signal FB is driven by the third group of inverters and then outputs an output signal CLK from an output end of the first clock signal FB.

Preferably, the first group of inverters comprise two inverters connected in series, the first signal a and the second signal B with opposite potential are output through output ends of the two inverters respectively, the delay circuit comprises a first delay circuit and a second delay circuit, and the first delay circuit and the second delay circuit are connected to output ends of the two inverters respectively.

Preferably, the latch comprises a three-input nor gate and a two-input nor gate, the output end of the first delay circuit is connected with the DA input end of the three-input nor gate, the output ends of the second group of inverters are connected with the EN input end of the three-input nor gate, and the output end of the two-input nor gate is connected with the FA input end of the three-input nor gate;

and the FB input end of the two-input NOR gate is connected with the output end of the three-input NOR gate, and the DB input end of the two-input NOR gate is connected with the output end of the second delay circuit.

Compared with the prior art, in the embodiment of the invention, any node in the RC oscillator is pulled to an abnormal level by an abnormal external force, for example, the node is forced to be a high level or a low level, and when the external force disappears, the RC oscillator circuit can automatically recover oscillation without additionally adding any dead-state recovery circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic diagram of an RC oscillator circuit according to an embodiment of the present invention;

FIG. 2 is a timing diagram of an RC oscillating circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an RC oscillating circuit according to another embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

Referring to fig. 1, an embodiment of the invention provides an RC oscillating circuit, including: a first set of inverters 10, a second set of inverters 20, a latch 40, a delay circuit 30, and a third set of inverters 50.

The first group of inverters 10 is connected to the delay circuit 30, and is used for generating two first signals a and second signals B with opposite potentials, and inputting the two first signals a and the second signals B into the delay circuit 30; the input end of the second group of inverters 20 is connected with an enable signal EN, the output end thereof is connected to the latch 40, and the inverted signal ENB opposite to the enable signal EN is generated and input to the latch 40, the control circuit is enabled, and the enable is active at high level; the output end of the delay circuit 30 is connected to the latch 40, and is configured to delay the first signal a and the second signal B, and output a first delay signal DA and a second delay signal DB to the latch 40; the latch 40 is connected to the third inverter 50, and includes a first output end and a second output end, and receives the first delay signal DA and the second delay signal DB, and receives the first clock signal FB and the second clock signal FA generated by itself, the first output end is connected to the third inverter 50, and inputs the first clock signal FB to the third inverter 50, the first output end is further connected to the input end 10 of the first inverter, and the first clock signal FB is used as the input of the first inverter 10, i.e. as the feedback input of the RC oscillation circuit; the first clock signal FB is driven by the third set of inverters 50 and outputs an output signal CLK at its output terminal.

In this embodiment, the first set of inverters 10 includes two inverters connected in series, and the first signal a and the second signal B with opposite potentials are output through output terminals of the two inverters, respectively.

In this embodiment, the delay length of the delay circuit 30 can be freely adjusted according to the duty ratio required by the output clock, the delay circuit 30 includes a first delay circuit 31 and a second delay circuit 32, the first delay circuit 31 and the second delay circuit 32 are respectively connected to the output ends of the two inverters, receive the input first signal a and second signal B, respectively perform delay processing on the first signal a and second signal B, the first delay circuit 31 outputs the first delay signal DA after performing delay processing on the first signal a, and the second delay circuit 32 outputs the second delay signal DB after performing delay processing on the second signal B.

In this embodiment, the latch 40 includes a three-input nor gate and a two-input nor gate, the output terminal of the first delay circuit 31 is connected to the DA input terminal of the three-input nor gate for inputting the first delay signal DA, the output terminals of the second group of inverters 20 are connected to the ENB input terminal of the three-input nor gate for inputting the inverted signal ENB, the output terminal of the two-input nor gate is connected to the FA input terminal of the three-input nor gate, and the second clock signal FA output by the input nor gate is input to the FA input terminal of the three-input nor gate.

The FB input terminal of the two-input nor gate is connected to the output terminal of the three-input nor gate for receiving the first clock signal FB output by the three-input nor gate, and the DB input terminal of the two-input nor gate is connected to the output terminal of the second delay circuit 32 for receiving the second delay signal output by the second delay circuit 32.

The latch 40 switches the output of the first clock signal FB according to the high levels of the DA input terminal and the DB input terminal, and latches and holds the first clock signal FB with the enable signal ENB active low until the next high level arrives.

As shown in fig. 2, the falling edge generated by the first clock signal FB is controlled by the rising edge of the first delay signal DA; the rising edge of the first clock signal FB is triggered by the falling edge generated after the second clock signal FA and the first delay signal DA, and the sequence of the falling edge of the second clock signal FA and the falling edge of the first delay signal DA is determined by the magnitude of the delay time tdA and tdB of the delay circuit; the falling edge generated by the second clock signal FA is controlled by the rising edge of the second delay signal DB; the rising edge of the second clock signal FA is triggered by the falling edge generated after the first clock signal FB and the second delay signal DB, and the sequence of the falling edge of the first clock signal FB and the falling edge of the second delay signal DB is determined by the magnitude of the delay times tdA and tdB of the delay circuits;

in this embodiment, the duty cycle of the output signal CLK is the delay time tdA of the first delay circuit, and the period of the output signal CLK is the sum of the delay times of the first delay circuit and the second delay circuit, that is, tdA + tdB.

In the present embodiment, the second inverter 20 includes a plurality of inverters, and particularly, includes an inverter for generating an inverted signal ENB opposite to the enable signal EN.

In one possible embodiment, the number of inverters of the third set of inverters 50 may be determined according to the connected load.

In another possible implementation, the number of inverters of the third group of inverters may be determined according to the phase of the output signal CLK.

Any node EN, ENB, A, B, DA, DB, FA, FB in the RC oscillator is pulled to an abnormal level by abnormal external force, for example, the node is forced to be a high level or a low level, when the external force disappears, the RC oscillator circuit can automatically recover oscillation, and no dead-state recovery circuit is required to be additionally added. For example, assuming that the first clock signal FB is at a low level, the second signal B is at a high level, the first signal a is at a low level, and the two signals should be delayed to turn the first clock signal FB to a high level. At this time, the first signal a is pulled to a high level by the strong source, the first delay signal DA is pulled to the high level after passing through the delay circuit, the first clock signal FB is kept at a low level unchanged, and the circuit stops oscillating. When the external strong source disappears, the first clock signal FB is at a low level, so that the first signal A is pulled to the low level again, the circuit recovers to a normal working state, and the oscillation starts again. Other nodes may also be analyzed by the same method.

Example two

Fig. 3 shows an RC oscillating circuit provided in this embodiment, which is different from the first embodiment in that in this embodiment, the enable signal EN is active low, and at this time, the enable signal EN is directly connected to the ENB port of the latch, and a second group of inverters does not need to be provided.

While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.