阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 八窪裕人 斋藤圣矢 大贯达也 于 2020-05-12 设计创作，主要内容包括：提供一种新颖的半导体装置。本发明的一个方式是一种半导体装置,包括具有将硅衬底用于沟道的第一晶体管的第一控制电路、设置在第一控制电路上且具有将金属氧化物用于沟道的第二晶体管的第二控制电路、设置在第二控制电路上且具有将金属氧化物用于沟道的第三晶体管的存储电路、以及具有传送第一控制电路与第二控制电路间的信号的功能的全局位线及反转全局位线。第一控制电路包括具有输入端子及反转输入端子的读出放大器电路。在从存储电路向第一控制电路读出数据的第一期间,第二控制电路控制是否根据从存储电路读出的数据对电荷被释放的全局位线及反转全局位线进行充电。(A novel semiconductor device is provided. One embodiment of the present invention is a semiconductor device including a first control circuit including a first transistor using a silicon substrate for a channel, a second control circuit provided over the first control circuit and including a second transistor using a metal oxide for the channel, a memory circuit provided over the second control circuit and including a third transistor using a metal oxide for the channel, and a global bit line and an inverted global bit line having a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit having an input terminal and an inverting input terminal. In a first period in which data is read from the memory circuit to the first control circuit, the second control circuit controls whether or not the global bit line and the inverted global bit line, from which electric charges are discharged, are charged in accordance with the data read from the memory circuit.)

1. A semiconductor device, comprising:

a first control circuit having a first transistor using a silicon substrate for a channel;

a second control circuit on the first control circuit and having a second transistor using a metal oxide for a channel;

a memory circuit on the second control circuit and having a third transistor using a metal oxide for a channel; and

a global bit line and an inverted global bit line having a function of transferring a signal between the first control circuit and the second control circuit,

wherein the first control circuit includes a sense amplifier circuit having an input terminal and an inverting input terminal,

in a first period in which data is read from the memory circuit to the first control circuit, the second control circuit controls whether or not the global bit line and the inverted global bit line, from which electric charges are discharged, are charged in accordance with the data read from the memory circuit.

2. A semiconductor device, comprising:

a first control circuit having a first transistor using a silicon substrate for a channel;

a second control circuit on the first control circuit and having a second transistor using a metal oxide for a channel;

a memory circuit on the second control circuit and having a third transistor using a metal oxide for a channel;

a global bit line and an inverted global bit line having a function of transmitting a signal between the first control circuit and the second control circuit; and

a plurality of switches disposed between the global bit line and the second control circuit and between the inverted global bit line and the second control circuit,

wherein the first control circuit includes a sense amplifier having an input terminal and an inverting input terminal,

the second control circuit has a control circuit that controls whether or not to discharge the electric charges precharged to the one bit line and the inverted global bit line in accordance with the data read out from the memory circuit during a first period in which the data is read out from the memory circuit to the first control circuit,

switching the changeover switch in such a manner that the global bit line and the input terminal and the inverted global bit line and the inverted input terminal are each in a conductive state during the first period,

in a second period in which the data read from the memory circuit is refreshed, the global bit line and the inversion input terminal, and the inversion global bit line and the input terminal are switched so as to be in a conductive state, respectively.

3. A semiconductor device, comprising:

a first control circuit having a first transistor using a silicon substrate for a channel;

a second control circuit on the first control circuit and having a second transistor using a metal oxide for a channel,

a memory circuit on the second control circuit and having a third transistor using a metal oxide for a channel; and

a global bit line and an inverted global bit line having a function of transferring a signal between the first control circuit and the second control circuit,

wherein the first control circuit has a sense amplifier including an amplifying circuit, an output terminal, an inverting output terminal, a first switch, a second switch, and a signal inverting circuit,

the first switch is disposed between the global bit line and the output terminal,

the second switch is disposed between the inverted global bit line and the inverted output terminal,

the signal inverting circuit has a function of supplying a potential that inverts logic data corresponding to the potentials of the global bit line and the inverted global bit line to the output terminal and the inverted output terminal that are electrically connected to the amplifying circuit,

the second control circuit has a function of controlling whether or not to discharge electric charges precharged to the global bit lines and the inversion global bit lines in accordance with data read out from the memory circuit during a first period in which data is read out from the memory circuit to the first control circuit,

in the first period, the first switch and the second switch are turned off, and a potential for inverting logic data corresponding to potentials of the global bit line and the inverted global bit line is supplied to the output terminal and the inverted output terminal which are electrically connected to the amplifier circuit,

in a second period of refreshing the data read from the memory circuit, the first switch and the second switch are turned on, and the potentials of the output terminal and the inverted output terminal amplified by the amplifier circuit are supplied to the global bit line and the inverted global bit line.

4. The semiconductor device according to any one of claims 1 to 3,

wherein the global bit lines and the inverted global bit lines are disposed in a direction perpendicular or substantially perpendicular to the silicon substrate surface.

5. The semiconductor device according to any one of claims 1 to 4,

wherein the metal oxide comprises In, Ga and Zn.

6. The semiconductor device according to any one of claims 1 to 5,

wherein the second control circuit includes fourth to seventh transistors,

a gate of the fourth transistor is electrically connected to a local bit line having a function of transferring a signal between the second control circuit and the memory circuit,

the fifth transistor has a function of controlling an on state between a gate of the fourth transistor and one of a source and a drain of the fourth transistor,

the sixth transistor has a function of controlling a conductive state between the other of the source and the drain of the fourth transistor and a wiring to which a potential for flowing a current through the fourth transistor is supplied,

and the seventh transistor has a function of controlling a conduction state between one of a source and a drain of the fourth transistor and the global bit line.

Technical Field

This specification describes a semiconductor device and the like.

In this specification, a semiconductor device refers to a device utilizing semiconductor characteristics, and refers to a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like), a device including the circuit, or the like. The semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Examples of the semiconductor device include an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package. In addition, the memory device, the display device, the light-emitting device, the lighting device, the electronic device, and the like are semiconductor devices themselves or include semiconductor devices in some cases.

Background

As a semiconductor which can be used for a transistor, a metal oxide is attracting attention. In-Ga-Zn oxides referred to as "IGZO" and the like are typical examples of the multi-component metal oxides. By studying IGZO, a CAAC (c-axis aligned crystalline) structure and nc (nanocrystalline) structure, which are neither single crystal nor amorphous, were found (for example, non-patent document 1).

It has been reported that a transistor including a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as an "oxide semiconductor transistor" or an "OS transistor") has extremely small off-state current (for example, non-patent documents 1 and 2). Various semiconductor devices using an OS transistor (for example, non-patent documents 3 and 4) are manufactured.

The manufacturing process of the OS transistor may be integrated into the CMOS process of the existing Si transistor, and the OS transistor may be stacked on the Si transistor. For example, patent document 1 discloses a structure in which a plurality of layers including a memory cell array of an OS transistor are stacked over a substrate provided with an Si transistor.

[ Prior Art document ]

[ patent document ]

[ patent document 1] specification of U.S. patent application publication No. 2012/0063208

[ non-patent document ]

[ non-patent document 1] S.Yamazaki et al, "Properties of crystalline In-Ga-Zn-oxide semiconductor and its transducer characteristics," Jpn.J.appl.Phys., vol.53, 04ED18(2014).

[ non-patent document 2] K.Kato et al, "Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide," Jpn.J.appl.Phys., vol.51, 021201(2012).

[ non-patent document 3] S.Amano et al, "Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency," SID Symp. dig. papers, vol.41, pp.626-629(2010).

Non-patent document 4 t, ishizu et al, "Embedded Oxide Semiconductor means: a Key Enabler for Low-Power ULSI, "ECS Tran., vol.79, pp.149-156(2017).

Disclosure of Invention

Technical problem to be solved by the invention

An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure. Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure, which can reduce manufacturing cost in a semiconductor device used as a memory device using an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure which achieves reduction in power consumption in a semiconductor device used as a memory device using an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure, which can be used as a memory device using an extremely small off-state current, and which can be miniaturized. Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure and excellent reliability of data read in a semiconductor device used as a memory device using an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure in which a write operation can be performed without inverting the logic of read data in a semiconductor device used as a memory device using an extremely small off-state current.

The description of multiple objects does not preclude the existence of multiple objects. It is not necessary for a mode of the invention to achieve all of the objectives illustrated. Further, objects other than the above-mentioned objects are naturally known from the description of the present specification and the like, and such objects may be objects of one embodiment of the present invention.

Means for solving the problems

One embodiment of the present invention is a semiconductor device including: a first control circuit having a first transistor using a silicon substrate for a channel; a second control circuit over the first control circuit and having a second transistor using a metal oxide for a channel; a memory circuit on the second control circuit and having a third transistor using a metal oxide for a channel; and a global bit line and an inverted global bit line having a function of transmitting a signal between the first control circuit and the second control circuit, wherein the first control circuit includes a sense amplifier circuit having an input terminal and an inverted input terminal, and the second control circuit controls whether or not the global bit line and the inverted global bit line that discharge charges are charged based on data read from the memory circuit in a first period in which data is read from the memory circuit to the first control circuit.

One embodiment of the present invention is a semiconductor device including: a first control circuit having a first transistor using a silicon substrate for a channel; a second control circuit over the first control circuit and having a second transistor using a metal oxide for a channel; a memory circuit on the second control circuit and having a third transistor using a metal oxide for a channel; a global bit line and an inverted global bit line having a function of transmitting a signal between the first control circuit and the second control circuit; and a plurality of switches provided between the global bit line and the second control circuit and between the inverted global bit line and the second control circuit, wherein the first control circuit includes a sense amplifier having an input terminal and an inverted input terminal, the second control circuit has a function of controlling whether or not to discharge electric charges precharged to one bit line and the inverted global bit line based on data read from the memory circuit in a first period in which data is read from the memory circuit to the first control circuit, the switches are switched such that the global bit line and the input terminal and the inverted global bit line and the inverted input terminal are each in a conductive state in the first period, and the switches are switched such that the global bit line and the inverted input terminal and the inverted global bit line and the input terminal are each in a conductive state in a second period in which data read from the memory circuit is refreshed.

One embodiment of the present invention is a semiconductor device including: a first control circuit having a first transistor using a silicon substrate for a channel; a second control circuit over the first control circuit and having a second transistor using a metal oxide for a channel, a memory circuit over the second control circuit and having a third transistor using a metal oxide for a channel; and a global bit line and an inverted global bit line having a function of transmitting a signal between the first control circuit and the second control circuit, wherein the first control circuit has a sense amplifier including an amplifying circuit, an output terminal, an inverted output terminal, a first switch provided between the global bit line and the output terminal, a second switch provided between the inverted global bit line and the inverted output terminal, and a signal inverting circuit having a function of supplying a potential for inverting logic data corresponding to potentials of the global bit line and the inverted global bit line to the output terminal and the inverted output terminal electrically connected to the amplifying circuit, and the second control circuit has a function of controlling whether or not to discharge electric charges precharged to the global bit line and the inverted global bit line based on data read from the memory circuit in a first period in which the data is read from the memory circuit to the first control circuit, in a first period, the first switch and the second switch are turned off, and a potential for inverting logic data corresponding to the potentials of the global bit line and the inverted global bit line is supplied to an output terminal and an inverted output terminal electrically connected to the amplifier circuit.

In the semiconductor device according to one embodiment of the present invention, the global bit line and the inverted global bit line are preferably provided in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

In the semiconductor device according to one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

In the semiconductor device according to one aspect of the present invention, it is preferable that the second control circuit includes fourth to seventh transistors, a gate of the fourth transistor is electrically connected to a local bit line having a function of transmitting a signal between the second control circuit and the memory circuit, the fifth transistor has a function of controlling a conduction state between the gate of the fourth transistor and one of a source and a drain of the fourth transistor, the sixth transistor has a function of controlling a conduction state between the other of the source and the drain of the fourth transistor and a wiring to which a potential for flowing a current through the fourth transistor is supplied, and the seventh transistor has a function of controlling a conduction state between the one of the source and the drain of the fourth transistor and the global bit line.

Effects of the invention

One embodiment of the present invention can provide a semiconductor device or the like having a novel structure. In addition, one embodiment of the present invention can provide a semiconductor device having a novel structure and the like, which can reduce manufacturing cost in a semiconductor device used as a memory device using an extremely small off-state current. In addition, one embodiment of the present invention can provide a semiconductor device having a novel structure and the like which can reduce power consumption in a semiconductor device used as a memory device using an extremely small off-state current. In addition, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure, which can realize miniaturization of a device in a semiconductor device used as a memory device using an extremely small off-state current. In addition, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure which is excellent in reliability of data read out in a semiconductor device used as a memory device using an extremely small off-state current. In addition, an embodiment of the present invention can provide a semiconductor device or the like having a novel structure in which writing back is possible without inverting the logic of read data in a semiconductor device used as a memory device using an extremely small off-state current.

The description of a plurality of effects does not hinder the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the above effects. Other objects, effects and novel features of the present invention in one aspect thereof will become apparent from the description and drawings in the specification.

Drawings

Fig. 1 is a block diagram showing a configuration example of a semiconductor device.

Fig. 2A and 2B are a block diagram and a circuit diagram showing a configuration example of the semiconductor device.

Fig. 3A and 3B are circuit diagrams showing examples of the structure of the semiconductor device.

Fig. 4 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 5 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 6 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 7 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 8 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 9 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 10 is a timing chart showing a configuration example of the semiconductor device.

Fig. 11 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 12 is a timing chart showing a configuration example of the semiconductor device.

Fig. 13 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 14 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 15 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 16 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 17 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 18 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 19 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 20 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 21 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 22 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 23 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 24 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 25 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 26 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 27 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 28 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 29 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 30 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 31 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 32 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 33 is a circuit diagram showing a configuration example of the semiconductor device.

Fig. 34A and 34B are schematic diagrams illustrating examples of the structure of the semiconductor device.

Fig. 35 is a schematic diagram showing a configuration example of the semiconductor device.

Fig. 36A and 36B are circuit diagrams showing examples of the structure of the semiconductor device.

Fig. 37A and 37B are a block diagram and a circuit diagram showing a configuration example of the semiconductor device.

Fig. 38A and 38B are block diagrams showing examples of the structure of the semiconductor device.

Fig. 39 is a schematic sectional view showing a structural example of the semiconductor device.

Fig. 40A and 40B are schematic cross-sectional views showing examples of the structure of the semiconductor device.

Fig. 41A, 41B, and 41C are schematic cross-sectional views showing structural examples of the semiconductor device.

Fig. 42 is a schematic sectional view showing a structural example of the semiconductor device.

Fig. 43 is a schematic sectional view showing a structural example of the semiconductor device.

Fig. 44A, 44B, and 44C are a plan view and a schematic cross-sectional view showing a configuration example of the semiconductor device.

Fig. 45A, 45B, 45C, and 45D are plan views illustrating examples of the structure of the semiconductor device.

Fig. 46A is a diagram illustrating classification of the crystal structure of IGZO. Fig. 46B is a diagram illustrating an XRD spectrum of the CAAC-IGZO film. Fig. 46C is a diagram illustrating a nanobeam electron diffraction pattern of the CAAC-IGZO film.

Fig. 47 is a block diagram illustrating a configuration example of the semiconductor device.

Fig. 48 is a conceptual diagram illustrating a configuration example of the semiconductor device.

Fig. 49A and 49B are schematic views illustrating an example of an electronic component.

Fig. 50 is a diagram showing an example of an electronic apparatus.

Detailed Description

The following describes embodiments. Note that an embodiment of the present invention is not limited to the following description, and a person having ordinary skill in the art can easily understand that the mode and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

Note that in this specification and the like, ordinal numbers such as "first", "second", "third", and the like are added to avoid confusion of constituent elements. Therefore, the ordinal number does not limit the number of components. In addition, the ordinal number does not limit the order of the constituent elements. For example, in the present specification and the like, a component denoted by "first" in one embodiment may be set as a component denoted by "second" in another embodiment or the scope of the claims. For example, in this specification and the like, a component denoted by "first" in one embodiment may be omitted in another embodiment or the scope of claims.

In the drawings, the same elements or elements having the same function, the same material elements, or elements formed at the same time may be denoted by the same reference numerals, and redundant description may be omitted.

In this specification, the power supply potential VDD is sometimes simply referred to as potentials VDD, or the like. The same applies to other components (for example, signals, voltages, circuits, elements, electrodes, wirings, and the like).

When a plurality of elements are identified by the same symbol and it is necessary to distinguish them from each other, symbols used for identification such as "_ 1", "_ 2", "[ n ]", "[ m, n ]", and the like may be added to the symbols. For example, the second wiring GL is represented as a wiring GL [2 ].

(embodiment mode 1)

A configuration example of a semiconductor device which is one embodiment of the present invention is described with reference to fig. 1 to 38.

Note that a semiconductor device is a device utilizing semiconductor characteristics, and is also a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like) and a device including the circuit. The semiconductor device described in this embodiment mode can be used as a memory device using a transistor with extremely small off-state current.

< example 1 of semiconductor device Structure >

Fig. 1 is a block diagram illustrating a schematic view of a cross-sectional structure of a semiconductor device 10.

The semiconductor device 10 includes a plurality of element layers 20_1 to 20_ M (M is a natural number) on a silicon substrate 50. The element layers 20_1 to 20_ M each include a transistor layer 30 and a transistor layer 40. The transistor layer 40 is composed of a plurality of transistor layers 41_1 to 41_ k (k is a natural number of 2 or more).

In the schematic diagram shown in fig. 1, the z-axis direction is defined to explain the arrangement of the respective components. The z-axis direction refers to a direction perpendicular or substantially perpendicular to the surface of the silicon substrate 50. Note that "substantially perpendicular" refers to a state of being arranged at an angle of 85 ° or more and 95 ° or less. For ease of understanding, the z-axis direction is sometimes referred to as the vertical direction. The surface of the silicon substrate 50 corresponds to a surface formed by x-axis, y-axis defined as a direction perpendicular or substantially perpendicular to the z-axis direction. For ease of understanding, the x-axis direction is sometimes referred to as the depth direction, and the y-axis direction is sometimes referred to as the horizontal direction.

Each of the transistor layers 40 configured by the plurality of transistor layers 41_1 to 41 — k includes a memory circuit having a plurality of memory cells (not shown). Each memory cell includes a transistor and a capacitor. Note that the capacitor is sometimes referred to as a capacitive element. The element layer is a layer provided with an element such as a capacitor or a transistor, and is also a layer including a member such as a conductor, a semiconductor, or an insulator.

Note that the memory cells included in the respective transistor layers 41_1 to 41 — k may also be referred to as a dosram (dynamic Oxide Semiconductor Random Access memory) in which a transistor including an Oxide Semiconductor in a channel formation region (hereinafter, referred to as an OS transistor) is used for a memory. Since the memory cell can be formed of one transistor and one capacitor, the density of the memory can be increased. Further, by using the OS transistor, the holding period of data can be extended.

In the structure according to one embodiment of the present invention, since the memory cell including the OS transistor is used, a leakage current (hereinafter referred to as an off-state current) flowing between the source and the drain at the time of turning off is extremely small, and thus, a charge corresponding to a desired voltage can be held in the capacitor connected to the other of the source and the drain by utilizing this characteristic. In other words, in the memory cell, the written data can be held for a long time. Therefore, the frequency of refreshing data can be reduced, and low power consumption can be achieved.

In addition, in a memory cell using an OS transistor, data can be written and read by charging and discharging electric charges, and thus data can be written and read virtually indefinitely. The memory cell using the OS transistor has good rewrite resistance because it has no change in atomic structure due to a magnetic memory, a resistance change memory, or the like. Further, even when a memory cell using an OS transistor is subjected to a repeated rewriting operation like a flash memory, instability due to an increase in electron trap centers does not occur.

Further, since a memory cell using an OS transistor can be freely arranged on a silicon substrate or the like provided with a transistor including silicon in a channel formation region (hereinafter referred to as an Si transistor), integration is easy. In addition, since the OS transistor can be manufactured by the same manufacturing apparatus as the Si transistor, it can be manufactured at low cost.

In addition, when a back gate electrode is provided in addition to the gate electrode, the source electrode, and the drain electrode, the OS transistor can be a 4-terminal semiconductor element. The circuit network can be configured to independently control input and output of signals flowing between the source and the drain in accordance with a voltage applied to the gate electrode or the back gate electrode. Therefore, circuit design can be performed in the same manner as LSI. In addition, the OS transistor has electrical characteristics superior to those of the Si transistor in a high-temperature environment. Specifically, even at a high temperature of 125 ℃ or higher and 150 ℃ or lower, the ratio of the on-state current to the off-state current is large, and thus a good switching operation can be performed.

The silicon substrate 50 includes a control circuit for writing or reading data to or from a selected memory cell through a global bit line (sometimes referred to as global bit line GBL) and a local bit line (sometimes referred to as local bit line LBL) in the transistor layer 30. The control circuit includes a plurality of Si transistors using a silicon substrate 50 for a channel. The control circuit in the silicon substrate 50 includes a sense amplifier circuit and the like composed of Si transistors. The control circuit in the silicon substrate 50 is sometimes referred to as a first control circuit.

The transistor layer 30 has a function of writing and reading data to and from one memory cell selected from a plurality of memory cells included in the transistor layer 40.

The transistor layer 30 includes a control circuit including a reading transistor for reading data and a transistor for controlling data writing and data reading. The gate of the read transistor is connected to a local bit line connected to one of the plurality of memory cells. With this configuration, the sense transistor can increase a slight potential difference of the local bit line and output the increased potential difference to the global bit line when data is read. The control circuit provided in the transistor layer 30 is used as an amplification circuit composed of an OS transistor. The control circuitry included in transistor layer 30 is sometimes referred to as second control circuitry.

The second control circuit may be configured to hold a gate of the readout transistor at a potential corresponding to a threshold voltage of the readout transistor. With this configuration, the reading transistor can reduce unevenness in data read from the memory cell.

Note that the local bit line LBL is a wiring directly connected to the memory cell. The global bit line GBL is a wiring that selects any one of the plurality of local bit lines and is electrically connected to the memory cell via the second control circuit. The global bit line GBL or the local bit line LBL has a function of transferring a signal. The data signal supplied to the global bit line GBL or the local bit line LBL corresponds to a signal written into or read out from the memory cell. The data signal is a binary signal having a high-level or low-level potential corresponding to data 1 or data 0. The data signal may be a multi-value of three or more values. In addition, the global bit line GBL is sometimes used as an inverted global bit line GBLB which is a wiring pair for reading data.

As shown in fig. 1, the transistor layer 40 is disposed in a z-axis direction in a stack with the transistor layer 30. The transistor layer 40 included in each of the element layers 20_1 to 20_ M is selected by the second control circuit. The second control circuit has a function of converting a data signal written in the memory cell into a change in the potential of the global bit line GBL by using a difference in the amount of current flowing through the reading transistor included in the transistor layer 30 and outputting the result to the first control circuit. Further, the second control circuit has a function of supplying the data signal output by the first control circuit to the local bit line.

In one embodiment of the present invention, an OS transistor with extremely small off-state current is used as a transistor provided in each element layer. Therefore, the refresh frequency of the data held in the memory cell can be reduced, and a semiconductor device with lower power consumption can be realized. Since the OS transistor can be stacked and manufactured by repeating the same manufacturing process in the vertical direction, the manufacturing cost can be reduced. In one embodiment of the present invention, the transistors constituting the memory cell may be arranged not in the planar direction but in the vertical direction to increase the memory density, so that the device can be miniaturized. In addition, since the OS transistor has smaller variations in electrical characteristics than the Si transistor even in a high-temperature environment, a semiconductor device used as a highly reliable storage device can be realized.

Next, fig. 2A shows a block diagram of the element layer 20 corresponding to any one of the element layers 20_1 to 20_ M of fig. 1.

As shown in fig. 1, the device layer 20 according to one embodiment of the present invention has a structure in which a plurality of transistor layers 40 including memory cells are provided on a transistor layer 30 in a z-axis direction. By adopting this structure, the distance between the transistor layer 30 and the transistor layer 40 can be shortened. When the local bit line is shortened, parasitic capacitance can be reduced. By repeatedly manufacturing the plurality of transistor layers 40 in the vertical direction using the same manufacturing process, a reduction in manufacturing cost can be achieved.

Fig. 2B is a diagram showing each component in the element layer 20 shown in fig. 2A by circuit marks.

Transistor layer 30 has control circuitry 35 that includes transistor 31, transistor 32, transistor 33, and transistor 34. The transistor layers 41_1, 41_2 each include a plurality of memory cells 42. The memory cell 42 includes a transistor 43 and a capacitor 44. The transistor 43 is used as a switch for switching a conductive state (on) or a non-conductive state (off) between the local bit line LBL and the capacitor 44 according to control of the word line WL connected to the gate. The local bit line LBL is connected to the gate of the transistor 31. The word line WL switches the transistor 43 on or off with a word signal (sometimes referred to as a signal WL) supplied to the word line WL. The capacitor 44 is connected to a wiring CSL supplying a fixed potential.

The transistors included in the control circuit 35 are connected to each other as illustrated in fig. 2B. Specifically, one of a source and a drain of the transistor 33 is connected to a gate of the transistor 31. The other of the source and the drain of the transistor 33 is connected to one of the source and the drain of the transistor 34 and one of the source and the drain of the transistor 31. One of a source and a drain of the transistor 32 is connected to the other of the source and the drain of the transistor 31. The other of the source and the drain of the transistor 32 is connected to a wiring SL. The other of the source and the drain of the transistor 34 is connected to the global bit line GBL. The transistors 32, 33, and 34 are used as switches for switching a conductive state or a non-conductive state between the source and the drain in accordance with the signals RE, WE connected to the gates and the control of the MUX. The signals RE, WE, and MUX are signals for switching on and off of the transistor used as the switch, and as an example, the transistor may be turned on at an H level and turned off at an L level.

The transistor 43 is the above-described OS transistor. The capacitor 44 has a structure in which an insulator is interposed between conductors used as electrodes. Note that as the conductor constituting the electrode, a semiconductor layer or the like provided with conductivity may be used in addition to a metal. The capacitor 44 may be disposed above or below the transistor 43, or a part of a semiconductor layer, an electrode, or the like constituting the transistor 43 may be used as one electrode of the capacitor 44, which will be described in detail later.

The transistor 31 has a function of causing a current to flow between the source and the drain of the transistor 31 in accordance with the potential of the local bit line LBL. When the potential of the gate of the transistor 31 exceeds the threshold voltage of the transistor 31, a current flows between the source and the drain.

The control circuit 35 has a function of controlling whether or not a current flowing between the source and the drain of the transistor 31 flows between the wiring SL and the global bit line GBL, a function of transferring the potential of the global bit line GBL to the local bit line LBL, or a function of discharging the gate potential of the transistor 31 to the wiring SL through between the source and the drain of the transistor 31.

The transistors 31 to 34 are formed of OS transistors, similarly to the transistor 43. Since the transistor layers 30 and 40 constituting the element layer 20 using the OS transistor can be stacked on the silicon substrate 50 including the Si transistor, integration is easy.

Fig. 3A shows an example of a circuit configuration of a control circuit 51 corresponding to a first control circuit formed of Si transistors provided on a silicon substrate 50. The figure shows a switch circuit 52, a precharge circuit 53, a precharge circuit 54, a sense amplifier 55, a global bit line GBL, an inverted global bit line GBLB, a bit line BL, and an inverted bit line BLB connected to the control circuit 51 in the control circuit 51. Note that in this specification and the like, a terminal or a part of a wiring connected to the global bit line GBL or the inverted global bit line GBLB in the control circuit 51 may be referred to as an input terminal and an inverted input terminal of the control circuit 51. The bit line BL and the inversion bit line BLB used as wirings connected to the sense amplifier 55 may be referred to as an output terminal and an inversion output terminal of the control circuit 51.

As shown in fig. 3A, for example, the switch circuit 52 includes n-channel type transistors 52_1, 52_ 2. The transistors 52_1 and 52_2 switch the conductive states of the pair of global bit lines GBL and the inverted global bit line GBLB and the pair of bit lines BL and the inverted bit line BLB in accordance with a signal of the wiring CSEL. As the switch circuit 52, an analog switch combined with a p-channel transistor may be used.

As shown in fig. 3A, the precharge circuit 53 is constituted by n-channel type transistors 53_1 to 53_ 3. Precharge circuit 53 is a circuit for precharging to potential VPRE corresponding to potential VDD/2 between bit line BL and inverted bit line BLB in response to a signal of wiring EQ. As shown in fig. 3A, the precharge circuit 54 is constituted by p-channel type transistors 54_1 to 54_ 3. Precharge circuit 54 is a circuit for precharging to a potential VPRE corresponding to a potential VDD/2 between bit line BL and inverted bit line BLB in response to a signal of wiring EQB. In addition, either one of the precharge circuits 53 and 54 may be used. The precharge circuits 53 and 54 have a function of electrically connecting the bit line BL and the inversion bit line BLB and equalizing (equalizing) them.

As shown in fig. 3A, the sense amplifier 55 is configured by p-channel transistors 55_1 and 55_2 and n-channel transistors 55_3 and 55_4 connected to a wiring SAP or a wiring SAN. The wiring SAP or the wiring SAN is a wiring having a function of supplying VDD or VSS. The transistors 55_1 to 55_4 are transistors constituting an inverter loop.

Fig. 3B shows a diagram illustrating a circuit block corresponding to the control circuit 51 illustrated in fig. 3A and the like. As shown in fig. 3B, the control circuit 51 may be shown as a block in the drawings or the like.

Fig. 4 is a circuit diagram illustrating an operation example of the semiconductor device 10 of fig. 1. In fig. 4, the circuit block described with reference to fig. 3A and 3B is used for illustration.

As shown in fig. 4, the transistor layers 41_1 to 41 — k include a memory cell 42. The memory cell 42 is connected to a pair of local bit lines LBL and LBL _ pre. The memory cell 42 connected to the local bit line LBL is subjected to data writing or reading. The local bit line LBL _ pre is precharged for potential comparison, and the memory cell connected to the local bit line LBL _ pre continues to hold data.

The local bit line LBL is connected to the global bit line GBL through the control circuit 35. Local bit line LBL _ pre is electrically connected to inverted global bit line GBLB through control circuit 35_ pre. Global bit line GBL and inverted global bit line GBLB are electrically connected to control circuit 51. Note that the signals RE, WE, and MUX that control the turning on or off of the transistors 32, 33, and 34 of the control circuit 35 and the control circuit 35_ pre are omitted in the drawing. The signals RE, WE, and MUX are signals for performing different controls in the control circuit 35 and the control circuit 35_ pre, respectively. For example, the signals for controlling the on/off of the transistors 32, 33, and 34 of the control circuit 35 are signals RE1, WE1, and MUX1 (not shown), and the signals for controlling the on/off of the transistors 32, 33, and 34 of the control circuit 35_ pre are signals RE2, WE2, and MUX2 (not shown).

Fig. 5 to 9 are schematic diagrams for explaining the operation of the circuit diagram shown in fig. 5. Note that in fig. 5 to 9, in order to facilitate understanding of the description, a part of a wiring electrically connected by turning on or off a transistor serving as a switch is sometimes indicated by a thick line. The description will be given assuming that the data held in the memory cell 42 for reading and writing data is data "1", that is, the H-level potential (indicated by "H" in the drawing) is held. In addition, cross signs are attached to transistors included in the control circuits 35 and 35_ pre in the off state.

Fig. 5 is a schematic diagram illustrating a period during which the local bit line LBL and the local bit line LBL _ pre are precharged. During the precharge period, transistors 33 and 34 of both control circuits 35 and 35_ pre are turned on to supply precharge voltage V to global bit line GBL and inverted global bit line GBLB_LBLThe bit line is transferred to the local bit line LBL and the local bit line LBL _ pre to be precharged. By performing the precharge, each wiring is pressed up to the power supply voltage VDD (for example, 1.5V). Precharge voltage V_LBLCorresponding to the potential VPRE described above.

FIG. 6 is a diagram illustrating the state where the gate of the transistor 31 is held at the threshold voltage V of the transistor 31_THAnd correcting the data read out corresponding to the threshold voltage V_THSchematic of the period of data of (1). During this period, both the transistors 34 of the control circuits 35 and 35_ pre are turned off and supplied to the globalPrecharge voltage V of bit line GBL and inverted global bit line GBLB_LBLTo the wiring SL. In the discharge, for example, the voltage of the wiring SL is set to be half of the precharge voltage. Current I flowing by discharge_disThe gate potential of the transistor 31 becomes 0.5 XV of the threshold voltage_LBL+V_THAnd then stop. During this period, global bit line GBL and inverted global bit line GBLB are precharged to voltage V₀. Voltage V₀Is set to a voltage lower than the potential supplied to other wirings and the like, for example, 0V.

In fig. 7, the transistor 43 of the memory cell 42 for reading data is turned on to share charge between the capacitor 44 and the local bit line LBL (charge sharing). The potential of the local bit line LBL is from 0.5V_LBL+V_THUp to a voltage of 0.5 x V_LBL+V_TH+ Δ V. The voltage Δ V here results from charge transfer of the H-level potential held in the memory cell 42. In the control circuits 35 and 35_ pre, the transistor 33 is turned off, and the potential of the wiring SL is higher than the voltage V₀. For example, the potential of the wiring SL is set to VDD. Controlling the gate voltage of transistor 31 of circuit 35 by charge sharing up to a voltage of 0.5 x V_LBL+V_TH+ Δ V, so current I_HAnd flows through. On the other hand, in the control circuit 35_ pre, the gate voltage of the transistor 31 is held at a voltage of 0.5 × V_LBL+V_THTherefore, the current flow rate is smaller than that of the control circuit 35. Therefore, the voltage of the global bit line GBL is higher than the voltage of the inverted global bit line GBLB.

In fig. 8, transistors 32 and 33 of both control circuits 35 and 35_ pre are turned off, and sense amplifiers included in control circuit 51 are activated to set the voltages of global bit line GBL and inverted global bit line GBLB to H level or L level. The sense amplifier is activated to determine the H level or the L level of each wiring based on the voltage difference between the global bit line GBL and the inverted global bit line GBLB.

In fig. 9, transistors 33 and 34 of both control circuits 35 and 35_ pre and transistor 43 included in memory cell 42 are turned on, and the voltages of global bit line GBL and inverted global bit line GBLB determined in the previous period are written back to memory cell 42.

By adopting the above-described structure, the voltage corresponding to the logic of the data read out by charge sharing can be rewritten back into the memory cell 42 without inverting the logic. In other words, in the memory cell 42 in which the data "1", that is, the H-level potential is read out, the data "1", that is, the H-level potential can be written back.

Fig. 10 is a timing chart showing operations in the respective periods described with reference to fig. 5 to 9. The timing chart of fig. 10 shows a pair of global bit line GBL and global bit line GBLB for each case where data is at H level (data ═ H) and data is at L level (data ═ L).

In the timing chart shown in fig. 10, the time T11 to the time T13 correspond to a period of data writing. The time T13 to the time T16 correspond to a period for obtaining the threshold voltage, i.e., a calibration period. The time T16 to time T18 correspond to a period during which data is read. The time T18 to time T20 correspond to a period during which data is written back. Note that in fig. 10, the signals RE, WE, and MUX are signals different between the control circuit 35 and the control circuit 35_ pre, but the control circuit 35 and the control circuit 35_ pre perform the same operation, and therefore the signals RE, WE, and MUX will be described.

At time T11, by setting the signal MUX or the signal WE to the H level and transferring write data from the sense amplifier, one of the pair of global bit lines GBL and the inverted global bit line GBLB is charged. The potential of the local bit line LBL rises. The potential of the word line WL is set to H level and the potential supplied to the local bit line LBL (H level in fig. 10) is written into the memory cell 42.

At time T12, the potential of the word line WL is set to the L level. The storage unit 42 holds data.

At time T13, both wirings SAP and SAN are set to VDD, signals of wirings EQ and EQB are inverted, and both of a pair of global bit lines GBL and an inverted global bit line GBLB are set to H level. The local bit line LBL _ pre is precharged to the H-level potential. Then, the signal MUX is set to L level. Further, the signal WE may also be set to the L level.

At time T14, the signal RE and the signal WE are set to H level. The potential of the local bit line LBL and the potential of the local bit line LBL _ pre are lowered by the discharge through the transistor 31. This discharge is stopped when the voltage between the gate and the source of the transistor 31 becomes the threshold voltage of the transistor 31. At time T14, both wirings SAP and SAN are set to VSS (0V) and the pair of global bit line GBL and inverted global bit line GBLB are set to the L level.

At time T15, both the signal WE and the signal RE are set to the L level. The local bit line LBL and the local bit line LBL _ pre hold potentials corresponding to the threshold voltage of the transistor 31. The signals EQ, EQB are inverted again to stop the precharging. That is, the pair of global bit lines GBL and the inverted global bit line GBLB become an electrically floating state, i.e., a floating state. Further, at time T15, the potential of the wiring SL is switched from the L level to the H level. By performing this switching, the direction of the current flowing through the transistor 31 can be switched.

At time T16, the word line WL is set to H level, and charge sharing is performed. The potential of the local bit line LBL changes according to data written into the memory cell 42. When writing H-level data into the memory cell 42, the potential of the local bit line LBL rises, and when writing L-level data into the memory cell 42, the potential of the local bit line LBL falls. On the other hand, since charge sharing by the operation of the word line WL is not performed in the local bit line LBL _ pre, the potential does not change.

At time T17, by setting the signal RE and the signal MUX to the H level, current flows through the transistor 31 included in the control circuit 35 and the transistor 31 included in the control circuit 35_ pre in accordance with the potentials of the local bit line LBL and the local bit line LBL _ pre. Since the potentials of the local bit line LBL and the local bit line LBL _ pre are different, the current flowing through the transistor 31 included in the control circuit 35 and the current flowing through the transistor 31 included in the control circuit 35_ pre are different. The current difference corresponds to the potential of the local bit line LBL, which changes due to charge sharing, that is, data read from the memory cell 42. Therefore, as shown in fig. 10, the data of the memory cell 42 can be converted into the amount of change in the potential of the pair of global bit lines GBL and the inverted global bit line GBLB.

At time T18, the signal RE is set to the L level. Then, the sense amplifier 55 is operated by supplying power supply voltages (VDD, VSS) to the wirings SAP, SAN. The potentials of the pair of global bit lines GBL and the inverted global bit line GBLB are determined due to the operation of the sense amplifier 55.

At time T19, by setting signal WE to the H level, the voltage corresponding to the logic of the read data can be written back into memory cell 42 again.

At time T20, signal MUX, signal WL, and signal WE are set to the L level. The write back of data corresponding to the logic of the read data can be completed in the memory cell 42.

Note that the precharging of the local bit lines LBL is performed by the global bit lines GBL in the structure shown in fig. 4, but is not limited thereto. For example, as shown in fig. 11, it is preferable to adopt a configuration in which the transistor 37 is provided in the same layer as the control circuit, and the transistor 37 is controlled by the signal PE to precharge the transistor 37 with the voltage Vp. With this configuration, power consumption of the charge/discharge portion with respect to global bit line GBL can be reduced.

Fig. 12 is a timing chart for explaining the operation of the configuration shown in fig. 11. As shown in the timing chart of fig. 12, the signal PE is controlled to be at the H level at time T13 to time T14. By adopting this configuration, unnecessary charging of global bit line GBL and inverted global bit line GBLB can be suppressed.

A transistor layer including a memory cell and a control circuit according to one embodiment of the present invention has the following structure: when writing data read from the memory cell, the direction of the current flowing through the transistor 31 is reversed by switching the potentials of the wiring SL and the global bit line GBL. By adopting this structure, write-back can be performed without inverting the logic of data written back into the memory cell.

< example 2 of semiconductor device construction >

Fig. 13 is another circuit diagram illustrating an operation example of the semiconductor device 10 of fig. 1. Fig. 13 shows an example of a configuration in which switches SW and SW _ B for switching the connection between the input terminal of the control circuit 51 and the global bit line GBL and the inverted global bit line GBLB are provided in addition to the circuit blocks described in fig. 3A and 3B. As shown in fig. 13, the connection between the input terminal of control circuit 51 and global bit line GBL and inverted global bit line GBLB can be switched by switching switches SW and SW _ B. Note that one of the pair of input terminals of the control circuit 51 may be referred to as a first input terminal and the other as a second input terminal.

As shown in fig. 13, the transistor layers 41_1 to 41 — k include memory cells 42. The memory cell 42 is connected to a pair of local bit lines LBL and LBL _ pre. The memory cell 42 connected to the local bit line LBL is subjected to data writing or reading. The local bit line LBL _ pre is precharged, and the memory cell connected to the local bit line LBL _ pre continues to hold data.

The local bit line LBL is electrically connected to the global bit line GBL through the control circuit 35. Local bit line LBL _ pre is electrically connected to inverted global bit line GBLB through control circuit 35_ pre. Global bit line GBL and inverted global bit line GBLB are electrically connected to control circuit 51 via switch SW or switch SW _ B. Note that the signals RE, WE, and MUX that control the turning on or off of the transistors 32, 33, and 34 of the control circuit 35 and the control circuit 35_ pre are omitted in the drawing. The signals RE, WE, and MUX are signals for performing different controls in the control circuit 35 and the control circuit 35_ pre, respectively. For example, the signals for controlling the on or off of the transistors 32, 33, 34 of the control circuit 35 are the signals RE1, WE1 and MUX1, and the signals for controlling the on or off of the transistors 32, 33, 34 of the control circuit 35_ pre are the signals RE2, WE2 and MUX 2.

Fig. 14 to 17 are schematic diagrams for explaining the operation of the circuit diagram shown in fig. 13. Note that in fig. 14 to 17, in order to facilitate understanding of the description, a part of a wiring electrically connected to each other by turning on or off a transistor serving as a switch may be indicated by a thick line. The description will be given assuming that the data held in the memory cell 42 for reading and writing data is data "1", that is, the H-level potential (indicated by "H" in the drawing) is held. In addition, cross signs are attached to transistors included in the control circuits 35 and 35_ pre in the off state.

In the description of fig. 14 to 17, it is assumed that data writing of the memory is ended and to maintain the threshold value by the local bit line LBL and the local bit line LBL _ preThe state of the voltage obtained by the correction operation is the initial state. Assuming that the potential of the wiring SL is, for example, a precharge voltage V_LBLIs corrected with the threshold voltage V of the transistor 31 taken into account_THVoltage of 0.5 XV_LBL+V_THHeld on global bit line GBL and inverted global bit line GBLB corresponding to V₁The state of the voltage (e.g., VDD) will be described. The local bit line LBL and the local bit line LBL _ pre hold the threshold voltage V of the transistor 31 by setting the wiring SL to VSS and releasing charges to the wiring SL through the transistor 31_THAnd (4) finishing. The voltages held in the local bit line LBL and the local bit line LBL _ pre are not limited to the threshold voltages, and may hold other voltages.

In fig. 14, the transistor 43 of the memory cell 42 for reading data is turned on to share charge between the capacitor 44 and the local bit line LBL (charge sharing). The potential of the local bit line LBL is from 0.5V_LBL+V_THUp to a voltage of 0.5 x V_LBL+V_TH+ Δ V. The voltage Δ V here results from charge transfer of the H-level potential held in the memory cell 42. In addition, in the control circuits 35 and 35_ pre, the transistor 33 is turned off, and the potential of the wiring SL is made lower than the voltage V₀. For example, the potential of the wiring SL is set to VSS (0V). Controlling the gate voltage of transistor 31 of circuit 35 by charge sharing up to a voltage of 0.5 x V_LBL+V_TH+ Δ V, so current I is discharged by global bit line GBL_HAnd flows through. On the other hand, in the transistor 31 of the control circuit 35_ pre, the gate voltage is held at a voltage of 0.5 × V_LBL+V_THTherefore, the current flow rate is smaller than that of the control circuit 35. Therefore, the voltage of the global bit line GBL is like the voltage V₁Δ V is decreased as much as that of global bit line GBLB, and the voltage of global bit line GBLB is inverted to a voltage V higher than that of global bit line GBL₁,. In the state of fig. 14, the first input terminal of the control circuit 51 is connected to one of the global bit line GBL and the inverted global bit line GBLB via the switches SW and SW _ B. A second input terminal of the control circuit 51 is connected to the other of the global bit line GBL and the inverted global bit line GBLB through the changeover switches SW, SW _ B.

In fig. 15, the transistors 32, 33 are turned off. In the state of fig. 15, the first input terminal and the second input terminal of the control circuit 51 are not connected to the global bit line GBL and the inverted global bit line GBLB by the changeover switches SW and SW _ B. Global bit line GBL or inverted global bit line GBLB is in an electrically floating state. In this state, the first input terminal of the control circuit 51 holds the voltage V₁Δ V and the second input terminal holds a voltage V₁. The voltage- Δ V described here is derived from charge fluctuation caused by a current flowing from the global bit line GBL through the transistor 31 to the wiring SL.

In fig. 16, the first input terminal and the second input terminal of the control circuit 51 are not connected to the global bit line GBL and the inverted global bit line GBLB via the switches SW and SW _ B, as in the state of fig. 15. Global bit line GBL or inverted global bit line GBLB is in an electrically floating state. In which state the sense amplifiers comprised by the control circuit 51 are activated. The first input terminal is determined to be an L level and the second input terminal is determined to be an H level. As shown in fig. 16, the global bit line GBL or the inverted global bit line GBLB is brought into an electrically floating state and the sense amplifier is activated, so that power consumption required for charging and discharging the load of the global bit line GBL or the inverted global bit line GBLB can be reduced and the time required until data is determined can be shortened.

In fig. 17, the first input terminal of the control circuit 51 is connected to the other of the global bit line GBL and the inverted global bit line GBLB via the switches SW and SW _ B. The second input terminal of control circuit 51 is connected to one of global bit line GBL and inverted global bit line GBLB via switches SW and SW _ B. In other words, connection is performed in a state different from the state of fig. 14. Then, the global bit line GBL is determined to be H level and the inverted global bit line GBLB is determined to be L level. Then, the transistors 33 and 34 and the transistor 43 included in the memory cell 42 are turned on to write the determined voltages of the global bit line GBL and the inverted global bit line GBLB back into the memory cell 42.

By adopting the above-described structure, the voltage corresponding to the logic of the data read out by charge sharing can be rewritten back into the memory cell 42 without inverting the logic.

Further, a configuration example different from fig. 14 to 17 will be described with reference to fig. 18 to 21.

In fig. 18, the transistor 43 of the memory cell 42 for reading data is turned on to share charge between the capacitor 44 and the local bit line LBL (charge sharing). The description of fig. 18 is the same as the description of fig. 14. In addition, the first input terminal of the control circuit 51 is connected to one of the global bit line GBL and the inverted global bit line GBLB via the switches SW and SW _ B in the state shown in fig. 18. A second input terminal of the control circuit 51 is connected to the other of the global bit line GBL and the inverted global bit line GBLB through the changeover switches SW, SW _ B.

In fig. 19, the transistors 32, 33 are turned off. In the state of fig. 19, the first input terminal and the second input terminal of the control circuit 51 are not connected to the global bit line GBL and the inverted global bit line GBLB via the switches SW and SW _ B. Global bit line GBL or inverted global bit line GBLB is in an electrically floating state. In this state, the first input terminal of the control circuit 51 holds the voltage V₁And the second input terminal holds a voltage V₁-ΔV。

In fig. 20, the first input terminal of the control circuit 51 is connected to the other of the global bit line GBL and the inverted global bit line GBLB via the changeover switches SW and SW _ B. The second input terminal of control circuit 51 is connected to one of global bit line GBL and inverted global bit line GBLB via switches SW and SW _ B. In other words, the connection is performed in a state different from the state of fig. 18. In this state the sense amplifier comprised by the control circuit 51 is activated. The global bit line GBL is determined to be H level and the inverted global bit line GBLB is determined to be L level.

In fig. 21, transistors 33 and 34 and transistor 43 included in memory cell 42 are turned on to write the determined voltages of global bit line GBL and inverted global bit line GBLB back to memory cell 42.

By adopting the above-described structure, the voltage corresponding to the logic of the data read out by charge sharing can be rewritten back into the memory cell 42 without inverting the logic. In the configuration described in fig. 18 to 21, when an output is made from the sense amplifier to the outside of the memory through the bit line BL and the inversion bit line BLB, the output may be made such that the logic of the global bit line GBL and the inversion global bit line GBLB is not inverted with the logic of the bit line BL and the inversion bit line BLB.

Further, a configuration example different from fig. 14 to 17 and 18 to 21 will be described with reference to fig. 22 to 24.

In fig. 22, the transistor 43 of the memory cell 42 for reading data is turned on to share charge between the capacitor 44 and the local bit line LBL (charge sharing). The description of fig. 22 is the same as that of fig. 14 or 18. The first input terminal of the control circuit 51 is connected to one of the global bit line GBL and the inverted global bit line GBLB via the switches SW and SW _ B in the state shown in fig. 22. A second input terminal of the control circuit 51 is connected to the other of the global bit line GBL and the inverted global bit line GBLB through the changeover switches SW, SW _ B.

In fig. 23, the transistors 32 and 33 are turned off and the sense amplifier included in the control circuit 51 is activated. Then, the global bit line GBL is determined to be L level and the inverted global bit line GBLB is determined to be H level.

In fig. 24, the global bit line GBL and the inverted global bit line GBLB are short-circuited by switching the switches SW and SW _ B to the first input terminal side of the control circuit 51. In other words, only the switch of the bit line to be written back is switched. The voltages of the global bit line GBL and the inverted global bit line GBLB determined by turning on the transistors 33 and 34 and the transistor 43 included in the memory cell 42 are set to H, and data H is written back to the memory cell 42.

By adopting the above-described structure, the voltage corresponding to the logic of the data read out by charge sharing can be rewritten back into the memory cell 42 without inverting the logic. In addition, by adopting the above driving method, only the global bit line GBL to be written back can be charged and discharged, and therefore, the power consumption can be half that when both the changeover switches SW and SW _ B are switched, and low-power-consumption driving can be realized. In the configuration example described above, since electrons can be extracted from global bit line GBL to wiring SL, voltage Vgs between the gate and the source of transistor 31 can be kept constant. This makes it possible to increase the speed of the reading operation.

< example 3 of semiconductor device construction >

Fig. 25 is a circuit diagram illustrating an example different from configuration examples 1 and 2. Fig. 25 shows an example of a circuit configuration of a control circuit 51A corresponding to a first control circuit formed of Si transistors provided on a silicon substrate 50. The switch circuit 52, the precharge circuit 53, the sense amplifier 55, the potential setting circuit 59, the global bit line GBL, the inverted global bit line GBLB, the bit line BL, and the inverted bit line BLB connected to the control circuit 51A are illustrated in the control circuit 51A. Note that in this specification and the like, a terminal or a part of a wiring connected to the global bit line GBL or the inverted global bit line GBLB in the control circuit 51A may be referred to as an input terminal and an inverted input terminal of the control circuit 51. The bit line BL and the inversion bit line BLB used as wirings connected to the sense amplifier 55 may be referred to as an output terminal and an inversion output terminal of the control circuit 51A.

As shown in fig. 25, for example, the switch circuit 52 includes n-channel transistors 52_1, 52_ 2. The transistors 52_1 and 52_2 switch the conductive states of the pair of global bit lines GBL and the inverted global bit line GBLB and the pair of bit lines BL and the inverted bit line BLB in accordance with a signal of the wiring CSEL. As the switch circuit 52, an analog switch combined with a p-channel transistor may be used.

As shown in fig. 25, the precharge circuit 53 is constituted by n-channel transistors 53_1 to 53_ 3. The precharge circuit 53 is a circuit for equalizing the bit line BL and the inversion bit line BLB and precharging the bit line BL and the inversion bit line BLB in response to a signal of the wiring EQ. Potential VPRE corresponds to potential VDD/2 between bit line BL and inverted bit line BLB.

As shown in fig. 25, the sense amplifier 55 includes p-channel transistors 55_1 and 55_2 and n-channel transistors 55_3 and 55_4 connected to a wiring SAP or a wiring SAN. The wiring SAP or the wiring SAN is a wiring having a function of supplying VDD or VSS. The transistors 55_1 to 55_4 are transistors constituting an inverter loop. The sense amplifier 55 has a function as a circuit for precharging the wiring SAP or the wiring SAN by supplying a precharge voltage thereto.

As shown in fig. 25, the potential setting circuit 59 includes n-channel type transistors 57_1, 57_2 connected to a wiring for supplying the potential VSS and n-channel type transistors 58_1, 58_2 connected to the sense amplifier 55. The turning on or off of the transistors 57_1, 57_2 is controlled according to the signal EN 1. In addition, the current flowing through the transistors 58_1 and 58_2 is controlled in accordance with the potentials of the global bit line GBL and the inverted global bit line GBLB connected to the gates. Data on the bit line BL and the inverted bit line BLB when the sense amplifier is operated is determined by currents flowing through the transistors 58_1 and 58_ 2.

Fig. 26 is another circuit diagram illustrating an operation example of the semiconductor device 10 in fig. 1. Fig. 26 shows a structure in which the structure of fig. 2 is used and the control circuit 51A described in fig. 25 is used for a control circuit provided over a silicon substrate 50.

As shown in fig. 26, the transistor layers 41_1 to 41 — k include memory cells 42. The memory cell 42 is connected to a pair of local bit lines LBL and LBL _ pre. The memory cell 42 connected to the local bit line LBL is subjected to data writing or reading. The local bit line LBL _ pre is precharged, and the memory cell connected to the local bit line LBL _ pre continues to hold data.

The local bit line LBL is electrically connected to the global bit line GBL through the control circuit 35. Local bit line LBL _ pre is electrically connected to inverted global bit line GBLB through control circuit 35_ pre. The global bit line GBL and the inverted global bit line GBLB are electrically connected to a control circuit 51A provided on the silicon substrate 50. In addition, although the signals RE, WE, and MUX for turning on or off the control transistors supplied to the control circuits 35 and 35_ pre are omitted in the drawing, the signals RE, WE, and MUX are different between the control circuit 35 and the control circuit 35_ pre.

Fig. 27 to 33 are schematic diagrams for explaining the operation of the circuit diagram shown in fig. 26. Note that in fig. 27 to 33, in order to facilitate understanding of the description, a part of a wiring electrically connected to each other by turning on or off a transistor serving as a switch is indicated by a thick line. The description will be given assuming that data held in the memory cell 42 for reading and writing data is data "1", i.e., an H-level potential (indicated by "H" in the drawing). In addition, cross signs are attached to transistors included in the control circuits 35 and 35_ pre in the off state.

Fig. 27 is a schematic diagram illustrating a period during which the local bit line LBL and the local bit line LBL _ pre are precharged. During the precharge period, transistors 33 and 34 are turned on to transmit precharge voltage V to global bit line GBL and inverted global bit line GBLB_LBLThe bit line is transferred to the local bit line LBL and the local bit line LBL _ pre to be precharged.

Fig. 28 is a schematic diagram illustrating the balancing (equalization) of the local bit line LBL and the local bit line LBL _ pre. During the period of performing the leveling, transistors 53_1 to 53_3 are turned on, and the transistors between global bit line GBL and inverted global bit line GBLB are turned on.

FIG. 29 is a diagram illustrating that the threshold voltage V of the transistor 31 is reflected in the gate holding of the transistor 31_THCorrecting the voltage corresponding to the threshold voltage V in the read data_THSchematic of the period of data of (1). During this period, both transistors 34 of control circuits 35 and 35_ pre are turned off, and precharge voltage V supplied to global bit line GBL and inverted global bit line GBLB is set to be lower than the first predetermined voltage_LBLTo the wiring SL. For example, when the potential of the wiring SL is set as the precharge voltage V_LBLWhen the discharge is performed at half the voltage, the current I flowing through the discharge_disThe gate potential of the transistor 31 becomes 0.5 XV of the threshold voltage_LBL+V_THAnd then stop. During this period, global bit line GBL and inverted global bit line GBLB are precharged to voltage V₁. Voltage V₁For example, to the potential VPRE. During this period, global bit line GBL and inverted global bit line GBLB are precharged, and then transistors 52_1 and 52_2 are turned off, so that global bit line GBL is electrically insulated from inverted global bit line GBLB (input terminal side) and bit line BL is electrically insulated from inverted bit line BLB (output terminal side). Global bit line GBL and inverted global bit line GBLB are in an electrically floating state.

In fig. 30, the transistor 43 of the memory cell 42 for reading data is turned on to share charge between the capacitor 44 and the local bit line LBL (charge sharing). Potential slave of local bit line LBLPressure 0.5 XV_LBL+V_THUp to a voltage of 0.5 x V_LBL+V_TH+ Δ V. The voltage Δ V is derived from charge transfer of the H-level potential held in the memory cell 42. In the control circuits 35 and 35_ pre, the transistor 33 is turned off, and the potential of the wiring SL is made lower than the precharge voltage V_LBL. Controlling the gate voltage of transistor 31 of circuit 35 by charge sharing up to a voltage of 0.5 x V_LBL+V_TH+ Δ V, so current I_HAnd flows through. On the other hand, in the transistor 31 of the control circuit 35_ pre, the gate voltage is held at a voltage of 0.5 × V_LBL+V_THTherefore, the current flow rate is smaller than that of the control circuit 35. Therefore, the voltage of the global bit line GBL is like the voltage V₁Δ V is decreased as much as that of- Δ V, and the voltage of global bit line GBLB is inverted to voltage V₁。

In fig. 31, the transistors 57_1 and 57_2 are turned on by control of a signal EN 1. In the transistors 58_1 and 58_2, the current I flows in accordance with the voltages of the global bit line GBL and the inverted global bit line GBLB_GBLAnd I_GBLBA difference occurs therebetween. According to current I_GBLAnd I_GBLBThe difference between them generates a potential difference between the bit line BL and the inverted bit line BLB.

In fig. 32, by turning off the transistors 57_1 and 57_2 and supplying a power supply voltage to the wirings SAP and SAN, the sense amplifier included in the control circuit 51A is activated. The bit line BL and the inversion bit line BLB are determined as logic of H level or L level. This logic is logic for inverting the logic read from the memory cell 42.

In fig. 33, the voltages of the global bit line BL and the inverted global bit line BLB determined in the previous period are written back into the memory cell 42 by turning on the transistors 52_1 and 52_2, the transistors 33 and 34, and the transistor 43 included in the memory cell 42.

By adopting the above-described structure, the voltage corresponding to the logic of the data read out by charge sharing can be rewritten back into the memory cell 42 without inverting the logic.

A transistor layer including a memory cell and a control circuit according to one embodiment of the present invention can read data as a signal for correcting the threshold voltage of a reading transistor. With this configuration, the reliability of data read from the memory cell to the first control circuit can be improved. In the semiconductor device according to one embodiment of the present invention, a plurality of switches are arranged between a pair of global bit lines, whereby data can be written into a memory cell again by using the logic of data read from the memory cell.

< example of modification of semiconductor device >

Fig. 34A illustrates a perspective view of the semiconductor device 10 in which the element layers 20_1 to 20_ M illustrated in fig. 1 are arranged on a silicon substrate 50. Fig. 34A shows a vertical direction (z-axis direction), a depth direction (x-axis direction), and a horizontal direction (y-axis direction).

In fig. 34A, the memory cell 42 included in the transistor layers 41_1 and 41_2 is indicated by a dotted line.

As shown in fig. 34A, in a semiconductor device 10 according to one embodiment of the present invention, transistor layers 30 and 40 including an OS transistor are stacked. Therefore, the semiconductor device 10 can be repeatedly manufactured through the same manufacturing process in the vertical direction, and the manufacturing cost can be reduced. In the semiconductor device 10 according to one embodiment of the present invention, the memory density can be increased by arranging the transistor layers 40 including the memory cells 42 not in the planar direction but in the vertical direction in a stacked manner, and the device can be miniaturized.

In fig. 34B, the components included in the element layers 20_1 to 20_ M shown in fig. 34A are omitted, and circuits provided in the silicon substrate 50 are shown. Fig. 34B shows a control logic circuit 61, a row driver circuit 62, a column driver circuit 63, and an output circuit 64, which are formed of Si transistors, in a silicon substrate 50. Embodiment 4 describes the control logic circuit 61, the row driver circuit 62, the column driver circuit 63, and the output circuit 64 in detail.

In fig. 35, the transistor layers 30, 41_1, and 41_2 of the semiconductor device 10 shown in fig. 34A are drawn out. Fig. 35 shows a transistor 43, a capacitor 44, a local bit line LBL, and a word line WL included in the memory cell in the transistor layers 41_1 and 41_ 2. In fig. 35, the local bit lines LBL are indicated by dotted lines for the sake of clarity. In fig. 35, the global bit line GBL provided so as to pass through each transistor layer is illustrated in the z-axis direction. As described above, the global bit line GBL is represented by a line thicker than the other lines for the sake of clarity.

As shown in fig. 35, in the semiconductor device 10, the local bit line LBL connected to the transistor 43 included in the memory cell, the control circuit 35 connected to the transistor layer 30, and the global bit line GBL of the silicon substrate 50 are arranged in the z-axis direction, i.e., in the direction perpendicular to the silicon substrate 50. By adopting this structure, the local bit line LBL connected to each memory cell can be shortened. Therefore, the parasitic capacitance of the local bit line LBL can be significantly reduced, and the potential can be read even if the data signal held by the memory cell is changed into multiple values. In addition, according to one embodiment of the present invention, data held in a memory cell can be read as a current, and thus the data can be easily read even if the current is multi-valued.

Fig. 36A and 36B are circuit diagrams illustrating a modification example of the control circuit 35 shown in fig. 2B. Each transistor shown in fig. 2B is a transistor of a top gate structure or a bottom gate structure without a back gate electrode, but the transistor structure is not limited thereto. For example, as shown in fig. 36A, a control circuit 35B including a back gate electrode connected to a back gate electrode line BGL may be employed. With the structure of fig. 36A, it is easier to control the electrical characteristics such as the threshold voltage of each transistor from the outside.

Alternatively, as shown in fig. 36B, a control circuit 35C including a back gate electrode connected to the gate electrode may be employed. By adopting the structure of fig. 36B, the amount of current flowing through each transistor can be increased.

The case where the semiconductor device 10 of fig. 1 includes one kind of memory cell is described, but the semiconductor device 10 may include two or more kinds of memory cells. Fig. 37A shows a block diagram of a semiconductor device 10A corresponding to a modified example of the semiconductor device 10.

The semiconductor device 10A is different from the semiconductor device 10 in that a transistor layer 90 including memory cells having different circuit structures is provided between the element layer 20 and the transistor layer 30.

Fig. 37B is a circuit diagram showing a configuration example of the memory cell 91 included in the transistor layer 90. The memory cell 91 includes a transistor 92, a transistor 93, and a capacitor 94.

One of a source and a drain of the transistor 92 is connected to a gate of the transistor 93. A gate of the transistor 93 is connected to one electrode of the capacitor 94. The other of the source and the drain of the transistor 92 and one of the source and the drain of the transistor 92 are connected to a wiring BL 2. The other of the source and the drain of the transistor 93 is connected to a wiring SL 2. The other electrode of the capacitor 94 is electrically connected to the wiring CAL. Here, a node at which one of the source and the drain of the transistor 92, the gate of the transistor 93, and one electrode of the capacitor 94 are connected to each other is a node N.

The wiring CAL is used as a wiring for applying a specified potential to the other electrode of the capacitor 94. The potential of the wiring CAL when data is read from the memory cell 91 is made different from the potential of the wiring CAL when data is written into the memory cell 91 and the potential of the wiring CAL when data is held in the memory cell 91. This makes it possible to make the apparent threshold voltage of the transistor 93 when data is read from the memory cell 91 different from the apparent threshold voltage of the transistor 93 when data is written into the memory cell 91 and when data is held in the memory cell 91.

In the case where the memory cell 91 has the structure shown in fig. 37B, when data is written into the memory cell 91 and when data is held in the memory cell 91, current does not flow between the wiring SL2 and the wiring BL2 regardless of the data written into the memory cell 91. On the other hand, when data is read from the memory cell 91, a current corresponding to the data held in the memory cell 91 flows between the wiring SL2 and the wiring BL 2.

The transistors 92, 93 are preferably OS transistors. As described above, the off-state current of the OS transistor is extremely small. Therefore, the electric charge corresponding to the data written in the memory cell 91 can be held in the node N for a long time. In other words, in the memory unit 91, the written data can be held for a long time. Therefore, the frequency of refreshing data can be reduced, and the power consumption of the semiconductor device according to one embodiment of the present invention can be reduced.

The memory cell 91 having the structure shown in fig. 37B may be referred to as a norsram (Nonvolatile Oxide Semiconductor RAM) in which an OS transistor is used for a memory. Norsram has a feature that nondestructive readout can be performed. On the other hand, when the retained data is read by the DOSRAM, a destructive read is performed.

The semiconductor device 10A can write data having a high read frequency from the dorsram into the norsram by including the memory cell 91. As described above, norsram can perform nondestructive readout, and thus the frequency of refreshing data can be reduced. Therefore, power consumption of the semiconductor device according to one embodiment of the present invention can be reduced. Note that although a transistor including one gate is illustrated as the transistor 92 and the transistor 93 shown in fig. 37B, the present invention is not limited to this. For example, one or both of the transistor 92 and the transistor 93 may be a transistor including two gates (a transistor including a front gate and a back gate opposite to the front gate).

Fig. 38A and 38B are schematic diagrams illustrating a modification example of the semiconductor device 10 illustrated in fig. 1.

Fig. 38A illustrates a semiconductor device 10B in which a transistor layer 40 is disposed below a transistor layer 30 among the element layers 20_1 to 20_ M in the semiconductor device 10 illustrated in fig. 1. Semiconductor device 10B shown in fig. 38A includes a transistor layer 49 having transistor layers 49_1 to 49 — k in a lower layer of transistor layer 30. In this configuration, the operation of correcting the threshold voltage of the readout transistor can be realized.

Fig. 38B shows a semiconductor device 10C in which the element layers 20_1 to 20_ M in the semiconductor device 10 shown in fig. 1 include the transistor layer 49 illustrated in fig. 38A in addition to the transistor layer 40. In this configuration, the operation of correcting the threshold voltage of the readout transistor can be performed.

(embodiment mode 2)

An example of a semiconductor device used as a memory device according to one embodiment of the present invention is described below.

Fig. 39 is a diagram showing an example of a semiconductor device in which a memory cell 470 (memory cell 470_1 to memory cell 470_ m: m is a natural number of 2 or more) is provided in a stack over an element layer 411 including a circuit provided over a semiconductor substrate 311. In the example shown in fig. 39, an element layer 411 and a plurality of memory cells 470 on the element layer 411 are stacked, and in each of the plurality of memory cells 470, a transistor layer 413 (transistor layer 413_1 to transistor layer 413_ m) and a plurality of memory device layers 415 on the transistor layers 413 (memory device layers 415_1 to 415_ n: n are natural numbers of 2 or more) are provided. In addition, an example in which the memory device layer 415 is provided on the transistor layer 413 is shown as each memory cell 470, but the present embodiment is not limited thereto. Transistor layer 413 may be disposed on a plurality of memory device layers 415, and memory device layers 415 may be disposed above and below transistor layer 413.

The element layer 411 may include the transistor 300 provided in the semiconductor substrate 311 and be used as a circuit of a semiconductor device (sometimes referred to as a peripheral circuit). Examples of the circuit include a column driver, a row driver, a column decoder, a row decoder, a sense amplifier, a precharge circuit, an amplifier circuit, a word line driver circuit, an output circuit, and a control logic circuit.

Transistor layer 413 may include transistor 200T and be used as circuitry to control each memory cell 470. Memory device layer 415 includes memory devices 420. The memory device 420 shown in this embodiment includes a transistor 200M and a capacitor 292.

The value of m is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less. The value of n is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less. The product of m and n is 4 to 256, preferably 4 to 128, and more preferably 4 to 64.

Fig. 39 is a cross-sectional view of the transistor 200T and the transistor 200M included in the memory cell in the channel length direction.

As shown in fig. 39, a transistor 300 is provided over a semiconductor substrate 311, a transistor layer 413 and a memory device layer 415 included in a memory cell 470 are provided over the transistor 300, a transistor 200T included in the transistor layer 413 and a memory device 420 included in the memory device layer 415 in one memory cell 470 are electrically connected to each other through a plurality of conductors 424, and the transistor 300 and the transistor 200T included in the transistor layer 413 in each memory cell 470 are electrically connected to each other through a conductor 426. The conductor 426 is preferably electrically connected to the transistor 200T through a conductor 428 electrically connected to any one of the source, the drain, and the gate of the transistor 200T. Electrical conductors 424 are preferably disposed in each of the memory device layers 415. Conductor 426 is preferably disposed in each of transistor layer 413 and memory device layer 415.

Further, it is preferable to provide insulators that suppress permeation of impurities such as water and hydrogen and oxygen on the side surfaces of the conductor 424 and the conductor 426, which will be described in detail later. As such an insulator, for example, silicon nitride, aluminum oxide, silicon oxynitride, or the like is preferably used.

The memory device 420 includes a transistor 200M and a capacitor 292, and the transistor 200M has the same structure as the transistor 200T included in the transistor layer 413. The transistors 200T and 200M may be collectively referred to as a transistor 200.

Here, in the transistor 200, a metal oxide used as an oxide semiconductor (hereinafter, sometimes referred to as an oxide semiconductor) is preferably used for a semiconductor including a region where a channel is formed (hereinafter, sometimes referred to as a channel formation region).

For example, as the oxide semiconductor, a metal oxide such as an In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) is preferably used. In addition, indium oxide, an In-Ga oxide, and an In-Zn oxide are preferably used as the oxide semiconductor. Note that by using an oxide semiconductor having a composition with a high indium ratio, on-state current, field-effect mobility, or the like of a transistor can be improved.

Since the leakage current in the non-conductive state of the transistor 200 using an oxide semiconductor for a channel formation region is extremely small, a semiconductor device with low power consumption can be provided. Further, since the oxide semiconductor can be formed by a sputtering method or the like, it can be used for the transistor 200 constituting a highly integrated semiconductor device. The method of forming the oxide semiconductor is not limited to the sputtering method, and for example, an ALD (Atomic Layer Deposition) method may be used.

On the other hand, in a transistor using an oxide semiconductor, since the electrical characteristics thereof vary depending on impurities and oxygen vacancies in the oxide semiconductor, the transistor easily has a normally-on characteristic (this characteristic means that a channel is present and a current flows through the transistor even when a voltage is not applied to a gate electrode).

Thus, an oxide semiconductor in which the impurity concentration and the defect state density are reduced is preferably used. Note that in this specification and the like, a case where the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic.

Therefore, it is preferable to reduce the impurity concentration in the oxide semiconductor as much as possible. Examples of the impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

In particular, hydrogen as an impurity contained in an oxide semiconductor sometimes forms an oxygen vacancy (also referred to as V) in the oxide semiconductor_O: oxygen vacacy). Further, defects in which hydrogen enters oxygen vacancies (hereinafter sometimes referred to as V)_OH) Electrons may be generated as carriers. Further, a part of hydrogen may react with oxygen bonded to a metal atom to generate electrons serving as carriers.

Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen easily has a normally-on characteristic. Further, since hydrogen in the oxide semiconductor is easily moved by heat, an electric field, or the like, when the oxide semiconductor contains a large amount of hydrogen, reliability of the transistor may be lowered.

Accordingly, as an oxide semiconductor used for the transistor 200, a high-purity intrinsic oxide semiconductor in which impurities such as hydrogen and oxygen vacancies are reduced is preferably used.

< sealing Structure >

In order to suppress impurities mixed from the outside, it is preferable to seal the transistor 200 with a material that suppresses diffusion of impurities (hereinafter, also referred to as a material having barrier properties against impurities).

Note that in this specification, the barrier property means a function of suppressing diffusion of a corresponding substance (it can be said that the permeability is low). Alternatively, it refers to a function of capturing and fixing a corresponding substance (also referred to as gettering).

For example, as a material having a function of suppressing diffusion of hydrogen and oxygen, there are aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, and the like. In particular, silicon nitride or silicon oxynitride has a high barrier property against hydrogen and is therefore preferably used as a sealing material.

For example, as a material having a function of trapping and fixing hydrogen, there are metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.

As a layer having barrier properties, an insulator 211, an insulator 212, and an insulator 214 are preferably provided between the transistor 300 and the transistor 200. By using a material that suppresses diffusion or permeation of impurities such as hydrogen for at least one of the insulator 211, the insulator 212, and the insulator 214, impurities such as hydrogen or water included in the semiconductor substrate 311, the transistor 300, and the like can be suppressed from diffusing into the transistor 200. Further, by using a material that suppresses oxygen permeation for at least one of the insulator 211, the insulator 212, and the insulator 214, oxygen contained in the channel of the transistor 200 or the transistor layer 413 can be suppressed from diffusing into the element layer 411. For example, a material that suppresses the transmission of impurities such as hydrogen and water is used for the insulator 211 and the insulator 212, and a material that suppresses the transmission of oxygen is preferably used for the insulator 214. In addition, a material having a property of absorbing and storing hydrogen is preferably used for the insulator 214. For example, a nitride such as silicon nitride or silicon oxynitride can be used for the insulator 211 and the insulator 212. For example, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide can be used as the insulator 214. It is particularly preferable to use alumina as the insulator 214.

Insulator 287 is preferably provided on the side surfaces of transistor layer 413 and memory device layer 415, that is, on the side surface of memory cell 470, and insulator 282 is preferably provided on the top surface of memory cell 470. At this time, the insulator 282 is preferably in contact with the insulator 287, and the insulator 287 is preferably in contact with at least one of the insulator 211, the insulator 212, and the insulator 214. As the insulator 287 and the insulator 282, materials which can be used for the insulator 214 are preferably used.

Further, it is preferable that the insulator 283 and the insulator 284 are provided so as to cover the insulator 282 and the insulator 287, and the insulator 283 is preferably in contact with at least one of the insulator 211, the insulator 212, and the insulator 214. Fig. 39 shows an example in which the insulator 287 is in contact with the side surface of the insulator 214, the side surface of the insulator 212, and the top surface and the side surface of the insulator 211, and the insulator 283 is in contact with the side surface of the insulator 287 and the top surface of the insulator 211, but the present embodiment is not limited thereto. The insulator 287 may be in contact with the side surface of the insulator 214 and the top surface and the side surface of the insulator 212, and the insulator 283 may be in contact with the side surface of the insulator 287 and the top surface of the insulator 212. As the insulator 282 and the insulator 287, materials which can be used for the insulator 211 and the insulator 212 are preferably used.

In the above structure, it is preferable to use a material that suppresses oxygen transmission as the insulator 287 and the insulator 282. Further, as the insulator 287 and the insulator 282, a material having a property of trapping and fixing hydrogen is more preferably used. By using a material having a function of trapping and fixing hydrogen on the side adjacent to the transistor 200, hydrogen in the transistor 200 or the memory cell 470 is trapped and fixed by the insulator 214, the insulator 287, and the insulator 282, and therefore, the hydrogen concentration in the transistor 200 can be reduced. Further, as the insulator 283 and the insulator 284, materials that suppress permeation of impurities such as hydrogen and water are preferably used.

By adopting the above-described structure, the memory cell 470 is surrounded by the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284. Specifically, the memory cell 470 is surrounded by the insulator 214, the insulator 287, and the insulator 282 (which may be referred to as a first structure), and the memory cell 470 and the first structure are surrounded by the insulator 211, the insulator 212, the insulator 283, and the insulator 284 (which may be referred to as a second structure). In this manner, a structure in which the memory cell 470 is surrounded by a plurality of structures of two or more layers is sometimes referred to as a nested structure. Here, the case where the memory cell 470 is surrounded by a plurality of structural bodies is described as a case where the memory cell 470 is sealed by a plurality of insulators.

In addition, the second structure body seals the transistor 200 with the first structure body interposed therebetween. Therefore, the second structure body can suppress diffusion of hydrogen existing outside the second structure body into the second structure body (the transistor 200 side). That is, the first structural body can efficiently trap and fix hydrogen present in the internal structure of the second structural body.

As the above structure, specifically, a metal oxide such as aluminum oxide can be used for the first structure body, and a nitride such as silicon nitride can be used for the second structure body. More specifically, an aluminum oxide film is preferably provided between the transistor 200 and the silicon nitride film.

Further, by appropriately setting the film formation conditions, the hydrogen concentration in the material used for the structure can be reduced.

Generally, the film formed by the CVD method has higher coverage than the film formed by the sputtering method. On the other hand, a compound gas used in the CVD method contains hydrogen in many cases, and therefore the hydrogen content of a film formed by the CVD method is higher than that of a film formed by the sputtering method.

Therefore, for example, a film having a reduced hydrogen concentration (specifically, a film formed by a sputtering method) is preferably used as a film adjacent to the transistor 200. On the other hand, when a film having high covering ability and a high hydrogen concentration in the film (specifically, a film formed by a CVD method) is used as the film for suppressing diffusion of the impurity, a film having a function of trapping and fixing hydrogen and a reduced hydrogen concentration is preferably disposed between the transistor 200 and the film having a high hydrogen concentration and a high covering ability.

That is, as a film disposed adjacent to the transistor 200, a film having a low hydrogen concentration is preferably used. On the other hand, a film having a high hydrogen concentration is preferably disposed separately from the transistor 200.

Specifically, when the transistor 200 is sealed with silicon nitride formed by a CVD method, an aluminum oxide film formed by a sputtering method is preferably provided between the transistor 200 and a silicon nitride film formed by a CVD method. More preferably, a silicon nitride film formed by a sputtering method is disposed between a silicon nitride film formed by a CVD method and an aluminum oxide film formed by a sputtering method.

In addition, when the film formation is performed by the CVD method, the concentration of hydrogen contained in the formed film may be reduced by performing the film formation using a compound gas containing no hydrogen atoms or a small amount of hydrogen atoms.

Further, it is preferable to provide an insulator 282 and an insulator 214 between each transistor layer 413 and the memory device layer 415 or between each memory device layer 415. Further, an insulator 296 is preferably provided between the insulator 282 and the insulator 214. The insulator 296 may be made of the same material as the insulator 283 or the insulator 284. In addition, silicon oxide or silicon oxynitride can be used. In addition, a known insulating material can be used. Here, the insulator 282, the insulator 296, and the insulator 214 may be elements constituting the transistor 200. The insulator 282, the insulator 296, and the insulator 214 also serve as components of the transistor 200, and are preferable because the number of steps required for manufacturing a semiconductor device can be reduced.

In addition, the respective sides of insulator 282, insulator 296, and insulator 214, which are preferably disposed between each transistor layer 413 and memory device layer 415 or between each memory device layer 415, are preferably in contact with insulator 287. By adopting such a structure, the transistor layer 413 and the memory device layer 415 are surrounded and sealed by the insulator 282, the insulator 296, the insulator 214, the insulator 287, the insulator 283, and the insulator 284, respectively.

Further, the insulator 274 may be provided around the insulator 284. The conductor 430 may be formed to be embedded in the insulator 274, the insulator 284, the insulator 283, and the insulator 211. The conductor 430 is electrically connected to the transistor 300, i.e., the circuit included in the element layer 411.

In addition, in the memory device layer 415, the capacitance element 292 is provided in the same layer as the transistor 200M, and therefore the height of the memory device 420 and the height of the transistor 200M can be made the same and thus the height of each memory device layer 415 can be suppressed from being excessively large. Thereby, the number of memory device layers 415 is increased relatively easily. For example, the layers of the transistor layer 413 and the memory device layer 415 may be stacked to be about 100 layers.

< transistor 200>

A transistor 200 that may be used for the transistor 200T included in the transistor layer 413 and the transistor 200M included in the memory device 420 is described with reference to fig. 40A.

As shown in fig. 40A, the transistor 200 includes an insulator 216, a conductor 205 (a conductor 205a and a conductor 205b), an insulator 222, an insulator 224, an oxide 230 (an oxide 230A, an oxide 230b, and an oxide 230c), a conductor 242 (a conductor 242a and a conductor 242b), an oxide 243 (an oxide 243a and an oxide 243b), an insulator 272, an insulator 273, an insulator 250, and a conductor 260 (a conductor 260A and a conductor 260 b).

Further, an insulator 216 and a conductor 205 are provided on the insulator 214, and an insulator 280 and an insulator 282 are provided on the insulator 273. The insulator 214, the insulator 280, and the insulator 282 may be considered to form part of the transistor 200.

The semiconductor device according to one embodiment of the present invention includes a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200 and is used as a plug. Further, an insulator 241 (an insulator 241a and an insulator 241b) may be provided so as to be in contact with a side surface of the conductor 240 used as a plug. Further, the insulator 282 and the conductor 240 are provided with a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the conductor 240 and used as a wiring.

In addition, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the conductors 240a and 240 b. The conductors 240a and 240b may have a laminated structure.

When the conductor 240 has a stacked-layer structure, a conductive material having a function of suppressing permeation of impurities such as water and hydrogen and oxygen is preferably used. For example, tantalum nitride, titanium nitride, ruthenium oxide, or the like is preferably used. Further, a conductive material having a function of suppressing permeation of impurities such as water and hydrogen and oxygen may be used in a single layer or a stacked layer. By using such a conductive material, it is possible to further reduce the mixing of impurities such as water and hydrogen diffused from the insulator 280 and the like into the oxide 230 through the conductors 240a and 240 b. Further, oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240 b.

As the insulator 241 provided so as to be in contact with the side surface of the conductor 240, for example, silicon nitride, aluminum oxide, silicon oxynitride, or the like can be used. Since the insulator 241 is provided so as to be in contact with the insulator 272, the insulator 273, the insulator 280, and the insulator 282, impurities such as water and hydrogen from the insulator 280 and the like can be suppressed from being mixed into the oxide 230 via the conductor 240a and the conductor 240 b. In particular, silicon nitride is preferable because of its high barrier property against hydrogen. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240 b.

The conductive body 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material. The conductor may be formed to be embedded in an opening provided in the insulator.

In transistor 200, electrical conductor 260 is used as a first gate of the transistor, while electrical conductor 205 is used as a second gate of the transistor. The conductors 242a and 242b serve as source and drain electrodes.

The oxide 230 is used as a semiconductor including a channel formation region.

Insulator 250 is used as a first gate insulator. Insulator 222 and insulator 224 are used as second gate insulators.

Here, in the transistor 200 shown in fig. 40A, the conductor 260 is formed in a self-aligned manner with the oxide 230c and the insulator 250 interposed therebetween in the opening portions provided in the insulator 280, the insulator 273, the insulator 272, the conductor 242, and the like.

That is, since the conductor 260 is formed to be fitted into an opening including the insulator 280 and the like through the oxide 230c and the insulator 250, alignment of the conductor 260 is not required in a region between the conductor 242a and the conductor 242 b.

Here, the oxide 230c is preferably provided in an opening formed in the insulator 280 or the like. Accordingly, the insulator 250 and the conductor 260 include a region overlapping the stacked structure of the oxide 230b and the oxide 230a with the oxide 230c interposed therebetween. By adopting this structure, the oxide 230c and the insulator 250 can be formed continuously, and the interface between the oxide 230 and the insulator 250 can be kept clean. Therefore, the influence of the interface scattering on the carrier conduction is reduced, and the transistor 200 can obtain a high-pass current and high-frequency characteristics.

In the transistor 200 shown in fig. 40A, the bottom surface and the side surface of the conductor 260 are in contact with the insulator 250. In addition, the bottom and side surfaces of the insulator 250 are in contact with the oxide 230 c.

In addition, as shown in fig. 40A, the transistor 200 has a structure in which an insulator 282 and an oxide 230c are in direct contact. With this structure, diffusion of oxygen contained in the insulator 280 to the conductor 260 can be suppressed.

Therefore, oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b through the oxide 230c, and oxygen vacancies in the oxide 230a and the oxide 230b can be reduced, thereby improving the electrical characteristics and reliability of the transistor 200.

Next, a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

In the transistor 200, a metal oxide used as an oxide semiconductor (hereinafter, sometimes referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including a channel formation region.

For example, a metal oxide used as an oxide semiconductor has an energy gap of 2eV or more, preferably 2.5eV or more. By using a metal oxide having a wide energy gap, the leakage current (off-state current) in the non-conductive state of the transistor 200 can be made extremely small. By using such a transistor, a semiconductor device with low power consumption can be provided.

Specifically, as the oxide 230, a metal oxide such as an In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. In particular, aluminum, gallium, yttrium or tin can be used as element M. Further, as the oxide 230, an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used.

As shown in fig. 40A, oxide 230 preferably includes oxide 230A on insulator 224, oxide 230b on oxide 230A, and oxide 230c disposed on oxide 230b with at least a portion thereof in contact with a top surface of oxide 230 b. Here, the oxide 230c is preferably provided so that the side surfaces thereof are in contact with the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272, the insulator 273, and the insulator 280.

That is, oxide 230 includes oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230 b. When the oxide 230a is provided under the oxide 230b, diffusion of impurities from a structure formed under the oxide 230a to the oxide 230b can be suppressed. When the oxide 230c is provided over the oxide 230b, diffusion of impurities from a structure formed over the oxide 230c to the oxide 230b can be suppressed.

Note that in the transistor 200, three layers of oxide 230a, oxide 230b, and oxide 230c are stacked over the channel formation region and the vicinity thereof, but the present invention is not limited thereto. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked-layer structure of four or more layers may be provided. For example, the oxide 230c may have a two-layer structure to form a four-layer stacked structure.

The oxide 230 preferably has a stacked structure of a plurality of oxides having different atomic number ratios of metal atoms. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 230a is preferably larger than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 230 b. In addition, the atomic number ratio of the element M with respect to In the metal oxide for the oxide 230a is preferably larger than the atomic number ratio of the element M with respect to In the metal oxide for the oxide 230 b. In addition, the atomic number ratio of In with respect to the element M In the metal oxide used for the oxide 230b is preferably larger than the atomic number ratio of In with respect to the element M In the metal oxide used for the oxide 230 a. In addition, as the oxide 230c, a metal oxide which can be used for the oxide 230a or the oxide 230b can be used.

Specifically, as the oxide 230a, In: ga: 1, Zn: 3: 4[ atomic number ratio ] or a composition in the vicinity thereof or 1: 1: 0.5[ atomic number ratio ] or a composition in the vicinity thereof.

In addition, as the oxide 230b, In: ga: zn is 4: 2: 3[ atomic number ratio ] or a composition in the vicinity thereof or 1: 1: 1[ atomic number ratio ] or a composition in the vicinity thereof. In addition, as the oxide 230b, In: ga: zn is 5: 1: 3[ atomic number ratio ] or a composition In the vicinity thereof or In: ga: 10: 1: 3[ atomic number ratio ] or a composition in the vicinity thereof. In addition, as the oxide 230b, an In — Zn oxide (for example, In: Zn 2: 1[ atomic ratio ] or a composition In the vicinity thereof, In: Zn 5: 1[ atomic ratio ] or a composition In the vicinity thereof, or In: Zn 10: 1[ atomic ratio ] or a composition In the vicinity thereof) may be used. In addition, In oxide may be used as the oxide 230 b.

In addition, as the oxide 230c, In: ga: 1, Zn: 3: 4[ atomic number ratio or composition in the vicinity thereof ], Ga: zn is 2: 1[ atomic number ratio ] or a composition in the vicinity thereof or Ga: zn is 2: 5[ atomic number ratio ] or a composition in the vicinity thereof. In addition, a material which can be used for the oxide 230b is used as the oxide 230c, and is provided in a single layer or a stacked layer. For example, when the oxide 230c has a stacked-layer structure, In: ga: zn is 4: 2: 3[ atomic number ratio ] or a composition In the vicinity thereof and In: ga: 1, Zn: 3: 4[ atomic number ratio ] or a composition in the vicinity thereof, Ga: zn is 2: 1[ atomic number ratio ] or a composition In the vicinity thereof and In: ga: zn is 4: 2: 3[ atomic number ratio ] or a composition in the vicinity thereof, Ga: zn is 2: 5[ atomic number ratio ] or a composition In the vicinity thereof and In: ga: zn is 4: 2: 3[ atomic number ratio ] or a composition In the vicinity thereof, and gallium oxide and In: ga: zn is 4: 2: 3[ atomic number ratio ] or a composition in the vicinity thereof.

Note that the structure of the OS transistor included in the memory cell 42 shown in embodiment mode 1 may be different from the structure of the OS transistor included in the transistor layer 30. For example, as the oxide 230c included In the OS transistor provided In the memory cell 42, In: ga: zn is 4: 2: 3[ atomic number ratio ] or a composition near the same, and In: ga: zn is 5: 1: 3[ atomic number ratio ] or a composition In the vicinity thereof, In: ga: 10: 1: 3[ atomic number ratio ] or a composition In the vicinity thereof, In: 10: 1[ atomic number ratio ] or a composition In the vicinity thereof, In: zn is 5: 1[ atomic number ratio ] or a composition In the vicinity thereof, In: zn is 2: 1[ atomic number ratio ] or a composition in the vicinity thereof.

In addition, in the oxide 230b and the oxide 230c, the on-state current, the field-effect mobility, and the like of the transistor can be increased by increasing the indium ratio in the film, and thus the oxide is preferable. The composition in the vicinity includes a range of ± 30% of a desired atomic number ratio.

In addition, the oxide 230b may have crystallinity. For example, the following CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used. An oxide having crystallinity such as CAAC-OS has a highly crystalline and dense structure with few impurities and defects (oxygen vacancies). Therefore, the source electrode or the drain electrode can be suppressed from extracting oxygen from the oxide 230 b. Further, since oxygen extracted from the oxide 230b can be reduced even by the heat treatment, the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

The conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260. The conductive body 205 is preferably embedded in the insulator 216.

In the case where the conductor 205 is used as a gate electrode, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential supplied to the conductor 205 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductive body 205, Vth of the transistor 200 can be made larger and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced as compared with the case where a negative potential is not applied to the conductor 205.

As shown in fig. 40A, the conductor 205 is preferably larger than the region of the oxide 230 which does not overlap with the conductors 242a and 242 b. Although not shown, the conductive body 205 preferably extends to a region outside the oxide 230a and the oxide 230b in the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap each other with an insulator interposed therebetween outside the side surface of the oxide 230 in the channel width direction. By making the conductive body 205 large, local charging (also referred to as charge accumulation) may be alleviated in a process using plasma in a manufacturing process after the conductive body 205 is formed. However, one embodiment of the present invention is not limited to this. As long as the conductive body 205 overlaps at least the oxide 230 between the conductive bodies 242a and 242 b.

The bottom surface of the conductor 260 in the region where the oxide 230a, the oxide 230b, and the conductor 260 do not overlap with each other is preferably located lower than the bottom surface of the oxide 230b with respect to the bottom surface of the insulator 224.

Although not shown, the conductor 260 serving as a gate electrode has a structure in which the side surfaces and the top surface of the oxide 230b in the channel formation region are covered with the oxide 230c and the insulator 250 in the channel width direction, whereby an electric field generated from the conductor 260 is easily applied to the entire channel formation region formed in the oxide 230 b. Therefore, the on-state current of the transistor 200 can be increased to improve the frequency characteristics. In this specification, a structure of a transistor in which a channel formation region is electrically surrounded by electric fields of the conductor 260 and the conductor 205 is referred to as a "surrounded channel (S-channel) structure".

The conductor 205a is preferably a conductor that suppresses permeation of impurities such as water and hydrogen and oxygen. For example, titanium nitride, tantalum, or tantalum nitride may be used. In addition, the conductive body 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205 has a two-layer structure, the conductor 205 may have a multilayer structure of three or more layers.

Here, it is preferable that different types of films be formed continuously without exposure to the air as the oxide semiconductor, the insulator or the conductor located in the lower layer of the oxide semiconductor, and the insulator or the conductor located in the upper layer of the oxide semiconductor, whereby an oxide semiconductor film having substantially high purity and intrinsic in which the concentration of impurities (particularly, hydrogen and water) is reduced can be formed.

At least one of the insulator 222, the insulator 272, and the insulator 273 is preferably used as a barrier insulating film which suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, it is preferable to use a material having a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N) suppressed as at least one of the insulator 222, the insulator 272, and the insulator 273₂O、NO、NO₂Etc.), copper atoms, etc., and functions to diffuse impurities such as copper atoms (the impurities are not easily permeated). Further, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (which is less likely to allow the oxygen to permeate).

For example, silicon nitride, silicon oxynitride, or the like is preferably used for the insulator 273, and aluminum oxide, hafnium oxide, or the like is preferably used for the insulator 222 and the insulator 272.

This can prevent impurities such as water and hydrogen from diffusing into the transistor 200 through the insulator 222. Alternatively, diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 222 can be suppressed.

Further, diffusion of impurities such as water and hydrogen from the insulator 280 and the like disposed through the insulator 272 and the insulator 273 toward the transistor 200 can be suppressed. In this manner, it is preferable that the transistor 200 be surrounded by the insulator 272 and the insulator 273, which have a function of suppressing diffusion of impurities such as water and hydrogen and oxygen.

Here, the insulator 224 in contact with the oxide 230 is preferably heated to release oxygen. In this specification, oxygen desorbed by heating is sometimes referred to as excess oxygen. For example, silicon oxide, silicon oxynitride, or the like can be used as the insulator 224. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, and thus the reliability of the transistor 200 can be improved.

Specifically, as the insulator 224, an oxide material in which part of oxygen is desorbed by heating is preferably used. The oxide in which oxygen is desorbed by heating means that the amount of desorbed oxygen molecules in thermal Desorption spectroscopy (TDS (thermal Desorption spectroscopy)) analysis is 1.0X 10¹⁸molecules/cm³Above, preferably 1.0X 10¹⁹molecules/cm³The above is more preferably 2.0 × 10¹⁹molecules/cm³Above, or 3.0 × 10²⁰molecules/cm³The above oxide film. The surface temperature of the membrane when TDS analysis is performed is preferably in the range of 100 ℃ to 700 ℃ or more, or 100 ℃ to 400 ℃ or less.

The insulator 222 is preferably used as a barrier insulating film which suppresses impurities such as water and hydrogen from entering the transistor 200 from the substrate side. For example, insulator 222 preferably has a lower hydrogen permeability than insulator 224. By surrounding the insulator 224, the oxide 230, and the like with the insulator 222 and the insulator 283, impurities such as water and hydrogen can be suppressed from entering the transistor 200 from the outside.

Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (the oxygen is not easily permeated). For example, insulator 222 preferably has a lower oxygen permeability than insulator 224. It is preferable that the insulator 222 has a function of suppressing diffusion of oxygen or impurities, because diffusion of oxygen contained in the oxide 230 to the lower side of the insulator 222 can be reduced. Further, the reaction of the conductor 205 with oxygen contained in the insulator 224 and the oxide 230 can be suppressed.

As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used as an insulating material. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 222 is formed using such a material, the insulator 222 is used as a layer which suppresses release of oxygen from the oxide 230 or entry of impurities such as hydrogen into the oxide 230 from the peripheral portion of the transistor 200.

Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, the insulator may be subjected to nitriding treatment. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

Further, as the insulator 222, for example, a single layer or a stacked layer including aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO) may be used₃) Or (Ba, Sr) TiO₃(BST) and the like. For example, when the insulator 222 is a laminate, a laminate in which three layers of zirconia, alumina, and zirconia are formed in this order, a laminate in which four layers of zirconia, alumina, zirconia, and alumina are formed in this order, or the like may be used. Further, as the insulator 222, a compound containing hafnium, zirconium, or the like can be used. In the case of miniaturization and high integration of a semiconductor device, there is a case where a problem such as a leakage current of a transistor or a capacitor occurs due to a reduction in thickness of a dielectric used for a gate insulator or a capacitor. By using a high-k material as an insulator used as a dielectric for a gate insulator and a capacitor element, a gate potential during operation of a transistor can be reduced while maintaining a physical thickness, and a capacitance of the capacitor element can be secured.

The insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to the stacked structure formed of the same material, and may be formed of different materials.

Further, an oxide 243 (an oxide 243a and an oxide 243b) may be provided between the oxide 230b and the conductor 242 (the conductor 242a and the conductor 242b) serving as the source electrode or the drain electrode. Since the conductive body 242 is not in contact with the oxide 230b, the conductive body 242 can be suppressed from absorbing oxygen of the oxide 230 b. That is, by preventing the oxidation of the conductor 242, the decrease in the conductivity of the conductor 242 can be suppressed. Therefore, the oxide 243 preferably has a function of suppressing oxidation of the conductor 242.

When the oxide 243 having a function of suppressing oxygen permeation is disposed between the conductor 242 serving as the source electrode or the drain electrode and the oxide 230b, the resistance between the conductor 242 and the oxide 230b is preferably decreased. With such a structure, the electric characteristics of the transistor 200 and the reliability of the transistor 200 can be improved.

As the oxide 243, a metal oxide having one or more elements M selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like can also be used. In particular, aluminum, gallium, yttrium or tin is preferably used as the element M. The concentration of the element M in the oxide 243 is preferably higher than that of the oxide 230 b. In addition, gallium oxide can also be used as the oxide 243. Further, as the oxide 243, a metal oxide such as In-M-Zn oxide can be used. Specifically, the atomic number ratio of the element M with respect to In the metal oxide for the oxide 243 is preferably larger than the atomic number ratio of the element M with respect to In the metal oxide for the oxide 230 b. The thickness of the oxide 243 is preferably 0.5nm or more and 5nm or less, and preferably 1nm or more and 3nm or less. In addition, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, oxygen in the oxide 230 can be more effectively suppressed from being released. For example, when the oxide 243 has a crystal structure of hexagonal crystal or the like, oxygen in the oxide 230 can be suppressed from being released in some cases.

In addition, the oxide 243 is not necessarily provided. In this case, the conductor 242 (the conductor 242a and the conductor 242b) may be oxidized because the conductor 242 contacts the oxide 230 and oxygen in the oxide 230 diffuses into the conductor 242. The possibility that the conductivity of the conductor 242 decreases due to oxidation becomes high. Note that the diffusion of oxygen in the oxide 230 to the conductor 242 may be referred to as the absorption of oxygen in the oxide 230 by the conductor 242.

Further, when oxygen in the oxide 230 diffuses into the conductor 242 (the conductor 242a and the conductor 242b), another layer may be formed between the conductor 242a and the oxide 230b and between the conductor 242b and the oxide 230 b. Since the other layer contains more oxygen than the conductor 242, the other layer is assumed to have insulating properties. In this case, the three-layer structure of the conductor 242, the other layer, and the oxide 230b may be a three-layer structure composed of a Metal-Insulator-Semiconductor, and may be referred to as a MIS (Metal-Insulator-Semiconductor) structure or a diode structure mainly including a MIS structure.

Note that the above-described another layer is not limited to being formed between the conductor 242 and the oxide 230b, and for example, another layer may be formed between the conductor 242 and the oxide 230c or between the conductor 242 and the oxide 230b and between the conductor 242 and the oxide 230 c.

Conductors 242 (conductors 242a and 242b) serving as source and drain electrodes are provided over the oxide 243. The thickness of the conductor 242 may be, for example, 1nm to 50nm, and preferably 2nm to 25 nm.

As the conductor 242, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, an alloy combining the above metal elements, or the like is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity.

An insulator 272 is provided in contact with the top surface of the conductive body 242, and the insulator 272 preferably serves as a barrier. With this structure, the conductor 242 can be prevented from absorbing the excess oxygen contained in the insulator 280. Further, by suppressing oxidation of the conductor 242, increase in contact resistance between the transistor 200 and the wiring can be suppressed. This can provide the transistor 200 with excellent electrical characteristics and reliability.

Therefore, the insulator 272 preferably has a function of suppressing oxygen diffusion. For example, the insulator 272 preferably has a function of further suppressing oxygen diffusion as compared with the insulator 280. As the insulator 272, for example, an insulator containing an oxide of one or both of aluminum and hafnium is preferably formed. Further, as the insulator 272, for example, an insulator containing aluminum nitride can be used.

The insulator 272 contacts a part of the top surface of the conductor 242b and the side surface of the conductor 242 b. Although not shown, the insulator 272 is in contact with a part of the top surface of the conductor 242a and the side surface of the conductor 242 a. Further, an insulator 273 is disposed on the insulator 272. By adopting this structure, for example, oxygen added to the insulator 280 can be suppressed from being absorbed by the conductive body 242.

Insulator 250 is used as a gate insulator. Insulator 250 is preferably disposed in contact with the top surface of oxide 230 c. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability.

As the insulator 224, the insulator 250 is preferably formed using an insulator which releases oxygen by heating. By providing an insulator that releases oxygen by heat addition as the insulator 250 so as to be in contact with the top surface of the oxide 230c, oxygen can be efficiently supplied to the channel formation region of the oxide 230 b. Similarly to the insulator 224, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 250. The thickness of the insulator 250 is preferably 1nm or more and 20nm or less.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably inhibits oxygen diffusion from the insulator 250 to the electrical conductor 260. By providing a metal oxide that suppresses diffusion of oxygen, diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, the oxidation of the conductive body 260 due to oxygen in the insulator 250 can be suppressed.

In addition, the metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, a metal oxide which is a high-k material having a high relative dielectric constant is preferably used as the metal oxide. By providing the gate insulator with a stacked structure of the insulator 250 and the metal oxide, a stacked structure having thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied at the time of the transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the Equivalent Oxide Thickness (EOT) of the insulator used as the gate insulator can be reduced.

Specifically, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like are preferably used as insulators containing an oxide of one or both of aluminum and hafnium.

Alternatively, the metal oxide is sometimes used as part of the gate. In this case, it is preferable that a conductive material containing oxygen be provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

In particular, as a conductor used for a gate electrode, a conductive material containing a metal element contained in a metal oxide forming a channel and oxygen is preferably used. In addition, a conductive material containing the metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon is added can be used. In addition, indium gallium zinc oxide containing nitrogen may also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel may be trapped. Alternatively, hydrogen mixed from an external insulator or the like may be trapped.

Although the electric conductor 260 has a two-layer structure in fig. 40A, it may have a single-layer structure or a stacked-layer structure of three or more layers.

The conductor 260a is preferably a conductor having a function of suppressing hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N)₂O、NO、NO₂Etc.), copper atoms, etc. In addition, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like).

Further, when the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b by oxygen contained in the insulator 250. As the conductive material having a function of suppressing oxygen diffusion, for example, tantalum nitride, ruthenium oxide, or the like is preferably used.

In addition, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used for the conductor 260 b. Further, since the conductor 260 is also used as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-described conductive material.

< Metal oxide > <

As the oxide 230, a metal oxide used as an oxide semiconductor is preferably used. Hereinafter, a metal oxide that can be used for the oxide 230 according to the present invention will be explained.

The metal oxide preferably contains at least indium or zinc. Particularly preferably indium and zinc. In addition, gallium, yttrium, tin, and the like are preferably contained. Alternatively, one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained.

Here, it is estimated that the metal oxide is a case of an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In particular, aluminum, gallium, yttrium or tin can be used as element M.

Note that in this specification and the like, a metal oxide containing nitrogen is also sometimes referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

< transistor 300>

The transistor 300 is described with reference to fig. 40B. The transistor 300 is provided on a semiconductor substrate 311, and includes: a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, and a semiconductor region 313 formed of a part of the semiconductor substrate 311; and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be of a p-channel type or an n-channel type.

Here, in the transistor 300 shown in fig. 40B, the semiconductor region 313 (a part of the semiconductor substrate 311) where the channel is formed has a convex shape. Although not shown, the conductor 316 is provided so as to cover the side surfaces and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween. In addition, a material for adjusting the work function can be used for the conductive body 316. Such a transistor 300 is also referred to as a FIN type transistor because a convex portion of the semiconductor substrate 311 is used. Further, the insulator may have a mask for forming the convex portion so as to be in contact with the upper surface of the convex portion. Although the case where the convex portion is formed by processing a part of the semiconductor substrate 311 is described here, a semiconductor film having a convex portion may be formed by processing an SOI substrate.

Note that the structure of the transistor 300 shown in fig. 40B is merely an example, and is not limited to the above structure, and an appropriate transistor may be used depending on a circuit structure or a driving method.

< memory device 420>

Next, the memory device 420 shown in fig. 39 is explained using fig. 41A. Note that the transistor 200M included in the memory device 420 is not described in a manner overlapping with the transistor 200.

In the memory device 420, the conductor 242a of the transistor 200M is used as one of the electrodes of the capacitor element 292, and the insulators 272 and 273 are used as dielectrics. The conductor 290 is provided so as to overlap the conductor 242a with the insulator 272 and the insulator 273 interposed therebetween, and the conductor 290 is used as the other of the electrodes of the capacitor element 292. Conductor 290 may also be used as another of the electrodes of capacitive element 292 included in an adjacent memory device 420. In addition, the conductive body 290 may be electrically connected to the conductive body 290 included in the adjacent memory device 420.

The conductor 290 is disposed on the top surface of the conductor 242a and the side surface of the conductor 242a with the insulator 272 and the insulator 273 interposed therebetween. In this case, the capacitance element 292 is preferable because a larger capacitance can be obtained than a capacitance obtained by an area where the conductor 242a and the conductor 290 overlap each other.

Conductor 424 is electrically connected to conductor 242b, and is electrically connected to conductor 424 of a layer located below via conductor 205.

As a dielectric of the capacitor element 292, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or the like can be used. In addition, a stack of these materials may be used. In the case where the dielectric of the capacitor element 292 has a stacked-layer structure, a stacked layer of aluminum oxide and silicon nitride, and a stacked layer of hafnium oxide and silicon oxide can be used. Here, the upper and lower layers of the laminate are not limited. For example, silicon nitride may be stacked on alumina, or alumina may be stacked on silicon nitride.

As the dielectric of the capacitor element 292, zirconia having a higher dielectric constant than the above-described materials can be used. As the dielectric of the capacitor element 292, zirconia may be used as a single layer or as part of a stack. For example, a laminate of zirconia and alumina may be used. In addition, a stack of three layers, zirconia as the first layer and the third layer, and alumina as the second layer between the first layer and the third layer may be used as the dielectric of the capacitor element 292.

By using zirconia having a high dielectric constant as the dielectric of the capacitance element 292, the area occupied by the capacitance element 292 in the memory device 420 can be reduced. Therefore, the area required for the memory device 420 can be reduced, and thus the bit cost (bit cost) can be increased, which is preferable.

As the conductor 290, a material usable for the conductors 205, 242, 260, 424, and the like can be used.

In this embodiment, an example is shown in which the transistor 200M and the capacitor element 292 are symmetrically arranged with the conductor 424 interposed therebetween. By disposing the pair of transistors 200M and the capacitor element 292 in this manner, the number of conductors 424 electrically connected to the transistors 200M can be reduced. Therefore, the area required for the memory device 420 can be reduced, and thus the bit cost can be increased, which is preferable.

When the insulator 241 is provided on the side surface of the conductor 424, the conductor 424 is connected to at least a part of the top surface of the conductor 242 b.

The transistor 200T in the memory cell 470 can be electrically connected to the memory device 420 by using the conductor 424 and the conductor 205.

< modification example 1 of memory device 420>

Next, the memory device 420A is explained as a modified example of the memory device 420 with reference to fig. 41B. In addition to the transistor 200M illustrated in fig. 41A, the memory device 420A includes a capacitive element 292A electrically connected to the transistor 200M. The capacitor element 292A is provided below the transistor 200M.

In the memory device 420A, the conductor 242a is disposed in an opening formed in the oxide 243a, the oxide 230b, the oxide 230A, the insulator 224, and the insulator 222, and is electrically connected to the conductor 205 at the bottom of the opening. Conductor 205 is electrically connected to capacitive element 292A.

The capacitor element 292A includes a conductor 294 used as one of electrodes, an insulator 295 used as a dielectric, and a conductor 297 used as the other of the electrodes. The conductor 297 overlaps the conductor 294 via the insulator 295. Further, the conductor 297 is electrically connected to the conductor 205.

Conductors 294 are disposed at the bottom and side surfaces of an opening formed in an insulator 298 provided on an insulator 296, and an insulator 295 is provided so as to cover the insulator 298 and the conductors 294. The conductor 297 is formed to be fitted into a recess provided in the insulator 295.

Further, a conductor 299 is formed to be embedded in the insulator 296, and the conductor 299 is electrically connected to the conductor 294. Conductor 299 may also be electrically connected to conductor 294 of an adjacent memory device 420A.

Conductor 297 is disposed on the top surface of conductor 294 and the side surface of conductor 294 with insulator 295 interposed therebetween. In this case, the capacitor element 292A is preferable because a larger capacitance can be obtained than a capacitance obtained by an area where the conductor 294 and the conductor 297 overlap each other.

As the insulator 295 used as a dielectric of the capacitor element 292A, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or the like can be used. In addition, a stack of these materials may be used. In the case where the insulator 295 has a stacked-layer structure, a stacked layer of aluminum oxide and silicon nitride, a stacked layer of hafnium oxide and silicon oxide can be used. Here, the upper and lower layers of the laminate are not limited. For example, silicon nitride may be stacked on alumina, or alumina may be stacked on silicon nitride.

In addition, as the insulator 295, zirconia having a higher dielectric constant than the above-described materials can be used. As the insulator 295, either single-layer zirconia or zirconia may be used as part of a stack. For example, a laminate of zirconia and alumina may be used. In addition, a stack of three layers, zirconia as a first layer and a third layer, and alumina as a second layer between the first layer and the third layer can be used as the insulator 295.

By using zirconia having a high dielectric constant as the insulator 295, the area occupied by the capacitor element 292A in the memory device 420A can be reduced. Therefore, the area required for the memory device 420A can be reduced, and thus the bit cost can be increased, which is preferable.

As the conductors 297, 294, and 299, materials usable for the conductors 205, 242, 260, and 424 can be used.

As the insulator 298, materials usable for the insulators 214, 216, 224, 280, and the like can be used.

< modification example 2 of memory device 420>

Next, a memory device 420B is explained as a modified example of the memory device 420 with reference to fig. 41C. In addition to the transistor 200M illustrated in fig. 41A, the memory device 420B includes a capacitive element 292B electrically connected to the transistor 200M. The capacitor element 292B is provided above the transistor 200M.

The capacitive element 292B includes a conductor 276 used as one of the electrodes, an insulator 277 used as a dielectric, and a conductor 278 used as the other of the electrodes. The conductor 278 overlaps the conductor 276 with the insulator 277 interposed therebetween.

An insulator 275 is provided on the insulator 282, and conductors 276 are provided on the bottom and side surfaces of openings formed in the insulator 275, the insulator 282, the insulator 280, the insulator 273, and the insulator 272. The insulator 277 is provided so as to cover the insulator 282 and the conductor 276. The conductor 278 is provided so as to overlap the conductor 276 in the recess of the insulator 277, and at least a part of the conductor 278 is provided on the insulator 275 via the insulator 277. The conductive body 278 may also be used as the other of the electrodes of the capacitive element 292B included in the adjacent memory device 420B. The conductor 278 may be electrically connected to the conductor 278 included in the adjacent memory device 420B.

The conductor 278 is disposed on the top surface of the conductor 276 and the side surface of the conductor 276 with the insulator 277 interposed therebetween. In this case, the capacitance element 292B is preferable because it can obtain a larger capacitance than the capacitance obtained by the area where the conductor 276 and the conductor 278 overlap.

The insulator 279 may be formed to be fitted into a recess provided in the conductor 278.

As the insulator 277 used as a dielectric of the capacitor element 292B, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or the like can be used. In addition, a stack of these materials may be used. In the case where the insulator 277 has a stacked-layer structure, a stacked layer of aluminum oxide and silicon nitride, a stacked layer of hafnium oxide and silicon oxide may be used. Here, the upper and lower layers of the laminate are not limited. For example, silicon nitride may be stacked on alumina, or alumina may be stacked on silicon nitride.

In addition, as the insulator 277, zirconia having a higher dielectric constant than the above-described materials can be used. As the insulator 277, zirconia may be used as a single layer or as part of a stack. For example, a laminate of zirconia and alumina may be used. Further, a stack of three layers, zirconia as the first layer and the third layer, and alumina as the second layer between the first layer and the third layer may be used as the insulator 277.

By using zirconia having a high dielectric constant as the insulator 277, the area occupied by the capacitive element 292B in the memory device 420B can be reduced. Therefore, the area required for the memory device 420B can be reduced, and thus the bit cost can be increased.

As the conductors 276 and 278, materials usable for the conductors 205, 242, 260, 424, and the like can be used.

As the insulators 275 and 279, materials that can be used for the insulators 214, 216, 224, 280, and the like can be used.

< connection of memory device 420 and transistor 200T >

In a region 422 surrounded by a chain line in fig. 39, the memory device 420 is electrically connected to the gate of the transistor 200T via the conductor 424 and the conductor 205, but the present embodiment is not limited thereto.

Fig. 42 shows an example in which the memory device 420 is electrically connected to the conductor 242b serving as one of the source and the drain of the transistor 200T via the conductor 424, the conductor 205, the conductor 246b, and the conductor 240 b.

Thus, the connection method of the memory device 420 and the transistor 200T may be determined according to the function of a circuit included in the transistor layer 413.

Fig. 43 shows an example in which the memory cell 470 includes a transistor layer 413 having the transistor 200T and a memory device layer 415 (memory device layer 415_1 to memory device layer 415_4) of four layers.

Each of the memory device layers 415_1 through 415_4 includes a plurality of memory devices 420.

The memory device 420 is electrically connected to the memory device 420 included in the different memory device layers 415 and the transistor 200T included in the transistor layer 413 through the conductor 424 and the conductor 205.

Memory cell 470 is sealed by insulator 211, insulator 212, insulator 214, insulator 287, insulator 282, insulator 283, and insulator 284. An insulator 274 is disposed around the insulator 284. The insulators 274, 284, 283, and 211 are provided with conductors 430 and electrically connected to the element layer 411.

Further, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen due to heat. In addition, the insulator 280 has an excess oxygen region.

The insulators 211, 283, and 284 are preferably made of a material having a high barrier property against hydrogen. In addition, the insulator 214, the insulator 282, and the insulator 287 are preferably materials that trap hydrogen or fix hydrogen.

Examples of the material having a high barrier property against hydrogen include silicon nitride, silicon oxynitride, and the like. Examples of the material for trapping hydrogen or fixing hydrogen include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate).

Note that in this specification, the barrier property means a function of suppressing diffusion of a corresponding substance (it can be said that the permeability is low). Alternatively, it refers to a function of capturing and fixing a corresponding substance (also referred to as gettering).

The crystal structure of the materials used for the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284 is not particularly limited, and a structure having amorphous or crystalline properties may be employed. For example, as a material for trapping hydrogen or fixing hydrogen, an amorphous aluminum oxide film is preferably used. Amorphous alumina sometimes traps and fixes a larger amount of hydrogen than alumina having high crystallinity.

Here, as a model of diffusion of excess oxygen in the insulator 280 to hydrogen in the oxide semiconductor in contact with the insulator 280, the following can be predicted.

Hydrogen existing in the oxide semiconductor diffuses to other structural bodies through the insulator 280 in contact with the oxide semiconductor. The excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to become OH bonds, and the hydrogen diffuses into the insulator 280. When a hydrogen atom having OH bonding reaches a material (typically the insulator 282) that traps hydrogen or fixes hydrogen, the hydrogen atom reacts with an oxygen atom bonded to an atom (e.g., a metal atom or the like) in the insulator 282 and is trapped or fixed in the insulator 282. On the other hand, oxygen atoms having OH-bonded excess oxygen are estimated to remain in the insulator 280 as excess oxygen. In other words, the possibility that the excess oxygen in the insulator 280 acts as a bridge upon diffusion of hydrogen is high.

One of the important elements for satisfying the above model is a manufacturing process of a semiconductor device.

As an example, the insulator 282 is formed after the oxide semiconductor is formed to form the insulator 280 containing excess oxygen. Then, heat treatment is preferably performed. Specifically, the heat treatment is performed at a temperature of 350 ℃ or higher, preferably 400 ℃ or higher, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen. The time of the heat treatment is 1 hour or more, preferably 4 hours or more, and more preferably 8 hours or more.

By the above heat treatment, hydrogen in the oxide semiconductor can be diffused to the outside through the insulator 280, the insulator 282, and the insulator 287. In other words, the absolute amount of hydrogen present in the oxide semiconductor and the vicinity of the oxide semiconductor can be reduced.

After the above-described heating treatment, the insulator 283 and the insulator 284 are formed. Since the insulators 283 and 284 are materials having high barrier properties against hydrogen, intrusion of hydrogen diffused to the outside or hydrogen existing outside into the inside, specifically, the oxide semiconductor or the insulator 280 side can be suppressed.

Note that although an example in which the heating treatment is performed after the insulator 282 is formed is shown with respect to the above-described heating treatment, it is not limited thereto. For example, the above-described heating process may be performed after the transistor layer 413 is formed or after the memory device layers 415_1 to 415_3 are formed, respectively. Further, when hydrogen is diffused to the outside by the above-described heating treatment, hydrogen is diffused to the upper side or the lateral direction of the transistor layer 413. Similarly, when the heat treatment is performed after the formation of the memory device layers 415_1 to 415_3, hydrogen diffuses in the upward or lateral direction.

Further, by adopting the above-described manufacturing process, the above-described sealing structure formed by bonding the insulator 211 and the insulator 283 together is formed.

As described above, by adopting the above-described structure and the above-described manufacturing process, a semiconductor device using an oxide semiconductor with a reduced hydrogen concentration can be provided. Therefore, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided.

Fig. 44A to 44C are diagrams showing examples of different configurations of the conductive body 424. Fig. 44A shows a layout view of the memory device 420 when viewed from the top surface, fig. 44B shows a cross-sectional view of a portion indicated by a chain line a1-a2 in fig. 44A, and fig. 44C shows a cross-sectional view of a portion indicated by a chain line B1-B2 in fig. 44A. In fig. 44A, the conductor 205 is omitted for clarity. When the conductor 205 is provided, the conductor 205 includes a region overlapping with the conductors 260 and 424.

As shown in fig. 44A, the opening provided with the conductor 424, that is, the conductor 424 is provided outside the oxide 230a and the oxide 230b, in addition to the region overlapping with the oxide 230a and the oxide 230 b. Fig. 44A shows an example in which the conductor 424 is provided so as to protrude to the B2 side of the oxide 230a and the oxide 230B, but the present embodiment is not limited to this. The conductor 424 may be provided so as to protrude to the B1 side of the oxide 230a and the oxide 230B, or may be provided so as to protrude to both the B1 side and the B2 side.

Fig. 44B and 44C show an example in which the memory device layer 415_ p is stacked on the memory device layer 415_ p-1 (p is a natural number of 2 or more and n or less). The memory device 420 included in the memory device layer 415_ p-1 is electrically connected to the memory device 420 included in the memory device layer 415_ p through the conductor 424 and the conductor 205.

FIG. 44B shows the case where conductor 424 in memory device layer 415_ p-1 is connected to conductor 242 in memory device layer 415_ p-1 and conductor 205 in memory device layer 415_ p. The conductor 424 is connected to the conductor 205 of the memory device layer 415_ p-1 outside the B2 side of the conductors 242, 243, 230B, and 230 a.

In fig. 44C, the conductor 424 is formed along the B2-side surfaces of the conductor 242, the oxide 243, the oxide 230B, and the oxide 230a, and is electrically connected to the conductor 205 through the openings formed in the insulators 280, 273, 272, 224, and 222. Here, in fig. 44B, a case where the conductor 424 is formed along the side surface on the B2 side of the conductor 242, the oxide 243, the oxide 230B, and the oxide 230a is shown by a broken line. Further, an insulator 241 may be formed between the conductor 242, the oxide 243, the oxide 230B, the oxide 230a, the insulator 224, and the B2-side surface of the insulator 222 and the conductor 424.

By providing the conductor 424 also in a region not overlapping with the conductor 242 or the like, the memory device 420 can be electrically connected to the memory device 420 provided in a different memory device layer 415. In addition, the memory device 420 may be electrically connected to the transistor 200T provided in the transistor layer 413.

When the conductor 424 is used as a bit line, the conductor 424 is provided in a region not overlapping with the conductor 242 or the like, whereby the distance between the bit lines of the memory devices 420 adjacent to each other in the B1-B2 direction can be increased. As shown in fig. 44, the distance between the conductors 424 on the conductor 242 is d1, but the distance between the conductors 424 in the opening formed by the insulator 224 and the insulator 222, which is the layer below the oxide 230a, is d2, so d2 is larger than d 1. By setting the distance of a part to d2, the parasitic capacitance of the conductor 424 can be reduced as compared with the case where the distance between the conductors 424 adjacent in the B1-B2 direction is d 1. It is preferable to reduce the capacitance required for the capacitance element 292 by reducing the parasitic capacitance of the conductive body 424.

A conductor 424 is provided in the memory device 420 that is used as a common bit line for both memory cells. The cell size of each memory cell can be reduced by appropriately adjusting the dielectric constant of the dielectric used for the capacitor element or the parasitic capacitance between the bit lines. Here, the estimation of the cell size, the estimation of the bit density, and the estimation of the bit cost of the memory cell when the channel length is 30nm (also referred to as a 30nm node) will be described. In fig. 45A to 45D to be described below, the conductor 205 is omitted for clarity. When the conductor 205 is provided, the conductor 205 includes a region overlapping with the conductors 260 and 424.

Fig. 45A shows an example in which hafnium oxide having a thickness of 10nm and silicon oxide having a thickness of 1nm above the hafnium oxide are stacked as a dielectric of a capacitor, a slit is formed between a conductor 242, an oxide 243, an oxide 230a, and an oxide 230b of each memory cell included in a memory device 420, and a conductor 424 serving as a bit line is provided so as to overlap the conductor 242 and the slit. The memory cell 432 obtained in this way is referred to as a cell a.

Cell size in cell A is 45.25F²。

Fig. 45B shows an example in which a first zirconia, an alumina thereon, and a second zirconia thereon are stacked as a dielectric of a capacitor, slits are formed between a conductor 242, an oxide 243, an oxide 230a, and an oxide 230B of each memory cell included in a memory device 420, and a conductor 424 serving as a bit line is provided so as to overlap the conductor 242 and the slits. The memory cell 433 obtained in this way is referred to as a cell B.

Since the dielectric constant of the dielectric serving as the capacitor element in the cell B is higher than that in the cell a, the area of the capacitor element can be reduced. Therefore, in the cell B, the cell size can be reduced as compared with the cell a. Cell size in cell B25.53F²。

The cell a and the cell B correspond to memory cells included in the memory device 420, the memory device 420A, or the memory device 420B shown in fig. 39, fig. 41A to fig. 41C, and fig. 42.

Fig. 45C shows an example in which a first zirconia, an alumina thereon, and a second zirconia thereon are stacked in this order as a dielectric of a capacitor element, and each memory cell has a conductor 242, an oxide 243, an oxide 230a, and an oxide 230b which are included in a memory device 420 in common, and a conductor 424 serving as a bit line is provided so that a part overlapping the conductor 242 and a part outside the conductor 242 overlap each other. The memory cell 434 obtained in this way is referred to as a cell C.

The distance between conductors 424 in cell C is greater in a layer below oxide 230a than above conductor 242. Therefore, the parasitic capacitance of the conductor 424 can be reduced, and the area of the capacitor element can be reduced. Further, no slit is formed in the conductor 242, the oxide 243, the oxide 230a, and the oxide 230 b. Thus, the cell C can be reduced in cell size as compared with the cells a and B. Cell size in cell C is 17.20F²。

Fig. 45D shows an example in which the conductor 205 and the insulator 216 are not provided in the cell C. Such a storage unit 435 is referred to as unit D.

By not providing the conductor 205 and the insulator 216 in the cell D, the thickness of the memory device 420 can be reduced. Accordingly, the memory device layer 415 including the memory device 420 can be thinned, and the height of the memory cell 470 in which a plurality of memory device layers 415 are stacked can be reduced. When the conductor 424 and the conductor 205 are regarded as bit lines, the bit lines can be shortened in the memory cell 470. The bit line can be shortened, the parasitic load on the bit line can be reduced, and the parasitic capacitance of the conductor 424 can be further reduced, thereby reducing the size of the memory cellArea of the capacitive element. Further, no slit is formed in the conductor 242, the oxide 243, the oxide 230a, and the oxide 230 b. Thus, the cell D can be reduced in cell size as compared with the cells a, B, and C. Cell size in cell D is 15.12F²。

The cell C and the cell D correspond to memory cells included in the memory device 420 shown in fig. 44A to 44C.

Here, the bit density and bit cost C of the units A to D and the unit E in the unit D for multi-valued estimation are estimated_b. In addition, the resulting estimates are compared to estimates of bit density and bit cost in currently commercially available DRAMs.

Estimation of bit cost C in a semiconductor device according to one embodiment of the present invention by equation 1_b。

[ equation 1]

Where n denotes the number of stacked memory device layers, P_cThe number of patterning times, P, of the element layer 411 is mainly shown as a common part_sRepresenting the number of patterning, D, of each of memory device layer 415 and transistor layer 413_dRepresenting bit density, D, of a DRAM_3dRepresenting the bit density, P, of one memory device layer 415_dRepresenting the number of patterning of the DRAM. Note that P_dIncluding the amount of increase that occurs due to the reduction.

Table 1 shows the estimated value of the bit density of a commercially available DRAM and the estimated value of the bit density of a semiconductor device according to an embodiment of the present invention. In addition, the process nodes of the commercially available DRAM are 18nm and 1 Xnm. In addition, a semiconductor device according to an embodiment of the present invention is estimated under the following conditions: the process node is 30nm, and the number of stacked memory device layers in the cells a to E is 5, 10, and 20.

[ Table 1]

Table 2 shows the result of estimating the relative bit cost of the semiconductor device according to one embodiment of the present invention from the bit cost of a commercially available DRAM. Note that a DRAM with a process node of 1Xnm was used in the bit cost comparison. In addition, a semiconductor device according to an embodiment of the present invention is estimated under the following conditions: the process node is 30nm, and the number of stacked memory device layers in the cells a to D is 5, 10, and 20.

[ Table 2]

The structure described in this embodiment can be implemented in combination with the structures described in other embodiments and the like as appropriate.

(embodiment mode 3)

In this embodiment mode, a metal oxide (hereinafter referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment modes will be described.

The metal oxide preferably contains at least indium or zinc. Particularly preferably indium and zinc. In addition, aluminum, gallium, yttrium, tin, or the like is preferably contained. Further, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like may be contained.

< Classification of Crystal Structure >

First, classification of crystal structures in an oxide semiconductor is described with reference to fig. 46A. Fig. 46A is a diagram illustrating classification of a crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

As shown in fig. 46A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". In addition, in "Amorphous" includes the complete Amorphous. The "crystal" includes CAAC (c-axis-aligned crystal), nc (nanocrystalline) and CAC (closed-aligned composite) (enclosing single crystal and polycrystalline). In addition, the classification of "Crystalline" does not include single crystals, multiple crystals and complex Amorphous. The category of "Crystal" includes single Crystal and multiple Crystal.

In addition, the structure in the portion of the outline shown in fig. 46A, which is thickened, is an intermediate state between "Amorphous" and "crystalline", and belongs to a New Crystal phase. That is, the structure is completely different from "Crystal" or "Amorphous" which is unstable in energy properties.

In addition, the crystal structure of the film or the substrate can be evaluated using X-Ray Diffraction (XRD) spectroscopy. Here, fig. 46B shows an XRD spectrum obtained by GIXD (Grazing-inclusion XRD) measurement of the CAAC-IGZO film classified as "crystalloid". The GIXD method is also called a thin film method or Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in fig. 46B is simply referred to as XRD spectrum. In addition, the composition of the CAAC-IGZO film shown In fig. 46B is In: ga: zn is 4: 2: 3[ atomic number ratio ]. In addition, the CAAC-IGZO film shown in FIG. 46B had a thickness of 500 nm.

As shown in fig. 46B, a peak indicating clear crystallinity was detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation was detected in the vicinity of 31 ° 2 θ. As shown in fig. 46B, the peak value near 31 ° when 2 θ is asymmetric about the angle at which the peak intensity is detected.

In addition, the crystal structure of the film or the substrate can be evaluated using a Diffraction pattern (also referred to as a nanobeam Electron Diffraction) observed by a nanobeam Electron Diffraction method (NBED). FIG. 46C shows the diffraction pattern of the CAAC-IGZO film. Fig. 46C is a diffraction pattern observed from an NBED in which an electron beam is incident in a direction parallel to the substrate. In addition, the composition of the CAAC-IGZO film shown In fig. 46C is In: ga: zn is 4: 2: 3[ atomic number ratio ]. In the nanobeam electron diffraction method, an electron diffraction method with a beam diameter of 1nm is performed.

As shown in fig. 46C, a plurality of spots indicating C-axis orientation were observed in the diffraction pattern of the CAAC-IGZO film.

< Structure of oxide semiconductor >

When attention is paid to the crystal structure of the oxide semiconductor, the classification of the oxide semiconductor may be different from that in fig. 46A. For example, the oxide semiconductor can be classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor. Examples of the non-single crystal oxide semiconductor include CAAC-OS and nc-OS. The non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, an a-like OS (amorphous oxide semiconductor), an amorphous oxide semiconductor, and the like.

The CAAC-OS, nc-OS and a-like OS will be described in detail.

[CAAC-OS]

The CAAC-OS is an oxide semiconductor including a plurality of crystalline regions whose c-axes are oriented in a specific direction. The specific direction is a thickness direction of the CAAC-OS film, a normal direction of a surface of the CAAC-OS film on which the CAAC-OS film is formed, or a normal direction of a surface of the CAAC-OS film. In addition, the crystalline region is a region having periodicity of atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region in which the lattice arrangement is uniform. The CAAC-OS has a region where a plurality of crystal regions are connected in the direction of the a-b plane, and this region may have distortion. The distortion is a portion in which, in a region where a plurality of crystal regions are connected, the direction of lattice arrangement changes between a region in which lattice arrangement is uniform and another region in which lattice arrangement is uniform. In other words, CAAC-OS refers to an oxide semiconductor in which the c-axis is oriented and there is no significant orientation in the a-b plane direction.

Each of the plurality of crystal regions is composed of one or more fine crystals (crystals having a maximum diameter of less than 10 nm). When the crystal region is composed of one fine crystal, the maximum diameter of the crystal region is less than 10 nm. When the crystal region is composed of a plurality of fine crystals, the size of the crystal region may be about several tens of nm.

In the In-M-Zn oxide (In which the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) including a layer In which indium (In) and oxygen are stacked (hereinafter, In layer) and a layer In which the element M, zinc (Zn), and oxygen are stacked (hereinafter, M, Zn layer). In addition, indium and the element M may be substituted for each other. Therefore, the (M, Zn) layer sometimes contains indium. In addition, the In layer may contain the element M. Note that the In layer sometimes contains Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

For example, when a structural analysis is performed on a CAAC-OS film using an XRD apparatus, in an Out-of-plane XRD measurement using a θ/2 θ scan, a peak of c-axis orientation is detected at or near 31 ° 2 θ. Note that the position (2 θ value) of the peak indicating the c-axis orientation may vary depending on the kind, composition, and the like of the metal element constituting the CAAC-OS.

In addition, for example, a plurality of bright spots (spots) were observed in the electron diffraction pattern of the CAAC-OS film. When the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) is taken as a center of symmetry, a certain spot and the other spots are observed at positions point-symmetric to each other.

When the crystal region is observed from the above-mentioned specific direction, the lattice arrangement in the crystal region is substantially hexagonal, but the unit lattice is not limited to regular hexagonal, and may be non-regular hexagonal. In addition, the distortion may have a lattice arrangement such as a pentagon or a heptagon. In addition, no clear grain boundary (grain boundary) was observed in the vicinity of the CAAC-OS distortion. That is, the distortion of the lattice arrangement suppresses the formation of grain boundaries. This may be because CAAC-OS can tolerate distortion that occurs due to a low density of the arrangement of oxygen atoms in the a-b plane direction or due to a change in the bonding distance between atoms due to substitution of metal atoms.

Further, it was confirmed that the crystal structure of the grain boundary was clearly defined as so-called polycrystal (crystal). Since the grain boundary becomes a recombination center and carriers are trapped, there is a possibility that the on-state current of the transistor is reduced, the field-effect mobility is reduced, or the like. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of crystalline oxides providing a semiconductor layer of a transistor with an excellent crystal structure. Note that, in order to constitute the CAAC-OS, a structure including Zn is preferable. For example, an In-Zn oxide and an In-Ga-Zn oxide are preferable because the occurrence of grain boundaries can be further suppressed as compared with an In oxide.

CAAC-OS is an oxide semiconductor having high crystallinity and no clear grain boundary is observed. Therefore, it can be said that in CAAC-OS, the decrease in electron mobility due to the grain boundary does not easily occur. Further, since crystallinity of an oxide semiconductor may be reduced by mixing of impurities, generation of defects, or the like, CAAC-OS can be said to be an oxide semiconductor with less impurities or defects (oxygen vacancies, or the like). Therefore, the oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS has high heat resistance and high reliability. The CAAC-OS is also stable against high temperature (so-called heat buildup) in the manufacturing process. Thus, the use of the CAAC-OS for the OS transistor can increase the degree of freedom in the manufacturing process.

[nc-OS]

In nc-OS, the atomic arrangement in a minute region (for example, a region of 1nm to 10nm, particularly 1nm to 3 nm) has periodicity. In other words, nc-OS has a minute crystal. The size of the fine crystal is, for example, 1nm or more and 10nm or less, particularly 1nm or more and 3nm or less, and the fine crystal is called a nanocrystal. In addition, no regularity in crystallographic orientation was observed between different nanocrystals for nc-OS. Therefore, orientation was not observed in the entire film. Therefore, sometimes nc-OS does not differ from a-like OS or amorphous oxide semiconductor in some analytical methods. For example, when the nc-OS film is subjected to structural analysis using an XRD device, a peak indicating crystallinity is not detected in an Out-of-plane XRD measurement using a theta/2 theta scan. Further, when electron diffraction using electron rays having a larger beam diameter than that of the nanocrystal (for example, 50nm or more) (also referred to as selective electron diffraction) is performed on the nc-OS film, a diffraction pattern similar to a halo pattern is observed. On the other hand, when electron diffraction (also referred to as nanobeam electron beam) using electron beam having a beam diameter close to or smaller than the size of nanocrystal (for example, 1nm or more and 30nm or less) is performed on the nc-OS film, an electron diffraction pattern in which a plurality of spots are observed in an annular region centered on a direct spot may be obtained.

[a-like OS]

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS contains holes or low density regions. That is, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. The hydrogen concentration in the film of the a-like OS is higher than that in the films of nc-OS and CAAC-OS.

< construction of oxide semiconductor >

Next, the details of the CAC-OS will be described. The CAC-OS will be described with respect to the material composition.

[CAC-OS]

CAC-OS is, for example, a structure in which elements contained in a metal oxide are unevenly distributed, and the size of a material containing unevenly distributed elements is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size. Note that a state in which one or more metal elements are unevenly distributed in a metal oxide and a region containing the metal elements is mixed is also referred to as a mosaic shape or a patch (patch) shape in the following, and the size of the region is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size.

The CAC-OS is a structure in which a material is divided into a first region and a second region to form a mosaic, and the first region is distributed in a film (hereinafter, also referred to as a cloud). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

Here, the atomic number ratios of In, Ga and Zn with respect to the metal elements of CAC-OS constituting the In-Ga-Zn oxide are each referred to as [ In ], [ Ga ] and [ Zn ]. For example, In the CAC-OS of the In-Ga-Zn oxide, the first region is a region whose [ In ] is larger than that In the composition of the CAC-OS film. In addition, the second region is a region whose [ Ga ] is larger than [ Ga ] in the composition of the CAC-OS film. In addition, for example, the first region is a region whose [ In ] is larger than [ In ] In the second region and whose [ Ga ] is smaller than [ Ga ] In the second region. In addition, the second region is a region whose [ Ga ] is larger than [ Ga ] In the first region and whose [ In ] is smaller than [ In ] In the first region.

Specifically, the first region is a region containing indium oxide, indium zinc oxide, or the like as a main component. The second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. In other words, the first region can be referred to as a region containing In as a main component. The second region may be referred to as a region containing Ga as a main component.

Note that a clear boundary between the first region and the second region may not be observed.

For example, In CAC-OS of an In-Ga-Zn oxide, it was confirmed that the oxide had a structure In which a region (first region) containing In as a main component and a region (second region) containing Ga as a main component were unevenly distributed and mixed, based on an EDX surface analysis (mapping) image obtained by Energy Dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy).

When the CAC-OS is used for a transistor, the CAC-OS can have a switching function (function of controlling on/off) by a complementary action of the conductivity due to the first region and the insulation due to the second region. In other words, the CAC-OS material has a function of conductivity in one part and an insulating function in the other part, and has a function of a semiconductor in the whole material. By separating the conductive function and the insulating function, each function can be improved to the maximum. Therefore, by using the CAC-OS for the transistor, a high on-state current (I) can be realized_on) High field effect mobility (mu) and good switching operation.

Oxide semiconductors have various structures and various characteristics. The oxide semiconductor according to one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

< transistor with oxide semiconductor >

Here, a case where the above-described oxide semiconductor is used for a transistor will be described.

By using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized.

An oxide semiconductor having a low carrier concentration is preferably used for the transistor. For example, the carrier concentration in the oxide semiconductor may be 1 × 10¹⁷cm^-3Hereinafter, it is preferably 1 × 10¹⁵cm^-3Hereinafter, more preferably 1 × 10¹³cm^-3Hereinafter, more preferably 1 × 10¹¹cm^-3Hereinafter, more preferably less than 1X 10¹⁰cm^-3And 1 × 10^-9cm^-3The above. In the case where the purpose is to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification and the like, a state where the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". In addition, an oxide semiconductor having a low carrier concentration is sometimes referred to as an "intrinsic high-purity" or an "intrinsic substantially high-purity" oxide semiconductor.

Since the oxide semiconductor film which is intrinsic or substantially intrinsic in high purity has a lower density of defect states, it is possible to have a lower density of trap states.

Further, the electric charges trapped in the trap level of the oxide semiconductor may take a long time to disappear, and may act as fixed electric charges. Therefore, the transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electric characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. The impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

< impurities >

Here, the influence of each impurity in the oxide semiconductor is described.

When the oxide semiconductor contains silicon or carbon which is one of the group 14 elements, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor or in the vicinity of the interface of the oxide semiconductor (concentration measured by Secondary Ion Mass Spectrometry (SIMS))¹⁸atoms/cm³Hereinafter, 2 × 10 is preferable¹⁷atoms/cm³The following.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level may be formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has a normally-on characteristic. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is set to 1X 10¹⁸atoms/cm³Hereinafter, 2 × 10 is preferable¹⁶atoms/cm³The following.

When the oxide semiconductor contains nitrogen, electrons as carriers are easily generated, and the carrier concentration is increased to make the oxide semiconductor n-type. As a result, a transistor using an oxide semiconductor containing nitrogen for a semiconductor tends to have a normally-on characteristic. Alternatively, when the oxide semiconductor contains nitrogen, a trap level may be formed. As a result, the electrical characteristics of the transistor may be unstable. Therefore, the nitrogen concentration in the oxide semiconductor measured by SIMS is set to be lower than 5 × 10¹⁹atoms/cm³Preferably 5X 10¹⁸atoms/cm³Hereinafter, more preferably 1 × 10¹⁸atoms/cm³Hereinafter, more preferably 5 × 10¹⁷atoms/cm³The following.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to the metal atom to generate water, and thus oxygen is sometimes formedA vacancy. When hydrogen enters the oxygen vacancy, electrons are sometimes generated as carriers. In addition, a part of hydrogen is bonded to oxygen bonded to a metal atom, and electrons as carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing hydrogen easily has a normally-on characteristic. Thus, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by SIMS is set to be lower than 1 × 10²⁰atoms/cm³Preferably less than 1X 10¹⁹atoms/cm³More preferably less than 5X 10¹⁸atoms/cm³More preferably less than 1X 10¹⁸atoms/cm³。

By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

Note that this embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.

(embodiment mode 4)

In this embodiment, a control logic circuit 61, a row driver circuit 62, a column driver circuit 63, and an output circuit 64 provided in a silicon substrate 50 in a semiconductor device 10 described in embodiment 1 will be described.

Fig. 47 is a block diagram showing a configuration example of a semiconductor device used as a memory device. The semiconductor device 10E includes a peripheral circuit 80 and a memory cell array 70. The peripheral circuit 80 includes a control logic circuit 61, a row drive circuit 62, a column drive circuit 63, and an output circuit 64.

The memory cell array 70 includes a plurality of memory cells 42. The row driving circuit 62 includes a row decoder 71 and a word line driving circuit 72. The column driving circuit 63 includes a column decoder 81, a precharge circuit 82, an amplification circuit 83, and a write circuit 84. The precharge circuit 82 has a function of precharging the global bit line GBL, the local bit line LBL, and the like. The amplifier circuit 83 has a function of amplifying the data signal read from the global bit line GBL and the local bit line LBL. The amplified data signal is output to the outside of the semiconductor device 10E as a digital data signal RDATA through the output circuit 64.

The semiconductor device 10E is supplied with a low power supply Voltage (VSS) as a power supply voltage, a high power supply Voltage (VDD) for the peripheral circuit 80, and a high power supply Voltage (VIL) for the memory cell array 70 from the outside.

Control signals (CE, WE, RE), address signals ADDR, and data signals WDATA are input to the semiconductor device 10E from the outside. Address signal ADDR is input to row decoder 71 and column decoder 81, and WDATA is input to write circuit 84.

The control logic circuit 61 processes input signals (CE, WE, RE) from the outside to generate control signals for the row decoder 71 and the column decoder 81. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 61 is not limited to this, and another control signal may be input as necessary. For example, a control signal for determining a defective bit may be input to determine a data signal read from an address of a specific memory cell as a defective bit.

The circuits and signals described above can be used as appropriate as needed.

In general, as a semiconductor device in a computer or the like, various memory devices (memories) can be used depending on the use thereof. FIG. 48 shows a hierarchy of various storage devices. The higher the access speed of the upper storage device is required, the higher the storage capacity and the higher the recording density of the lower storage device are required. Fig. 48 shows, from the top, a memory, an sram (static Random Access memory), a dram (dynamic Random Access memory), and a 3DNAND memory, which are mounted together as a register in an arithmetic processing device such as a CPU.

Since a memory mounted as a register in an arithmetic processing device such as a CPU is used for temporary storage of arithmetic results, access from the arithmetic processing device is frequently performed. Therefore, a higher operating speed than the storage capacitor is required. The register has a function of holding setting information of the arithmetic processing device.

SRAM is used for cache, for example. The cache memory has a function of copying and holding a part of information held in the main memory. By copying data that is frequently used in a cache, the speed of access to the data can be increased.

DRAM is used for a main memory, for example. The main memory has a function of holding a program or data read out from a storage (storage). The recording density of DRAM is about 0.1 to 0.3Gbit/mm²。

The 3D NAND memory is used for storage, for example. The storage has a function of holding data that needs to be stored for a long period of time and various programs used by the arithmetic processing device. Therefore, storage is required to have a larger storage capacity and a higher recording density than a faster operating speed. The recording density of the memory device for storage is about 0.6 to 6.0Gbit/mm²。

A semiconductor device used as a memory device according to one embodiment of the present invention has high operation speed and can hold data for a long period of time. The semiconductor device according to one embodiment of the present invention can be used as a semiconductor device located in a boundary area 901 between a cache level and a main memory level. The semiconductor device according to one embodiment of the present invention can be used as a semiconductor device located in a boundary region 902 including both a level of a main memory and a level of storage.

(embodiment 5)

This embodiment mode shows an example of an electronic component and an electronic device in which the semiconductor device and the like described in the above embodiment modes are mounted.

< electronic Components >

First, an example of electronic components mounted with the semiconductor device 10 and the like will be described with reference to fig. 49A and 49B.

Fig. 49A shows a perspective view of the electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in fig. 49A includes the semiconductor device 10 in which the element layer 20 is laminated on the silicon substrate 50 in the mold 711. In fig. 49A, a part of the electronic component 700 is omitted in the drawing in order to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 10 through a wire 714. The electronic component 700 is mounted on a printed circuit board 702, for example. By combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702, respectively, the mounting substrate 704 is completed.

Fig. 49B shows a perspective view of the electronic component 730. The electronic component 730 is an example of an SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer (interposer)731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 10 are provided on the interposer 731.

An example in which the semiconductor device 10 is used as a High Bandwidth Memory (HBM) is shown in the electronic component 730. In addition, the semiconductor device 735 may use an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. As the board 731, a silicon board, a resin board, or the like can be used.

The interposer 731 includes a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different pitches of terminals. The plurality of wirings are formed of a single layer or a plurality of layers. Furthermore, board 731 has a function of electrically connecting an integrated circuit provided over board 731 and an electrode provided over package substrate 732. Therefore, the interposer is also sometimes referred to as a "rewiring substrate" or an "intermediate substrate". Further, a through-hole electrode may be provided in the board 731, and the integrated circuit and the package substrate 732 may be electrically connected through the through-hole electrode. In addition, in the case of using a Silicon interposer, a TSV (Through Silicon Via) may be used as a Through electrode.

As the insertion plate 731, a silicon insertion plate is preferably used. Since the silicon interposer does not need to be provided with an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of the silicon interposer can be performed in a semiconductor process, it is easy to form a fine wiring which is difficult to form when using a resin interposer.

In HBM, many wires need to be connected in order to realize a wide memory bandwidth. Therefore, it is required that fine wiring be formed with high density on an interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer for mounting the HBM.

In addition, in an SiP or MCM using a silicon interposer, a decrease in reliability due to a difference in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Further, since the surface flatness of the silicon interposer is high, a connection failure is less likely to occur between the integrated circuit provided in the silicon interposer and the silicon interposer. It is particularly preferred to use the silicon interposer for a 2.5D package (2.5D mounting) in which a plurality of integrated circuits are arranged side by side on the interposer.

Further, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 730. In the case where a heat sink is provided, it is preferable to make the height of the integrated circuit provided over the board 731 uniform. For example, in the electronic component 730 shown in this embodiment, the semiconductor device 10 and the semiconductor device 735 are preferably made to have the same height.

In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732. Fig. 49B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. The electrode 733 may be formed using a conductive needle. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

The electronic component 730 may be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, a mounting method such as SPGA (stacked Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad J-leaded Package), or QFN (Quad Flat Non-leaded Package) can be used.

< electronic apparatus >

Next, an example of an electronic device in which the electronic component is mounted will be described with reference to fig. 50.

The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezoelectric sensor, a light sensor, a gyro sensor, and the like), a moving mechanism, and the like. The electronic means 730 includes a processor or the like and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data measured by a sensor.

The microphone has a function of detecting an audio signal such as a user's voice and surrounding sounds. The speaker has a function of emitting audio signals such as sounds and warning sounds. The robot 7100 may analyze an audio signal input through a microphone and emit a desired audio signal from a speaker. The robot 7100 may communicate with the user by using a microphone and speaker.

The camera has a function of taking an image of the periphery of the robot 7100. Further, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can take a surrounding image by using a camera, analyze the image, and determine the presence or absence of an obstacle during movement.

The flying object 7120 includes a propeller, a camera, a battery, and the like, and has an autonomous flying function. The electronic component 730 has a function of controlling these peripheral devices.

For example, image data photographed by a camera is stored to the electronic component 700. The electronic unit 730 can determine whether or not an obstacle is present during movement by analyzing the image data. In addition, the remaining capacity of the battery can be estimated by the change in the storage capacity of the battery using the electronic means 730.

The cleaning robot 7140 includes a display disposed on the top surface, a plurality of cameras disposed on the side surface, a brush, operation buttons, various sensors, and the like. Although not shown, the cleaning robot 7140 is provided with tires, a suction port, and the like. The sweeping robot 7140 can automatically walk to detect the garbage and can suck the garbage from the suction inlet on the bottom surface.

For example, the electronic unit 730 can determine the presence or absence of an obstacle such as a wall, furniture, or a step by analyzing an image captured by the camera. In addition, in the case where an object such as a wire that may be wound around the brush is detected by image analysis, the rotation of the brush may be stopped.

The automobile 7160 includes an engine, tires, brakes, steering devices, cameras, and the like. For example, the electronic unit 730 performs control for optimizing the traveling state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state, and brake use frequency. For example, image data photographed by a camera is stored to the electronic component 700.

The electronic component 700 and/or the electronic component 730 can be mounted in a TV device 7200 (television receiving device), a smartphone 7210, PCs (personal computers) 7220 and 7230, a game machine 7240, a game machine 7260, or the like.

For example, the electronic component 730 provided in the TV device 7200 can function as an image engine. For example, the electronic component 730 may perform image processing such as noise removal, up-conversion of resolution (up-conversion), and the like.

The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. The electronic means 730 control these peripheral devices.

PC7220 and PC7230 are examples of a notebook PC and a desktop PC, respectively. The keyboard 7232 and the display device 7233 may be connected to the PC7230 wirelessly or by wire. The game machine 7240 is an example of a portable game machine. Gaming machine 7260 is an example of a stationary gaming machine. The game machine 7260 is connected to the controller 7262 wirelessly or by wire. The electronic component 700 and/or the electronic component 730 may be mounted to the controller 7262.

This embodiment can be implemented in combination with the structures described in other embodiments and the like as appropriate.

(Note about the description of this specification, etc.)

Next, the above embodiments and the description of each configuration in the embodiments are annotated.

The structure described in each embodiment can be combined with the structure described in other embodiment or example as appropriate to form an embodiment of the present invention. In addition, when a plurality of configuration examples are shown in one embodiment, these configuration examples may be appropriately combined.

In addition, the contents (or a part thereof) described in one embodiment can be applied to, combined with, or replaced with the other contents (or a part thereof) described in the embodiment and/or the contents (or a part thereof) described in another embodiment or another plurality of embodiments.

Note that the content described in the embodiments refers to content described in various figures or content described in a text described in the specification in each embodiment.

In addition, a drawing (or a part thereof) shown in one embodiment may be combined with another part of the drawing, another drawing (or a part thereof) shown in the embodiment, and/or a drawing (or a part thereof) shown in another or more other embodiments to form a plurality of drawings.

In this specification and the like, constituent elements are classified according to functions and are represented as blocks independent of each other in a block diagram. However, in an actual circuit or the like, it is difficult to classify constituent elements according to functions, and there are cases where one circuit involves a plurality of functions or where a plurality of circuits involve one function. Therefore, the blocks in the block diagrams are not limited to the constituent elements described in the specification, and may be expressed in an alternative manner as appropriate.

For convenience of explanation, in the drawings, any size, thickness of layer, or region is illustrated. Therefore, the present invention is not limited to the dimensions in the drawings. The drawings are schematically illustrated for clarity and are not limited to the shapes, numerical values, etc. shown in the drawings. For example, unevenness of a signal, voltage, or current due to noise, timing deviation, or the like may be included.

The positional relationship of the components shown in the drawings and the like is relative. Therefore, when the constituent elements are described with reference to the drawings, terms such as "upper" and "lower" indicating a positional relationship may be used for convenience. The positional relationship of the components is not limited to the contents described in the present specification, and words may be appropriately changed depending on the case.

In this specification and the like, in describing a connection relationship of the transistor, a description is given of "one of a source and a drain" (a first electrode or a first terminal) and "the other of the source and the drain" (a second electrode or a second terminal). This is because the source and the drain of the transistor change depending on the structure, the operating condition, or the like of the transistor. Note that the source and the drain of the transistor may be appropriately referred to as a source (drain) terminal, a source (drain) electrode, or the like as appropriate.

In the present specification and the like, "electrode" or "wiring" is not limited to a functional constituent element thereof. For example, an "electrode" is sometimes used as part of a "wiring", and vice versa. The term "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wirings" are integrally formed.

In this specification and the like, the voltage and the potential may be appropriately exchanged. The voltage is a potential difference from a reference potential, and for example, when the reference potential is a ground voltage (ground voltage), the voltage may be referred to as a potential. The ground potential does not necessarily mean 0V. Note that the potentials are relative, and the potential supplied to the wiring or the like sometimes varies depending on the reference potential.

In this specification and the like, a node may be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit configuration, a device configuration, or the like. In addition, a terminal, a wiring, or the like may also be referred to as a node.

In this specification and the like, the connection of a and B means that a and B are electrically connected. Here, the electrical connection between a and B means a connection that can transmit electrical signals of a and B when an object (a switch, an element such as a transistor element or a diode, or a circuit including the element and a wiring) is present between a and B. Note that the case where a and B are electrically connected includes the case where a and B are directly connected. Here, the direct connection of a and B means a connection in which a and B can transmit an electric signal through a wire (or an electrode) or the like therebetween without passing through the above-mentioned object. In other words, direct connection refers to connection that can be regarded as the same circuit diagram when represented using an equivalent circuit.

In this specification and the like, a switch is an element having a function of controlling whether or not to allow a current to flow by being turned into an on state (on state) or an off state (off state). Alternatively, the switch refers to an element having a function of selecting and switching a current path.

In this specification and the like, for example, the channel length refers to a distance between a source and a drain in a region where a semiconductor (or a portion through which a current flows in the semiconductor when the transistor is in an on state) and a gate overlap or a region where a channel is formed in a plan view of the transistor.

In this specification and the like, for example, the channel width refers to a length of a region where a semiconductor (or a portion through which a current flows in a semiconductor when a transistor is in an on state) overlaps with a gate electrode, or a portion where a source and a drain are opposed in a region where a channel is formed.

In this specification and the like, terms such as "film" and "layer" may be interchanged depending on the situation or state. For example, the "conductive layer" may be sometimes changed to a "conductive film". In addition, for example, the "insulating film" may be replaced with an "insulating layer".

[ description of symbols ]

BL 2: wiring, EN 1: signal, RE 1: signal, RE 2: signal, SL 2: wiring, T11: time, T12: time, T13: time, T14: time, T15: time, T16: time, T17: time, T18: time, T19: time, T20: time, 10: semiconductor device, 10A: semiconductor device, 10B: semiconductor device, 10C: semiconductor device, 10E: semiconductor device, 20: element layer, 20_ M: element layer, 20_ 1: element layer, 30: transistor layer, 31: transistor, 32: transistor, 33: transistor, 34: transistor, 35: control circuit, 35_ pre: control circuit, 35B: control circuit, 35C: control circuit, 36: control circuit, 36_ pre: control circuit, 37: transistor, 40: transistor layer, 40_ k: transistor layer, 40_ 1: transistor layer, 41_ k: transistor layer, 41_ 1: transistor layer, 41_ 2: transistor layer, 42: storage unit, 43: transistor, 44: capacitor, 49: transistor layer, 49_ k: transistor layer, 49_ 1: transistor layer, 50: silicon substrate, 51: control circuit, 51A: control circuit, 52: switching circuit, 52_ 1: transistor, 52_ 2: transistor, 53: precharge circuit, 53_ 1: transistor, 53_ 3: transistor, 54: precharge circuit, 54_ 1: transistor, 54_ 3: transistor, 55: sense amplifier, 55_ 1: transistor, 55_ 2: transistor, 55_ 3: transistor, 55_ 4: transistor, 57_ 1: transistor, 57_ 2: transistor, 58_ 1: transistor, 58_ 2: transistor, 59: potential setting circuit, 61: control logic circuit, 62: row driving circuit, 63: column drive circuit, 64: output circuit, 70: memory cell array, 71: row decoder, 72: word line driver circuit, 80: peripheral circuit, 81: column decoder, 82: precharge circuit, 83: amplification circuit, 84: write circuit, 90: transistor layer, 91: storage unit, 92: transistor, 93: transistor, 94: capacitor, 100: storage device, 200: transistor, 200M: transistor, 200T: transistor, 205: conductor, 205 a: conductor, 205 b: conductor, 211: insulator, 212: insulator, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: oxide, 230 a: oxide, 230 b: oxide, 230 c: oxide, 240: conductor, 240 a: conductor, 240 b: conductor, 241: insulator, 241 a: insulator, 241 b: insulator, 242: conductor, 242 a: conductor, 242 b: conductor, 243: oxide, 243 a: oxide, 243 b: oxide, 246: electrical conductor, 246 a: conductor, 246 b: conductor, 250: insulator, 260: conductor, 260 a: conductor, 260 b: conductor, 272: insulator, 273: insulator, 274: insulator, 275: insulator, 276: electrical conductor, 277: insulator, 278: electrical conductor, 279: insulator, 280: insulator, 282: insulator, 283: insulator, 284: insulator, 287: insulator, 290: electric conductor, 292: capacitive element, 292A: capacitive element, 292B: capacitive element, 294: conductor, 295: insulator, 296: insulator, 297: conductor, 298: insulator, 299: conductor, 300: transistor, 311: semiconductor substrate, 313: semiconductor region, 314 a: low-resistance region, 314 b: low-resistance region, 315: insulator, 316: conductor, 411: element layer, 413: transistor layer, 413_ m: transistor layer, 413_ 1: transistor layer, 415: memory device layer, 415 — n: memory device layer, 415_ p: memory device layer, 415_ p-1: memory device layer, 415_ 1: memory device layer, 415_ 3: memory device layer, 415_ 4: memory device layer, 420: memory device, 420A: memory device, 420B: memory device, 422: region, 424: electrical conductor, 426: electrical conductor, 428: electrical conductor, 430: conductor, 432: storage unit, 433: storage unit, 434: storage unit, 435: storage unit, 470: memory cell, 470_ m: memory cell, 470_ 1: memory cell, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 711: mold, 712: land, 713: electrode pad, 714: line, 730: electronic component, 731: plug board, 732: package substrate, 733: electrode, 735: semiconductor device, 820: peripheral circuit, 901: boundary region, 902: border area, 7100: robot, 7120: flyer, 7140: sweeping robot, 7160: car, 7200: TV apparatus, 7210: smart phone, 7220: PC, 7230: PC, 7232: keyboard, 7233: display device, 7240: game machine, 7260: game machine, 7262: and a controller.