阅读说明：本技术 可编程模块、时序控制芯片和显示装置 (Programmable module, time sequence control chip and display device ) 是由 付刚伟 康报虹 于 2021-07-30 设计创作，主要内容包括：本申请公开了一种可编程模块、时序控制芯片和显示装置,可编程模块包括低压差分信号解码模块、信号处理模块、微型低压差分信号编码模块、通讯控制模块、模拟量控制模块、非易失性存储量控制模块、时序生成模块、外围电路控制模块和主控制模块,主控制模块控制所述低压差分信号解码模块、信号处理模块、微型低压差分信号编码模块、通讯控制模块、模拟量控制模块、非易失性存储量控制模块、时序生成模块和外围电路控制模块的数据输出。通过上述设计,使得可编程模块具有多功能、高集成度和高性能的特点,结合到显示装置中,能够有效简化了显示装置中的内部电路结构和功耗,并监控显示装置内部电路,提高电路稳定性。(The application discloses programmable module, sequential control chip and display device, programmable module include low pressure difference signal decoding module, signal processing module, miniature low pressure difference signal coding module, communication control module, analog quantity control module, nonvolatile memory quantity control module, time sequence generation module, peripheral circuit control module and main control module, main control module control low pressure difference signal decoding module, signal processing module, miniature low pressure difference signal coding module, communication control module, analog quantity control module, nonvolatile memory quantity control module, time sequence generation module and peripheral circuit control module's data output. Through the design, the programmable module has the characteristics of multifunction, high integration level and high performance, and is combined into the display device, so that the internal circuit structure and power consumption in the display device can be effectively simplified, the internal circuit of the display device can be monitored, and the circuit stability can be improved.)

1. A programmable module, comprising:

the low-voltage differential signal decoding module receives a low-voltage differential signal;

the signal processing module is used for converting the low-voltage differential signal into an RGB signal;

the micro low-voltage differential signal coding module is used for converting the RGB signals into micro low-voltage differential signals and outputting source electrode driving signals;

the communication control module receives data transmitted from the outside;

the analog quantity control module receives the detected voltage detection value;

the nonvolatile storage quantity control module stores video standard parameters and standard voltage values corresponding to the voltage detection values;

a timing generation module outputting a gate driving signal;

the peripheral circuit control module outputs a power supply maintaining or turning-off signal; and

and the main control module is electrically connected with the low-voltage differential signal decoding module, the signal processing module, the miniature low-voltage differential signal encoding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the time sequence generation module and the peripheral circuit control module, compares the stored video standard parameters with the low-voltage differential signals, checks whether the low-voltage differential signals meet the standard, compares the voltage detection value with a standard voltage value, and controls the data output of the low-voltage differential signal decoding module, the signal processing module, the miniature low-voltage differential signal encoding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the time sequence generation module and the peripheral circuit control module.

2. A timing control chip, comprising:

the power supply conversion module receives power supply voltage and converts the power supply voltage into a power supply signal;

the gamma module is electrically connected with the power supply conversion module, receives a power supply signal and converts the power supply signal into gamma voltage;

the programmable module receives the video signal and generates a data driving signal;

the pixel power supply module receives a power supply signal and generates a grid driving signal; and

the voltage detection module is electrically connected with the power conversion module, the gamma module and the pixel power supply module and is used for detecting the voltages in the power conversion module, the gamma module and the pixel power supply module;

the programmable module is electrically connected with the voltage detection module and the power supply conversion module, receives the voltage detected by the voltage detection module, forms a plurality of voltage detection values, compares the voltage detection values with corresponding standard voltage values in the programmable module, and controls the power supply conversion module to maintain or turn off the power supply according to the comparison result.

3. The utility model provides a display device, includes time sequence control chip, source control chip, grid control chip and display panel, the time sequence control chip receives video signal and mains voltage, to source control chip output data drive signal, and then the data line among the drive display panel, to grid control chip output grid drive signal, and then the scanning line among the drive display panel, its characterized in that, the time sequence control chip includes:

the power supply conversion module receives power supply voltage and converts the power supply voltage into a power supply signal;

the gamma module is electrically connected with the power supply conversion module, receives a power supply signal and converts the power supply signal into gamma voltage, and the source electrode control chip receives the gamma voltage;

the programmable module receives a video signal and generates a data driving signal, and the source control chip receives the data driving signal;

the pixel power supply module receives a power supply signal and generates a grid driving signal, and the grid control chip receives the grid driving signal and the power supply signal; and

the voltage detection module is electrically connected with the power conversion module, the gamma module, the source control chip, the grid control chip and the pixel power supply module and is used for detecting the voltages in the power conversion module, the gamma module, the source control chip, the grid control chip and the pixel power supply module;

the programmable module is electrically connected with the voltage detection module and the power supply conversion module, receives the voltage detected by the voltage detection module, forms a plurality of voltage detection values, compares the voltage detection values with corresponding standard voltage values in the programmable module, and controls the power supply conversion module to maintain or turn off the power supply according to the comparison result.

4. The display device according to claim 3, wherein the voltage detection module comprises a digital-to-analog converter, and the digital-to-analog converter samples and converts the voltages in the power conversion module, the gamma module, the source control chip, the gate control chip and the pixel power supply module into data voltage signals;

and the programmable module receives the data voltage signal through a serial peripheral interface and compares the data voltage signal with a standard voltage value.

5. The display device according to claim 3, wherein the timing control chip further comprises a communication interface circuit, the communication interface circuit is electrically connected with the programmable module and can receive externally transmitted data through a serial port;

the programmable module comprises a buffer chip, a gamma voltage value is stored in the buffer chip, the buffer chip is electrically connected with the gamma module and the communication interface circuit, and the buffer chip adjusts the gamma value of the gamma module through transmission data received by the communication interface circuit.

6. The display device according to claim 3, wherein the programmable module includes a data signal decoding module, a signal processing module, and a data signal encoding module, the data signal decoding module receives a first video signal, the signal processing module converts the first video signal into an RGB signal, the data signal encoding module converts the RGB signal into a second video signal, and inputs the second video signal into the source control chip;

the first video screen signal and the second video screen signal are video signals with different formats.

7. The display device according to claim 6, wherein the data signal decoding module includes a low voltage differential signal decoding module, the first video signal is a low voltage differential signal, and the signal processing module converts the low voltage differential signal into an RGB signal;

the data signal coding module comprises a micro low-voltage differential signal coding module, the second video signal is a micro low-voltage differential signal, and the micro low-voltage differential signal coding module converts the RGB signal into the micro low-voltage differential signal.

8. The display device of claim 7, wherein the low voltage differential signal decoding module comprises:

the clock module is used for receiving the low-voltage differential signal and performing frequency multiplication processing on the low-voltage differential signal to generate a clock signal;

the serial data conversion module is electrically connected with the clock module and is used for converting the clock signal into first serial data;

the delay module is used for carrying out delay processing on the first serial data to generate delay data; and

and the parallel data conversion module is used for converting the delay data into parallel data and inputting the parallel data into the signal processing module to generate parallel RGB signals.

9. The display device according to claim 8, wherein the micro low voltage differential signal encoding module includes two reverse data conversion modules, the two reverse data conversion modules are connected in a cascade manner to convert the received parallel RGB signals into second serial data, and the second serial data forms a micro low voltage differential signal and is input to the source control chip.

10. The display device of claim 6, wherein the programmable module further comprises:

the communication control module is electrically connected with a communication interface circuit in the time sequence control chip, and the communication interface circuit can receive data transmitted from the outside through a serial port;

the analog quantity control module is electrically connected with the voltage detection module and receives the voltage detected by the voltage detection module;

the nonvolatile storage quantity control module stores video standard parameters and standard voltage values corresponding to the voltage detection values;

the time sequence generation module is in point connection with the grid control chip and controls the opening or closing of an active switch in the display panel;

the peripheral circuit control module controls the power supply conversion module to maintain or switch off the power supply; and

and the main control module is electrically connected with the data signal decoding module, the signal processing module, the data signal coding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the time sequence generation module and the peripheral circuit control module, compares the stored video standard parameters with a first video signal received by the data signal decoding module, checks whether the first video signal meets the standard, compares the voltage detection value with a corresponding standard voltage value in the programmable module, and controls the data signal decoding module, the signal processing module, the data signal coding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the time sequence generation module and the peripheral circuit control module to output data.

Technical Field

The application relates to the technical field of display, in particular to a programmable module, a time sequence control chip and a display device.

Background

The time sequence controller (T-CON) is one of the core components of the liquid crystal display, and is a key element for realizing the normal display of the liquid crystal screen and improving the display effect and performance. At present, most of the driving circuits of the liquid crystal display are centered on a special timing controller. Since these dedicated timing controllers have a certain pertinence, the interface type, the number of data channels, the processing speed, the main functions, etc. are all solidified. Therefore, in general, a new lcd panel is designed by selecting a suitable Source control chip (Source IC) and a suitable Gate control chip (Gate IC) according to expected performance parameters and a timing controller.

However, with the continuous push-out of large-screen liquid crystal panels, the supported display resolution is higher and higher, the requirements on the timing controller are also higher and higher, the timing controller cannot completely meet the use requirements, and the requirements on the working temperature range, the stability and the like of the timing controller are stricter.

Disclosure of Invention

The application aims to provide a programmable module, a time sequence control chip and a display device which can monitor a plurality of circuit structures, and safety and stability of products are improved.

The application discloses a programmable module which comprises a low-voltage differential signal decoding module, a signal processing module, a miniature low-voltage differential signal encoding module, a communication control module, an analog quantity control module, a nonvolatile storage quantity control module, a time sequence generation module, a peripheral circuit control module and a main control module, wherein the low-voltage differential signal decoding module receives a low-voltage differential signal; the signal processing module converts the low-voltage differential signal into an RGB signal; the miniature low-voltage differential signal coding module converts the RGB signals into miniature low-voltage differential signals and outputs source electrode driving signals; the communication control module receives data transmitted from the outside; the analog quantity control module receives a detected voltage detection value; the nonvolatile storage quantity control module stores video standard parameters and standard voltage values corresponding to the voltage detection values; the time sequence generation module outputs a grid driving signal; the peripheral circuit control module outputs a power supply maintaining or turning-off signal;

the main control module is electrically connected with the low-voltage differential signal decoding module, the signal processing module, the miniature low-voltage differential signal encoding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the time sequence generation module and the peripheral circuit control module, compares the stored video standard parameters with the low-voltage differential signals, checks whether the low-voltage differential signals meet the standard, compares the voltage detection value with a standard voltage value, and controls the data output of the low-voltage differential signal decoding module, the signal processing module, the miniature low-voltage differential signal encoding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the time sequence generation module and the peripheral circuit control module.

The application also discloses a time sequence control chip which is used for the display device, and the time sequence control chip comprises a power supply conversion module, a gamma module, a programmable module, a pixel power supply module and a voltage detection module, wherein the power supply conversion module receives power supply voltage and converts the power supply voltage into a power supply signal; the gamma module is electrically connected with the power supply conversion module, receives a power supply signal and converts the power supply signal into gamma voltage; the programmable module receives a video signal and generates a data driving signal; the pixel power supply module receives a power supply signal and generates a grid driving signal; the voltage detection module is electrically connected with the power conversion module, the gamma module and the pixel power supply module and is used for detecting the voltages in the power conversion module, the gamma module and the pixel power supply module;

the programmable module is electrically connected with the voltage detection module and the power supply conversion module, receives the voltage detected by the voltage detection module, forms a plurality of voltage detection values, compares the voltage detection values with corresponding standard voltage values in the programmable module, and controls the power supply conversion module to maintain or turn off the power supply according to the comparison result.

The application also discloses a display device, which comprises a time sequence control chip, a source electrode control chip, a grid electrode control chip and a display panel, wherein the time sequence control chip receives video signals and power voltage, outputs data driving signals to the source electrode control chip, further drives a data line in the display panel, outputs grid electrode driving signals to the grid electrode control chip, and further drives a scanning line in the display panel;

the gamma module is electrically connected with the power supply conversion module, receives a power supply signal and converts the power supply signal into gamma voltage, and the source electrode control chip receives the gamma voltage; the programmable module receives a video signal and generates a data driving signal, and the source control chip receives the data driving signal; the pixel power supply module receives a power supply signal and generates a grid driving signal, and the grid control chip receives the grid driving signal and the power supply signal; the voltage detection module is electrically connected with the power conversion module, the gamma module, the source control chip, the grid control chip and the pixel power supply module and is used for detecting the voltages in the power conversion module, the gamma module, the source control chip, the grid control chip and the pixel power supply module; the programmable module is electrically connected with the voltage detection module and the power supply conversion module, receives the voltage detected by the voltage detection module, forms a plurality of voltage detection values, compares the voltage detection values with corresponding standard voltage values in the programmable module, and controls the power supply conversion module to maintain or turn off the power supply according to the comparison result.

Optionally, the voltage detection module includes a digital-to-analog converter, and the digital-to-analog converter samples voltages in the power conversion module, the gamma module, the source control chip, the gate control chip, and the pixel power supply module and converts the voltages into data voltage signals; and the programmable module receives the data voltage signal through a serial peripheral interface and compares the data voltage signal with a standard voltage value.

Optionally, the timing control chip further includes a communication interface circuit, and the communication interface circuit is electrically connected to the programmable module and can receive externally transmitted data through a serial port; the programmable module comprises a buffer chip, a gamma voltage value is stored in the buffer chip, the buffer chip is electrically connected with the gamma module and the communication interface circuit, and the buffer chip adjusts the gamma value of the gamma module through transmission data received by the communication interface circuit.

Optionally, the programmable module includes a data signal decoding module, a signal processing module and a data signal encoding module, the data signal decoding module receives a first video signal, the signal processing module converts the first video signal into an RGB signal, the data signal encoding module converts the RGB signal into a second video signal, and the second video signal is input to the source control chip; the first video screen signal and the second video screen signal are video signals with different formats.

Optionally, the data signal decoding module includes a low voltage differential signal decoding module, the first video signal is a low voltage differential signal, and the signal processing module converts the low voltage differential signal into an RGB signal; the data signal coding module comprises a micro low-voltage differential signal coding module, the second video signal is a micro low-voltage differential signal, and the micro low-voltage differential signal coding module converts the RGB signal into the micro low-voltage differential signal.

Optionally, the low-voltage differential signal decoding module includes a clock module, a serial data conversion module, a delay module, and a parallel data conversion module, where the clock module receives the low-voltage differential signal and performs frequency multiplication on the low-voltage differential signal to generate a clock signal; the serial data conversion module is electrically connected with the clock module and converts the clock signal into first serial data; the delay module carries out delay processing on the first serial data to generate delay data; and the parallel data conversion module converts the delay data into parallel data, inputs the parallel data into the signal processing module and generates parallel RGB signals.

Optionally, the micro low-voltage differential signal coding module includes two reverse data conversion modules, the two reverse data conversion modules are connected in a cascade manner, the received parallel RGB signals are converted into second serial data, and the second serial data form a micro low-voltage differential signal and are input to the source control chip.

Optionally, the programmable module further includes a communication control module, an analog quantity control module, a nonvolatile storage quantity control module, a timing sequence generation module, a peripheral circuit control module, and a main control module, where the communication control module is electrically connected to a communication interface circuit in the timing sequence control chip, and the communication interface circuit can receive externally transmitted data through a serial port; the analog quantity control module is electrically connected with the voltage detection module and receives the voltage detected by the voltage detection module; the nonvolatile storage quantity control module stores video standard parameters and standard voltage values corresponding to the voltage detection values; the time sequence generation module is in point connection with the grid control chip and controls the opening or closing of an active switch in the display panel; the peripheral circuit control module controls the power supply conversion module to maintain or switch off a power supply;

the main control module is electrically connected with the data signal decoding module, the signal processing module, the data signal coding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the time sequence generation module and the peripheral circuit control module, compares the stored video standard parameters with a first video screen signal received by the data signal decoding module, checks whether the first video screen signal meets the standard, compares the voltage detection value with a corresponding standard voltage value in the programmable module, and controls the data signal decoding module, the signal processing module, the data signal coding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the time sequence generation module and the peripheral circuit control module to output data.

The application provides a programmable module, after the programmable module is combined with a display device, the signal transcoding function of the display device is realized through an integrated low-voltage differential signal decoding module, a signal processing module and a miniature low-voltage differential signal coding module in the programmable module, and the display device combined with the programmable module can receive external information through a communication control module in the programmable module and can perform online adjustment on a program in the display device through the programmable module; the monitoring and detection of the internal circuit of the display device are realized through an analog quantity control module, a nonvolatile storage quantity control module, an LCD time sequence generation module and a peripheral circuit control module in the programmable module, and the safety performance of the internal circuit of the display device is improved. According to the display device, the plurality of functional modules are integrated together and are uniformly controlled through the main control module, so that the internal circuit structure and the power consumption of the display device are effectively simplified, and the working efficiency is greatly improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a schematic diagram of a display device according to a first embodiment of the present application;

FIG. 2 is a diagram illustrating the internal architecture of a programmable module according to a first embodiment of the present application;

fig. 3 is a schematic diagram of an operation of a data signal decoding module according to a first embodiment of the present application.

Wherein, 1, a first pin; 2. a second pin; 3. a third pin; 4. a fourth pin; 5. a fifth pin; 6. a sixth pin; 7. a seventh pin; 8. an eighth pin; 9. a ninth pin; 10. a tenth pin; 11. an eleventh pin; 12. a twelfth pin; 13. a thirteenth pin; 14. a fourteenth pin; 15. a fifteenth pin; 16. a sixteenth pin; 17. a seventeenth pin; 18. an eighteenth pin; 19. a nineteenth pin; 20. a twentieth pin; 21. a twenty-first pin; 22. a twenty-second pin; 23. a twenty-third pin; 24. a twenty-fourth pin; 25. a twenty-fifth pin; 26. a twenty-sixth pin; 27. a twenty-seventh pin; 28. a twenty-eighth pin; 29. a twenty-ninth pin; 30. a thirtieth pin; 31. a thirty-first pin; 100. a display device; 200. a time sequence control chip; 210. a power conversion module; 220. a gamma module; 230. a programmable module; 232. a data signal decoding module; 2321. a low voltage differential signal decoding module; 2322. a clock module; 2323. a serial data conversion module; 233. a signal processing module; 234. a data signal encoding module; 2341. a miniature low-voltage differential signal coding module; 235. a communication control module; 236. an analog quantity control module; 237. a non-volatile storage volume control module; 238. a timing generation module; 239. a peripheral circuit control module; 240. a main control module; 250. a pixel power supply module; 260. a voltage detection module; 261. a digital-to-analog converter; 270. a communication interface circuit; 300. a source control chip; 400. a gate control chip; 500. a display panel.

Detailed Description

It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.

Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The present application will now be described in detail with reference to the drawings and alternative embodiments, it being understood that any combination of the various embodiments or technical features described below may form new embodiments without conflict.

Fig. 1 shows a schematic diagram of a display device according to a first embodiment of the present application, as shown in fig. 1, the display device 100 includes a timing control chip 200, a source control chip 300, a gate control chip 400 and a display panel 500, the timing control chip 200 receives a video signal and a power voltage, provides a data driving signal to the source control chip 300, and further drives a data line in the display panel 500, provides a gate driving signal to the gate control chip 400, and further drives a scan line in the display panel 500, the timing control chip 200 includes a power conversion module 210, a Gamma (Gamma) module 220, a programmable module (FPGA module) 230, a pixel power supply module 250 and a voltage detection module 260, and the power conversion module 210 receives the power voltage and converts the power voltage into a power signal;

the Gamma module 220 is electrically connected to the power conversion module 210, receives a power signal and converts the power signal into Gamma voltage, and the source control chip 300 receives the Gamma voltage; the FPGA module 230 receives a video signal and generates a data driving signal, and the source control chip 300 receives the data driving signal; the pixel power supply module 250 receives a power signal and generates a gate driving signal, and the gate control chip 400 receives the gate driving signal and the power signal; the voltage detection module 260 is electrically connected to the power conversion module 210, the Gamma module 220, the source control chip 300, the gate control chip 400 and the pixel power supply module 250, and detects voltages in the power conversion module 210, the Gamma module 220, the source control chip 300, the gate control chip 400 and the pixel power supply module 250; the FPGA module 230 is electrically connected to the voltage detection module 260 and the power conversion module 210, receives the voltage detected by the voltage detection module 260, forms a plurality of voltage detection values, compares the plurality of voltage detection values with corresponding standard voltage values in the FPGA module 230, and the FPGA module 230 controls the power conversion module 210 to maintain or turn off the power according to the comparison result.

The invention adopts a large-screen thin film transistor liquid crystal display panel driving circuit based on an FPGA (Field-Programmable Gate Array, a signal processing and time sequence generating module), has the characteristics of high supporting display resolution, high circuit integration level, strong flexibility and the like, and compared with the traditional liquid crystal panel driving design, the invention also increases a circuit state monitoring circuit, can monitor the driving circuit in real time and improves the reliability of the driving circuit. And the FPGA module 230 is used as a core controller, and necessary peripheral circuits are used as auxiliary devices to drive the large-screen liquid crystal panel, so that the integration level of the circuit chip is improved. The abnormal condition of the input voltage is judged by detecting the power conversion module 210, so that the abnormal voltage data can be prevented from being transmitted to the display panel 500, and the display panel 500 is prevented from being damaged; the abnormal condition of the driving signal is monitored by detecting the voltage in the grid control chip 400, the source control chip 300, the Gamma module 220 and the pixel power supply module 250, so that the abnormal picture is prevented; therefore, the function of actively monitoring the state of each circuit in the display device 100 is realized, and the reliability of the circuit is greatly improved.

Specifically, the voltage detection module 260 includes a digital-to-analog converter 261(DAC), where the digital-to-analog converter 261 samples voltages in the power conversion module 210, the Gamma module 220, the source control chip 300, the gate control chip 400, and the pixel power supply module 250, and converts the sampled voltages into data voltage signals; the FPGA module 230 receives the data voltage signal through a Serial Peripheral Interface (SPI), compares the data voltage signal with a standard voltage value, and controls the power conversion module 210 to directly cut off the power if the data voltage signal is not within the range of the standard voltage value.

Since the liquid crystal panel driving requires multiple sets of voltages, only the voltages required by the modules in the FPGA module 230 are different, for example: the core operating voltage is 1.2V, and supplies power to various logic modules in the FPGA module 230; the driving voltage of each I/O port is generally 2.5V or 3.3V. There are also Gate-on voltage VGH, Gate-off voltage VGL, power supply voltage AVDD, common voltage VCOM, gamma voltage, etc. for supplying power to the Source driver chip (Source IC) and the Gate driver chip (Gate IC). The values and variations of these voltages directly affect the operation state of the driving circuit and the display effect of the liquid crystal panel. In order to realize effective control of the liquid crystal panel, the voltage points in each circuit structure are monitored; and in order to reduce the complexity of the monitoring circuit, the application can only detect critical voltages, such as: the DAC is used to sample the gate-on voltage VGH, the gate-off voltage VGL, the supply voltage AVDD, the common voltage VCOM, and the intermediate gamma voltage. Because the input voltage range of the DAC is 0 to +3.3V, preprocessing is required to be carried out through an operational amplifier, and all voltages reach the detection range of the DAC; in this case, it is not necessary to provide a plurality of detection structures, thereby simplifying the structure of the detection circuit. And the DAC is connected with the FPGA module 230 through an SPI interface to periodically read the voltage value of each channel.

The voltage data input by the DAC is read at intervals of a certain time through the FPAG module, whether the voltage data can be in a default safety range or not is judged, if the input voltage is abnormal, the FPGA reports the abnormal voltage state through a serial port and simultaneously closes the power supply voltage, and the liquid crystal display is prevented from being damaged; whether the driving time sequence is abnormal is judged by monitoring periodic signals returned from a Source driving chip (Source IC) and a Gate driving chip (Gate IC), and if the driving time sequence is abnormal, the power supply voltage is also shut down by reporting through a serial port; in addition, whether the input video time sequence signal meets the VESA standard can be detected. The standard voltage value corresponding to the voltage detection value, i.e. the signal standard, is stored in an external Nonvolatile (NVM) memory chip, and is read when being powered on, and when the FPGA module 230 detects that the input timing deviation exceeds the range or no timing input is made, the abnormal state is reported, and the picture is switched to a dynamic picture preset in the FPGA, so as to avoid the picture abnormality.

In the thin film transistor liquid crystal panel, each liquid crystal pixel corresponds to at least one Thin Film Transistor (TFT) switch, which is turned on once in each frame to complete the recharging of the pixel capacitor, so as to complete the updating and displaying of the image. To turn on and off the TFT, a gate-on voltage VGH and a gate-off voltage VGL are required. Since the carrier mobility of the TFT is low, sufficient current needs to be supplied in order to charge the pixel capacitance to the required voltage through the TFT in a limited time; a very high voltage is provided so that it is much larger than the threshold voltage of the TFT. Normally, this voltage is between +15V and + 30V. Meanwhile, in order to rapidly turn off the TFT, the gate-off voltage VGL needs to be set to a value much smaller than its cut-off voltage, which is typically between-5V to-l 0V.

In the present application, the gate control chip 400 is electrically connected to the power conversion module 210 and the pixel power supply module 250, the pixel power supply module 250 controls the gate-on voltage VGH and the gate-off voltage VGL voltage signals of the active switch in the display panel 500, and the pixel power supply module 250 adopts a dedicated chip, which can provide both high voltage and low voltage; the power conversion module 210 provides a digital operating voltage for the gate control chip 400.

In addition, the timing control chip 200 further includes a communication interface circuit 270, and the communication interface circuit 270 is electrically connected to the FPGA module 230 and can receive data transmitted by an external computer through a serial port (RS-232); the FPGA module 230 includes a buffer chip (buffer IC), a Gamma voltage value is stored in the buffer chip, the buffer chip is electrically connected to the Gamma module 220 and the communication interface circuit 270, and the buffer chip adjusts the Gamma value of the Gamma module 220 through transmission data received by the communication interface circuit 270, so as to realize Gamma online adjustment.

According to the application, the FPGA module 230 and the peripheral circuit are combined in the time sequence control chip 200, besides the active monitoring function and the gamma online adjusting function of the circuit state are achieved, the parameter configurable function can be achieved through FPGA programming by adopting Verilog or VHDL language software, and therefore the reliability and the flexibility of the circuit are greatly improved, and the FPGA module 230, the time sequence control chip 200 and the display device 100 can be stably applied to the special display field, such as vehicle-mounted, ship-mounted and other high-temperature exposure and high-saline-alkali environment.

Fig. 2 shows an internal architecture diagram of a programmable module according to a first embodiment of the present application, and as shown in fig. 2, the FPGA module 230 further has a function of converting a video signal, so as to convert one video signal into another video signal, which can greatly improve the applicability of the display device 100 and meet the use requirements of various environments. Specifically, the FPGA module 230 includes a data signal decoding module 232, a signal processing module 233 and a data signal encoding module 234, the data signal decoding module 232 receives a first video signal, the signal processing module 233 converts the first video signal into an RGB signal, the data signal encoding module 234 converts the RGB signal into a second video signal, and inputs the second video signal into the source control chip 300; the first video screen signal and the second video screen signal are video signals with different formats.

Taking an example of converting a Low Voltage Differential Signaling (LVDS) signal into a Mini low voltage differential signaling (Mini-LVDS), the data signal decoding module 232 includes a low voltage differential signaling decoding module 2321, the first video screen signal is a Low Voltage Differential Signaling (LVDS), and the signal processing module 233 converts the low voltage differential signaling into an RGB signal; the data signal encoding module 234 includes a Mini low voltage differential signal encoding module 2341, the second video signal is a Mini low voltage differential signal (Mini-LVDS), and the Mini low voltage differential signal encoding module 2341 converts the RGB signal into a Mini low voltage differential signal.

Specifically, fig. 3 shows a schematic diagram of an operation of a data signal decoding module according to a first embodiment of the present application, as shown in fig. 3, a schematic diagram of an operation of the data signal decoding module 232 is shown, that is, a transistor Logic circuit (RTL) diagram of Low Voltage Differential Signaling (LVDS) decoding, in the diagram, the low voltage differential signaling decoding module 2321 includes a clock module 2322, a serial data conversion module 2323, a delay module, and a parallel data conversion module, and the clock module 2322(PLL module) receives the low voltage differential signaling and performs frequency multiplication on the low voltage differential signaling to generate X1 and X7 clock signals; the serial data conversion module 2323(rx _ data module) is electrically connected to the clock module 2322, and completes the functions of data delay and serial/parallel data conversion, and converts the clock signal into first serial data; the DELAY module (IO-DELAY2 module) performs DELAY processing on the first serial data to generate DELAY data; the parallel data conversion module (ISERDES2 module) converts the delay data into parallel data and inputs the parallel data to the signal processing module 233, generating parallel RGB signals.

Specifically, the low voltage differential signal decoding module 2321 is provided with a first pin 1, a second pin 2, a third pin 3, a fourth pin 4, a fifth pin 5, a thirtieth pin 30 and a thirty-first pin 31, where the first pin 1 is named as clkin _ n, the second pin 2 is named as clkin _ p, the third pin 3 is named as reset, the fourth pin 4 is named as datain _ n (3:0), the fifth pin 5 is named as datain _ p (3:0), the thirtieth pin 30 is named as rx _ data _ out, and the thirty-first pin 31 is named as clk _ out; and two ends of the low voltage differential signal decoding module 2321 are further provided with pins top _ lvds _ rx:1 and top _ lvds _ rx.

The clock module 2322 is provided with the following pins: a sixth pin 6, a seventh pin 7, an eighth pin 8, a ninth pin 9, a tenth pin 10, an eleventh pin 11, a twelfth pin 12, a thirteenth pin 13, a fourteenth pin 14, a fifteenth pin 15, a sixteenth pin 16, a seventeenth pin 17, and an eighteenth pin 18, the sixth pin 6 is named pattem1(4:0), the seventh pin 7 is named pattem2(4:0), the eighth pin 8 is named clkin _ n, the ninth pin 9 is named clkin _ p, the tenth pin 10 is named reset, the eleventh pin 11 is named datain (4:0), the twelfth pin 12 is named bitslip, the thirteenth pin 13 is named rxoclk, the fourteenth pin 14 is named rx _ bufg _ pll _ x1, the fifteenth pin 15 is named frx _ burkd, the sixteenth pin 16 is named fplcklux _ pllcll, and the seventeenth pin 17 is named vlcl _ 17, the eighteenth pin 18 is named rx _ serdestrobe. The eighth pin 8 is connected with the first pin 1 through a signal line, the ninth pin 9 is connected with the second pin 2 through a signal line, and the tenth pin 10 is connected with the third pin 3 through a signal line.

The serial data conversion module 2323 is provided with the following pins: a nineteenth pin 19, a twentieth pin 20, a twenty-first pin 21, a twenty-second pin 22, a twenty-third pin 23, a twenty-fourth pin 24, a twenty-fifth pin 25, a twenty-sixth pin 26, a twenty-seventh pin 27, a twenty-eighth pin 28, and a twenty-ninth pin 29, the nineteenth pin 19 is named datain _ n (3:0), the twentieth pin 20 is named datain _ p (3:0), the twenty-first pin 21 is named debug _ in (1:0), the twenty-second pin 22 is named bitslip, the twenty-third pin 23 is named gclk, the twenty-fourth pin 24 is named reset, the twenty-fifth pin 25 is named rxisoclk, the twenty-sixth pin 26 is named rxserdesbestrol, the twenty-seventh pin 27 is named use _ se _ dese, the twenty-eighth pin 28 is named data _ 19 (0), the twenty-ninth pin 29 is named debug (17: 0).

The nineteenth pin 19 is connected to the fourth pin 4 through a signal line, the twentieth pin 20 is connected to the fifth pin 5 through a signal line, the twenty-second pin 22 is connected to the twelfth pin 12 through a signal line, the twenty-third pin 23 is connected to the fourteenth pin 14 through a signal line, the fourteenth pin 14 is further connected to the thirty-first pin 31 through a signal line, the twenty-fourth pin 24 is connected to the fifteenth pin 15 through a signal line, the twenty-fifth pin 25 is connected to the thirteenth pin 13 through a signal line, the twenty-sixth pin 26 is connected to the eighteenth pin 18 through a signal line, and the twenty-eighth pin 28 is connected to the thirty-third pin 30 through a signal line.

Because of the error in the length of each Low Voltage Differential Signaling (LVDS) channel, there is a deviation in the phase between the associated clock and the serial data, and if not through phase adjustment, a sampling data error may occur because the requirements of setup time and hold time between data and clock cannot be met. To solve this problem, the present application uses a DELAY (IO-DELAY2) module to DELAY the input serial data to be sampled by the sample clk at the middle position, and the IO-DELAY2 outputs the delayed clock signal to be connected to the clkin _ n and clkin _ p connections. And finally, performing serial/parallel conversion on the delayed data through an ISERDES2 module. Finally, RGB, DEN, HSY and VSY signals are output by a pixel clock (DEN is used for controlling effective time of line display, the high level is the output time of effective data of the line, the high level of HSY is effective, the data input signal of each line of pixels is periodically controlled, VSY is used for periodically controlling the data input signal of each column of pixels, and RGB is a color signal), and LVDS decoding is completed.

As for Mini-LVDS coding, the miniature low voltage differential signal coding module 2341 includes two reverse data conversion modules (OSERDESE2 modules), the OSERDESE2 module implements a parallel/serial conversion function, which is the reverse process of ISERDES 2; one of the OSERDESE2 modules is used as a master module (master), the other OSERDESE2 module is used as a slave module (slave), the two inverse data conversion modules are connected in a cascade manner, the received parallel RGB signals are converted into second serial data, and the second serial data form a micro low-voltage differential signal and are input into the source control chip 300.

Since the single OSERDESE2 and ISERDES2 modules support parallel/serial conversion of 4-bit data at most, in order to realize 8-bit data transmission, a cascade mode is needed to work. And two OSERDESE2 modules are cascaded through the SHIFTIN and SHIFTOUT pins. And simultaneously, the position mapping is carried out on the input parallel data according to the required serial data transmission sequence so as to ensure that the liquid crystal panel receives and displays correctly.

In addition, in fig. 2, the FPGA module 230 further includes a communication control module 235, an analog quantity control module 236, a nonvolatile storage quantity control module 237, a timing generation module (LCD timing generation module) 238, a peripheral circuit control module 239, and a main control module 240, the communication control module 235 is electrically connected to a communication interface circuit 270 in the timing control chip 200, and the communication interface circuit 270 may receive data transmitted from the outside through a serial port (RS232), so as to connect the FPGA module 230 to an external computer, thereby implementing Gamma online adjustment and receiving an exception report of processed data; the analog quantity control module 236 is electrically connected to the voltage detection module 260 through an SPI interface, and receives the voltage detected by the voltage detection module 260.

The nonvolatile storage amount control module 237 stores video standard parameters and standard voltage values corresponding to the voltage detection values, compares the input LVDS signals with the standard voltage values to see whether the input LVDS signals meet the standard values, and reads the input LVDS signals when the input LVDS signals are powered on, and mainly includes: hor Total, H Front Port, Hor Sync, H Back Port, Vor Total, V Front Port, Vor Sync, V Back Port, etc.; IIC data is transmitted between the IIC bus and the nonvolatile storage volume control module 237 through an IO interface; the LCD timing generation module 238 is connected to the gate control chip 400 to control the active switch in the display panel 500 to be turned on or off; the peripheral circuit control module 239 controls the power conversion module 210 to maintain or turn off the power supply, and controls signal input and output, thereby ensuring stable operation of the whole system.

The main control module 240 is electrically connected to the data signal decoding module 232, the signal processing module 233, the data signal encoding module 234, the communication control module 235, the analog quantity control module 236, the nonvolatile storage quantity control module 237, the LCD timing generation module 238 and the peripheral circuit control module 239, compares the stored video standard parameter with the first video signal received by the data signal decoding module 232, checks whether the first video signal meets the standard, compares the voltage detection value with the corresponding standard voltage value in the FPGA module 230, and controls the data output of the data signal decoding module 232, the signal processing module 233, the data signal encoding module 234, the communication control module 235, the analog quantity control module 236, the nonvolatile storage quantity control module 237, the LCD timing generation module 238 and the peripheral circuit control module 239.

By integrating multiple functional modules in the FPGA module 230, the area of the sequential control chip 200 is effectively simplified on the premise that the sequential control chip 200 satisfies multiple functions, power consumption can be reduced, and product competitiveness can be improved.

In addition, all the modules are controlled in the FPGA module through the main control module 240 so as to set and control parameters of the peripheral circuit and each logic module, communicate with the middle of the upper computer, control the time schedule controller by the upper computer and monitor the working state of the whole driving circuit. The main control module is realized in a state machine mode, the risk of program 'running away' in a software mode is avoided, and the safety and reliability of system operation are guaranteed.

The work flow of the FPGA module through the main control module is as follows: the peripheral circuit control module control system is powered on, after the FPGA module is loaded, a nonvolatile Memory control module (EEPROM) reads data, and after the data is Read, the main control module sets parameters. After the setting is finished, a peripheral circuit control module (IDLE) controls and controls the input of serial port data, at the moment, an LVDS decoding module or a communication control module receives the data, if the parameters need to be stored, the parameters are stored in a nonvolatile memory control module, and after the parameters are stored, the parameters are confirmed with the peripheral circuit control module; if the parameters do not need to be stored, the external short circuit/internal module is subjected to parameter setting, and the set parameters are confirmed with the peripheral circuit control module after the setting is finished. The peripheral circuit control module also controls state data to be input into the analog quantity control module to complete state analysis of the external circuit and the internal module or state needs to be fed back, and the state data serial port is fed back into the peripheral circuit control module; if the state does not need to be fed back, the external short circuit/internal module is adjusted and controlled, and after the control is finished, the external short circuit/internal module is confirmed with the peripheral circuit control module.

As another embodiment of the present application, a timing control chip in the display device is further disclosed, which is shown in fig. 1, and includes a power conversion module, a Gamma module, an FPGA module, a pixel power supply module, and a voltage detection module, where the power conversion module receives a power voltage and converts the power voltage into a power signal; the Gamma module is electrically connected with the power supply conversion module, receives a power supply signal and converts the power supply signal into Gamma voltage; the FPGA module receives a video signal and generates a data driving signal; the pixel power supply module receives a power supply signal and generates a grid driving signal; the voltage detection module is electrically connected with the power conversion module, the Gamma module and the pixel power supply module and is used for detecting the voltages in the power conversion module, the Gamma module and the pixel power supply module;

the FPGA module is electrically connected with the voltage detection module and the power supply conversion module, receives the voltage detected by the voltage detection module, forms a plurality of voltage detection values, compares the voltage detection values with corresponding standard voltage values in the FPGA module, and controls the power supply conversion module to maintain or turn off the power supply according to the comparison result.

The sequential control chip in the embodiment has the characteristics of high supporting display resolution, high circuit integration level, strong flexibility and the like, and compared with the traditional sequential control chip design, the sequential control chip further has the advantages that a circuit state monitoring circuit is additionally arranged, a driving circuit can be monitored in real time, and the reliability of the driving circuit is improved.

As another embodiment of the present application, a programmable module (FPGA module) is further disclosed, which is shown in fig. 2, and includes a low voltage differential signal decoding module, a signal processing module, a micro low voltage differential signal encoding module, a communication control module, an analog quantity control module, a nonvolatile storage quantity control module, an LCD timing generation module, a peripheral circuit control module, and a main control module, where the low voltage differential signal decoding module receives a low voltage differential signal; the signal processing module converts the low-voltage differential signal into an RGB signal; the miniature low-voltage differential signal coding module converts the RGB signals into miniature low-voltage differential signals and outputs source electrode driving signals; the communication control module receives data transmitted from the outside; the analog quantity control module receives a detected voltage detection value; the nonvolatile storage quantity control module stores video standard parameters and standard voltage values corresponding to the voltage detection values; the LCD time sequence generation module outputs a grid driving signal; the peripheral circuit control module outputs a power supply maintenance or shutdown signal.

The main control module is electrically connected with the low-voltage differential signal decoding module, the signal processing module, the miniature low-voltage differential signal encoding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the LCD time sequence generating module and the peripheral circuit control module, compares the stored video standard parameters with the low-voltage differential signals, checks whether the low-voltage differential signals meet the standard, compares the voltage detection value with a standard voltage value, and controls the data output of the low-voltage differential signal decoding module, the signal processing module, the miniature low-voltage differential signal encoding module, the communication control module, the analog quantity control module, the nonvolatile storage quantity control module, the LCD time sequence generating module and the peripheral circuit control module.

The FPGA module in the embodiment has the characteristics of multiple functions, high integration level, high performance and high stability, and is not only suitable for the time sequence control chip and the display device, but also suitable for other circuit designs. After the programmable module is combined with the display device, the signal transcoding function of the display device is realized through an integrated low-voltage differential signal decoding module, a signal processing module and a miniature low-voltage differential signal coding module in the programmable module, and the display device combined with the programmable module can receive external information through a communication control module in the programmable module and can perform online adjustment on a program in the display device through the programmable module; the monitoring and detection of the internal circuit of the display device are realized through an analog quantity control module, a nonvolatile storage quantity control module, an LCD time sequence generation module and a peripheral circuit control module in the programmable module, and the safety performance of the internal circuit of the display device is improved. According to the display device, the plurality of functional modules are integrated together and are uniformly controlled through the main control module, so that the internal circuit structure and the power consumption of the display device are effectively simplified, and the working efficiency is greatly improved.

It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced.

The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.