阅读说明：本技术 一种tft阵列基板及液晶显示屏 (TFT array substrate and liquid crystal display ) 是由 廖亿彬 万志强 于 2021-08-11 设计创作，主要内容包括：本发明公开一种TFT阵列基板及液晶显示屏,TFT阵列基板包括：基板；TFT膜层；驱动IC,包括多个输出引脚和多个输入引脚,多个输出引脚沿横向排成至少一排,各排输出引脚沿竖向排列且自中部至两端向远离显示区的方向排布,多个输入引脚位于输出引脚的两端,与输出引脚沿竖向排列,且位于输出引脚各端的输入引脚沿竖向排成至少一排,各排输入引脚沿横向排列,其中横向为显示区至非显示区方向,竖向与横向垂直；FPC绑定焊盘,设置在驱动IC的两端,与驱动IC沿竖向排列。本发明中,不用在驱动IC的外侧预留输入导线空间,从而缩小驱动IC外侧与FPC之间的距离,进而缩小TFT阵列基板在驱动IC一侧的非视区宽度。(The invention discloses a TFT array substrate and a liquid crystal display screen, wherein the TFT array substrate comprises: a substrate; a TFT film layer; the driving IC comprises a plurality of output pins and a plurality of input pins, wherein the output pins are arranged in at least one row along the transverse direction, the output pins of each row are vertically arranged and are arranged from the middle part to the two ends in the direction far away from the display area, the input pins are positioned at the two ends of the output pins and are vertically arranged with the output pins, the input pins positioned at the ends of the output pins are vertically arranged in at least one row along the vertical direction, the input pins of each row are horizontally arranged, the transverse direction is the direction from the display area to the non-display area, and the vertical direction is vertical to the transverse direction; and the FPC binding pads are arranged at two ends of the drive IC and are vertically arranged with the drive IC. In the invention, the space of the input lead wire is not reserved at the outer side of the drive IC, so that the distance between the outer side of the drive IC and the FPC is reduced, and the width of a non-visual area of the TFT array substrate at one side of the drive IC is further reduced.)

1. A TFT array substrate, comprising:

the display device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a display area and a non-display area positioned at the periphery of the display area;

the TFT film layer is formed in the display area of the substrate;

the driving IC is fixed in a non-display area of the substrate and comprises a plurality of output pins and a plurality of input pins, the output pins are arranged in at least one row along the transverse direction, the output pins in each row are arranged along the vertical direction and are distributed from the middle part to the two ends in the direction far away from the display area, the input pins in each row are positioned at the two ends of the output pins and are arranged along the vertical direction, the input pins at the ends of the output pins are arranged along the vertical direction into at least one row, the input pins in each row are arranged along the transverse direction, the transverse direction is the direction from the display area to the non-display area, and the vertical direction is perpendicular to the transverse direction;

the FPC bonding pads are arranged at two ends of the driving IC and are vertically arranged with the driving IC.

2. The TFT array substrate according to claim 1, wherein each row of the output pins comprises a plurality of middle pins located in a middle portion and a plurality of end pins located at two ends, wherein each of the middle pins has a same distance from the display area, and the distance between each of the end pins and the display area gradually increases from the middle portion to the two ends of each row of the output pins.

3. The TFT array substrate of claim 2, wherein in each row of the output pins, the number of the middle pins is greater than the number of the end pins at each end, and a vertical spacing between two adjacent middle pins is the same as a vertical spacing between two adjacent end pins.

4. The TFT array substrate of claim 3, wherein each of the middle leads extends in a lateral direction and each of the end leads extends in the lateral direction.

5. The TFT array substrate of claim 3, wherein each end of the output pins is provided with a row of the input pins, and each of the input pins is vertically equidistant from the output pins.

6. The TFT array substrate of claim 5, wherein a distance between each row of the input pins and the display area is greater than a minimum distance between the output pins and the display area.

7. The TFT array substrate of claim 6, wherein each of the input pins extends in a vertical direction.

8. The TFT array substrate of any one of claims 1-7, wherein the driver IC further comprises a registration mark located outside the output pin, wherein the outside of the output pin is a side away from the display area.

9. The TFT array substrate of claim 8, wherein the alignment marks are cross-shaped alignment marks and two alignment marks are provided.

10. A liquid crystal display screen, comprising a TFT array substrate and an FPC connected to the TFT array substrate, wherein the TFT array substrate is the TFT array substrate according to any one of claims 1 to 9, and the gold fingers of the FPC are located at both ends of the TFT array substrate.

Technical Field

The invention relates to the technical field of display, in particular to a TFT array substrate and a liquid crystal display screen.

Background

With the continuous improvement of the customer experience requirements of consumer electronic products, the requirements of the whole screen are continuously increased, and electronic products with narrow edges are more and more popular with customers.

In the current narrow-edge electronic product, as shown in fig. 1, the pin arrangement of the driver IC 2' on the TFT array substrate is as follows: the output pins 21 'and the input pins 22' are arranged in a plurality of rows along the direction from the viewing area to the non-viewing area of the electronic product, the output pins 21 'are close to the viewing area of the electronic product and the output pins 21' in each row are arranged in a straight line, and the input pins 22 'are far away from the viewing area of the electronic product and the input pins 22' in each row are also arranged in a straight line. The FPC binding position is located on the outer side, far away from the visual area of the electronic product, of the input pin. Thus, the wires connecting the FPC and the input pins 22 'of the driver IC 2' are located between the outer side of the driver IC2 'and the FPC, and the occupied space of the wires is large, so that the current electronic product is still large at the position of the driver IC 2'.

Disclosure of Invention

The invention discloses a TFT array substrate and a liquid crystal display screen, which are used for solving the problem that an electronic product is large in position of a drive IC in the prior art.

In order to solve the problems, the invention adopts the following technical scheme:

provided is a TFT array substrate including:

the display device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a display area and a non-display area positioned at the periphery of the display area;

the TFT film layer is formed in the display area of the substrate;

the driving IC is fixed in a non-display area of the substrate and comprises a plurality of output pins and a plurality of input pins, the output pins are arranged in at least one row along the transverse direction, the output pins in each row are arranged along the vertical direction and are distributed from the middle part to the two ends in the direction far away from the display area, the input pins in each row are positioned at the two ends of the output pins and are arranged along the vertical direction, the input pins at the ends of the output pins are arranged along the vertical direction into at least one row, the input pins in each row are arranged along the transverse direction, the transverse direction is the direction from the display area to the non-display area, and the vertical direction is perpendicular to the transverse direction;

the FPC bonding pads are arranged at two ends of the driving IC and are vertically arranged with the driving IC.

Optionally, each row of the output pins includes a plurality of middle pins located in the middle and a plurality of end pins located at both ends, where the distance between each middle pin and the display area is the same, and the distance between each end pin and the display area gradually increases from the middle to both ends of each row of the output pins.

Optionally, in each row of the output pins, the number of the middle pins is greater than that of the end pins at each end, and a vertical distance between two adjacent middle pins is the same as that between two adjacent end pins.

Optionally, each of the intermediate legs extends in a transverse direction, and each of the end legs extends in the transverse direction.

Optionally, each end of the output pin is provided with a row of the input pins, and the vertical distance between each input pin and the output pin is equal.

Optionally, a distance between each row of the input pins and the display area is greater than a minimum distance between each row of the input pins and the display area.

Optionally, each of the input pins extends in a vertical direction.

Optionally, the driver IC further includes a register located outside the output pin, where the outside of the output pin is a side far away from the display area.

Optionally, the alignment mark is a cross-shaped alignment mark and is provided with two.

The liquid crystal display screen comprises a TFT array substrate and an FPC connected with the TFT array substrate, wherein the TFT array substrate is any one of the TFT array substrate, and the golden fingers of the FPC are positioned at two ends of the TFT array substrate.

The technical scheme adopted by the invention can achieve the following beneficial effects:

the input lead of the drive IC input pin and the input lead of the FPC binding pad are positioned at two ends of the drive IC, so that the space of the input lead does not need to be reserved on the outer side of the drive IC, the distance between the outer side of the drive IC and the FPC is reduced, and the width of a non-visual area of the TFT array substrate on one side of the drive IC is reduced; output pin at drive IC middle part is comparatively close to the display area, the output pin in the drive IC outside comparatively keeps away from the display area, even connect output pin and base plate visual area drive line like this, the output wire of scanning line is when walking the line to one side, also be difficult for causing the cycle racing phenomenon, thereby can be nearer with output pin setting, it has more abundant arrangement space to make output wire simultaneously, can further reduce the distance between drive IC and the base plate visual area, and make input pin have more abundant arrangement space, it provides probably to arrange input pin for the both ends at output pin.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below to form a part of the present invention, and the exemplary embodiments and the description thereof illustrate the present invention and do not constitute a limitation of the present invention. In the drawings:

fig. 1 is a diagram illustrating a pin arrangement of a driver IC according to the prior art;

fig. 2 is a side view of a TFT array substrate according to an embodiment of the present invention;

fig. 3 is a front view of a TFT array substrate according to an embodiment of the present invention;

FIG. 4 is an enlarged view of portion A of FIG. 3;

fig. 5 is a schematic structural diagram of a driving IC according to an embodiment of the present invention.

Wherein the following reference numerals are specifically included in figures 1-5:

FPC-1'; a drive IC-2'; output pin-21'; input pin-22';

a substrate-1; a driver IC-2; FPC-3; an input lead-4; an output lead-5; a TFT film layer-6; an output pin-21; middle pin-211; end pin-212; input pin-22; FPC bond pad-23; and a counterpoint-24.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 2 to 5, the TFT array substrate of the present invention includes a substrate 1, a TFT film layer 6, a driver IC2, and FPC bonding pads 23 (shown in fig. 3). The middle of the substrate 1 is a display area, and the periphery is a non-display area. The TFT film layer 6 is plated on the display area of the substrate 1, and the structure is the same as usual. The driver IC2 is fixed in the non-display area of the substrate 1, and includes a plurality of output pins 21 and a plurality of input pins 22, the plurality of output pins 21 are arranged in at least one row along the horizontal direction (i.e., the display area to the non-display direction), the plurality of input pins 22 are located at two ends of the output pins 21, the plurality of input pins 22 at each end are arranged in at least one row along the vertical direction (perpendicular to the horizontal direction), the plurality of output pins 21 are arranged along the vertical direction, the plurality of output pins 21 are arranged from the middle to the two ends in the direction away from the display area, and the plurality of input pins 22 are arranged along the horizontal direction. The FPC bonding pads 23 are disposed at both ends of the driving IC2, and are vertically aligned with the driving IC 2.

The TFT array substrate is arranged in the above way, so that the input leads 4 connected with the input pins 22 of the driving IC2 and the FPC bonding pads 23 are positioned at two ends of the driving IC2, and thus, the space of the input leads 4 is not reserved at the outer side of the driving IC2, the distance between the outer side of the driving IC2 and the FPC3 is reduced, and the non-visual area width of the TFT array substrate at one side of the driving IC2 is reduced; the output pin 21 in the middle of the driver IC2 is closer to the display area, and the output pin 21 outside the driver IC2 is farther from the display area, so that even if the output wire 5 connecting the output pin 21 and the drive line and the scan line of the viewing area of the substrate 1 is obliquely routed, racing is not easily caused, and the output pin 21 can be set closer, and meanwhile, the output wire 5 has a more spacious arrangement space, so that the distance between the driver IC2 and the viewing area of the substrate 1 can be further reduced, and the input pin 22 has a more spacious arrangement space, thereby providing possibility for arranging the input pins 22 at two ends of the output pin 21.

The further arrangement of the rows of output pins 21 is: the plurality of output pins 21 in the middle are arranged in a line along a vertical straight line, and the plurality of output pins 21 at both ends are arranged in a line obliquely in a direction gradually away from the display area. That is, each row of the output pins 21 includes a plurality of middle pins 211 located in the middle and a plurality of end pins 212 located at both ends, the middle pins 211 are vertically arranged in a row at the same distance from the display area, and the end pins 212 are obliquely arranged in a row at an increasing distance from the display area in the direction from the middle to both ends of the driver IC 2. Wherein the lateral distance between two adjacent end pins 212 can be set according to requirements. In this way, the middle leads 211 and the end leads 212 may extend in the lateral direction, that is, the extending direction of the middle leads 211 and the end leads 212 may be perpendicular to the display area of the substrate 1, so as to facilitate the processing and manufacturing of the leads.

Further, in each row of the output pins 21, the number of the middle pins 211 is greater than the number of the end pins 212 at each end, and the vertical distance between two adjacent middle pins 211 is the same as the vertical distance between two adjacent end pins 212, so that the total length of the middle pins 211 in the vertical direction is greater than the total length of the end pins 212 at each end in the vertical direction, that is, in each row of the output pins 21, the vertical total length of the driving IC2 occupied by the middle pins 211 is greater than the vertical total length of the driving IC2 occupied by the end pins 212 at each end, that is, the vertical distance between the middle pins 211 at two ends is greater than the vertical distance between the end pins 212 at two ends at the same end. This reduces the likelihood of racing of the output leads 5 connected to the end pins 212, while facilitating the placement of the input pins 22 in a limited space to avoid racing of the input leads 4.

When at least two rows of output pins 21 are provided, the output pins 21 in two adjacent rows are offset from each other. The output wires 5 connected to the rows of output pins 21 far from the display area of the substrate 1 extend along a horizontal straight line to exceed the row of output pins 21 closest to the display area, and then extend obliquely to be connected to the driving lines or scanning lines inside the substrate 1.

A row of input pins 22 is arranged at each end of the output pins 21, and the vertical distance between each input pin 22 and the output pin 21 is equal. And the distance between each row of input pins 22 and the display area is greater than the minimum distance between the output pins 21 and the display area, i.e. the distance between the input pin 22 closest to the display area and the display area is greater than the distance between the middle pin 211 and the display area. And each input pin 22 extends in the vertical direction, i.e., the input pin 22 is arranged perpendicular to the output pin 21. And the interval between two adjacent input pins 22 is larger than the interval between two adjacent output pins 21 (i.e., two adjacent intermediate pins 211 or two adjacent end pins 212). So configured, the maximum number of input pins 22 can be arranged in a limited space, while avoiding racing of the input wires 4.

Of course, in other embodiments, the rows of output pins 21 may also be arranged in an arc shape, and the output pins 21 are disposed obliquely, for example, the angle between each output pin 21 and the vertical direction is 75 °. Alternatively, the input pins 22 at each end are arranged in at least two pieces, and the input pins 22 in two adjacent rows are laterally displaced.

The driver IC2 further includes a registration mark 24, and when the driver IC2 is attached to the substrate 1, the driver IC2 is registered by the registration mark 24. The alignment mark 24 is located outside the outermost row of output pins 21. The indices 24 may be cross-shaped indices 24, two on the driver IC 2. And, the index 24 overlaps with the end pin 212 in the vertical direction, and the index 24 is close to the middle pin 211 with respect to the end pin 212 at the end. So set up, simple structure is compact, improves the location accuracy.

The liquid crystal display device comprises a TFT array substrate and an FPC3 connected with the TFT array substrate, wherein the TFT array substrate is the TFT array substrate, and the golden fingers of the FPC3 are positioned at two ends of the TFT array substrate. In the liquid crystal display device, the input leads 4 connecting the input pins 22 of the driving IC2 and the FPC bonding pads 23 are positioned at two ends of the driving IC2, so that the space of the input leads 4 is not reserved outside the driving IC2, the distance between the outside of the driving IC2 and the FPC3 is reduced, and the non-visual area width of the TFT array substrate on one side of the driving IC2 is reduced; the output pin 21 in the middle of the driver IC2 is closer to the display area, and the output pin 21 outside the driver IC2 is farther from the display area, so that even if the output wire 5 connecting the output pin 21 and the drive line and the scan line of the viewing area of the substrate 1 is obliquely routed, racing is not easily caused, and the output pin 21 can be set closer, and meanwhile, the output wire 5 has a more spacious arrangement space, so that the distance between the driver IC2 and the viewing area of the substrate 1 can be further reduced, and the input pin 22 has a more spacious arrangement space, thereby providing possibility for arranging the input pins 22 at two ends of the output pin 21.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.