阅读说明：本技术 一种高密度智能网卡、fpga及其工作方法 (High-density intelligent network card, FPGA and working method thereof ) 是由 郑冠儒 韩威 薛广营 于 2021-08-30 设计创作，主要内容包括：本申请公开了一种高密度智能网卡,包括FPGA,网口,PCIE接口,SOC设备,SODIMM内存,其中FPGA用于分别接收来自SOC设备的内存访问请求和来自网口的内存访问请求,区分来自SOC设备的内存访问请求和来自网口的内存访问请求,将来自SOC设备的内存访问请求发送至SODIMM内存,得到请求数据并反馈至SOC设备。可见,相比于传统的智能网卡架构,本申请将FPGA的内存和SOC设备的内存池化,节省了板卡上硬件的空间,简化了硬件设计,提高了硬件设计的效率。此外,本申请还提供了一种应用于高密度智能网卡的FPGA、高密度智能网卡中FPGA的工作方法,其技术效果与上述高密度智能网卡的技术效果相对应。(The application discloses a high-density intelligent network card, which comprises an FPGA, a network port, a PCIE interface, an SOC device and an SODIMM memory, wherein the FPGA is used for respectively receiving a memory access request from the SOC device and a memory access request from the network port, distinguishing the memory access request from the SOC device from the memory access request from the network port, sending the memory access request from the SOC device to the SODIMM memory, obtaining request data and feeding the request data back to the SOC device. Therefore, compared with the traditional intelligent network card architecture, the method and the system have the advantages that the memory of the FPGA and the memory of the SOC device are pooled, the space of hardware on the board card is saved, the hardware design is simplified, and the hardware design efficiency is improved. In addition, the application also provides an FPGA applied to the high-density intelligent network card and a working method of the FPGA in the high-density intelligent network card, and the technical effect of the FPGA is corresponding to that of the high-density intelligent network card.)

1. A high-density intelligent network card, comprising: the system comprises an FPGA, a network interface, a PCIE interface, an SOC device and an SODIMM memory;

the network port is used for communicating the FPGA with external equipment; the PCIE interface is used for communicating the FPGA and the uplink server equipment; the SODIMM memory and the SOC equipment are interconnected with the FPGA; the FPGA is used for respectively receiving a memory access request from the SOC device and a memory access request from the network port, distinguishing the memory access request from the SOC device from the memory access request from the network port, sending the memory access request from the SOC device to the SODIMM memory, obtaining request data and feeding the request data back to the SOC device.

2. The high-density intelligent network card of claim 1, wherein the FPGA comprises: the system comprises a memory message exchange module, a memory control module, a Slave memory module and a network module;

the Slave memory module receives a memory access request sent by the SOC device and sends the memory access request to the memory message exchange module; the memory message exchange module identifies a memory access request from the SOC device or the network module and sends the memory access request to the memory control module; the memory control module realizes the access to the SODIMM memory according to the memory access request, feeds back the request data returned by the SODIMM memory to the memory message exchange module, and feeds back the request data to the network module or the Slave memory module through identifying message information after the memory exchange module receives the request data; and the Slave memory module feeds the request data back to the SOC equipment.

3. The high-density intelligent network card of claim 2, wherein the FPGA further comprises: the network interface control module and the PCIE module;

the network port control module is used for communicating the network port with the network module; the PCIE module is used for communicating the PCIE interface and the network module.

4. The high-density intelligent network card of claim 2, wherein the Slave memory module is interconnected with an SOC memory control interface for providing a network interface to the SOC device.

5. The high-density intelligent network card of claim 4, wherein the SOC memory control interface is a QSFP28 interface.

6. A working method of FPGA in a high-density intelligent network card is characterized in that the high-density intelligent network card comprises a network port, a PCIE interface, SOC equipment and an SODIMM memory, wherein the network port is used for communicating the FPGA with external equipment, and the PCIE interface is used for communicating the FPGA with uplink server equipment, and the method comprises the following steps:

respectively receiving a memory access request from the SOC equipment and a memory access request from the network port;

distinguishing a memory access request from the SOC device from a memory access request from the network port;

and sending the memory access request from the SOC equipment to the SODIMM memory to obtain request data and feeding the request data back to the SOC equipment.

7. The method according to claim 6, wherein the FPGA comprises a memory message exchange module, a Slave memory module, and a network module, and the receiving of the memory access request from the SOC device and the memory access request from the network port are performed respectively; distinguishing a memory access request from the SOC device from a memory access request from the portal, comprising:

controlling the Slave memory module to receive a memory access request sent by the SOC device and sending the memory access request to the memory message exchange module;

and controlling the memory message exchange module to identify a memory access request from the SOC equipment or from the network module.

8. The method according to claim 7, wherein the FPGA further comprises a memory control module, and the memory access request from the SOC device is sent to the SODIMM memory to obtain request data and feed the request data back to the SOC device, and the method comprises:

controlling the memory message exchange module to send the memory access request to the memory control module;

controlling the memory control module to realize the access to the SODIMM memory according to the memory access request, and feeding back request data returned by the SODIMM memory to the memory message exchange module;

after receiving the request data, controlling the memory exchange module to feed back the request data to a network module or the Slave memory module through identification message information;

and controlling the Slave memory module to feed the request data back to the SOC equipment.

9. The method for operating FPGA in high-density intelligent network card according to claim 7, further comprising:

and controlling the Slave memory module to provide a network interface for the SOC equipment through an SOC memory control interface.

10. The FPGA is applied to a high-density intelligent network card, and is characterized in that the high-density intelligent network card comprises a network port, a PCIE interface, an SOC device and an SODIMM memory, wherein the network port is used for communicating the FPGA with an external device, the PCIE interface is used for communicating the FPGA with an uplink server device, and the SODIMM memory and the SOC device are interconnected with the FPGA;

the FPGA is used for respectively receiving a memory access request from the SOC device and a memory access request from the network port, distinguishing the memory access request from the SOC device from the memory access request from the network port, sending the memory access request from the SOC device to the SODIMM memory, obtaining request data and feeding the request data back to the SOC device.

Technical Field

The application relates to the technical field of computers, in particular to a high-density intelligent network card, an FPGA (field programmable gate array) applied to the high-density intelligent network card and a working method of the FPGA in the high-density intelligent network card.

Background

With the development of a data center network architecture, the concept of an intelligent network card is developed to solve the problem of network flow resource consumption caused by data center virtualization. The intelligent network card unloads network flow between the virtual machines on the server to the network card, so that precious computing resources in the server are released.

Currently, the mainstream intelligent network card architecture is implemented by SOC + FPGA, as shown in fig. 1, the FPGA provides a service channel to the outside through a network port, the FPGA is interconnected with an uplink device through a PCIE interface, a set of DRAM memory is set under the FPGA, the FPGA and the SOC are interconnected through a set of interface, and an SODIMM memory is set under the SOC. The architecture has convenient service deployment and strong expansibility. However, the hardware design needs to occupy a large amount of hardware space, and the further development of the limited network card space is limited.

Therefore, a high-density intelligent network card architecture is needed to release the limited hardware space on the card and increase the capacity of the card.

Disclosure of Invention

The application aims to provide a high-density intelligent network card, an FPGA applied to the high-density intelligent network card and a working method of the FPGA in the high-density intelligent network card, and the method is used for solving the problem of hardware layout tension caused by more peripheral devices of the existing intelligent network card. The specific scheme is as follows:

in a first aspect, the present application provides a high-density intelligent network card, including: the system comprises an FPGA, a network interface, a PCIE interface, an SOC device and an SODIMM memory;

the network port is used for communicating the FPGA with external equipment; the PCIE interface is used for communicating the FPGA and the uplink server equipment; the SODIMM memory and the SOC equipment are interconnected with the FPGA; the FPGA is used for respectively receiving a memory access request from the SOC device and a memory access request from the network port, distinguishing the memory access request from the SOC device from the memory access request from the network port, sending the memory access request from the SOC device to the SODIMM memory, obtaining request data and feeding the request data back to the SOC device.

Optionally, the FPGA includes: the system comprises a memory message exchange module, a memory control module, a Slave memory module and a network module;

the Slave memory module receives a memory access request sent by the SOC device and sends the memory access request to the memory message exchange module; the memory message exchange module identifies a memory access request from the SOC device or the network module and sends the memory access request to the memory control module; the memory control module realizes the access to the SODIMM memory according to the memory access request, feeds back the request data returned by the SODIMM memory to the memory message exchange module, and feeds back the request data to the network module or the Slave memory module through identifying message information after the memory exchange module receives the request data; and the Slave memory module feeds the request data back to the SOC equipment.

Optionally, the FPGA further includes: the network interface control module and the PCIE module;

the network port control module is used for communicating the network port with the network module; the PCIE module is used for communicating the PCIE interface and the network module.

Optionally, the Slave memory module is interconnected with the SOC memory control interface, and is configured to provide a network interface for the SOC device.

Optionally, the SOC memory control interface is a QSFP28 interface.

In a second aspect, the present application provides a method for operating an FPGA in a high-density intelligent network card, where the high-density intelligent network card includes a network interface, a PCIE interface, an SOC device, and an SODIMM memory, where the network interface is used to communicate the FPGA with an external device, and the PCIE interface is used to communicate the FPGA with an uplink server device, and the method includes:

respectively receiving a memory access request from the SOC equipment and a memory access request from the network port;

distinguishing a memory access request from the SOC device from a memory access request from the network port;

and sending the memory access request from the SOC equipment to the SODIMM memory to obtain request data and feeding the request data back to the SOC equipment.

Optionally, the FPGA includes a memory message exchange module, a Slave memory module, and a network module, and the network module receives the memory access request from the SOC device and the memory access request from the network interface, respectively; distinguishing a memory access request from the SOC device from a memory access request from the portal, comprising:

controlling the Slave memory module to receive a memory access request sent by the SOC device and sending the memory access request to the memory message exchange module;

and controlling the memory message exchange module to identify a memory access request from the SOC equipment or from the network module.

Optionally, the FPGA further includes a memory control module, which sends the memory access request from the SOC device to the SODIMM memory, obtains request data, and feeds back the request data to the SOC device, and includes:

controlling the memory message exchange module to send the memory access request to the memory control module;

controlling the memory control module to realize the access to the SODIMM memory according to the memory access request, and feeding back request data returned by the SODIMM memory to the memory message exchange module;

after receiving the request data, controlling the memory exchange module to feed back the request data to a network module or the Slave memory module through identification message information;

and controlling the Slave memory module to feed the request data back to the SOC equipment.

Optionally, the method further includes:

and controlling the Slave memory module to provide a network interface for the SOC equipment through an SOC memory control interface.

In a third aspect, the present application provides an FPGA applied to a high-density intelligent network card, where the high-density intelligent network card includes a network port, a PCIE interface, an SOC device, and an SODIMM memory, where the network port is used to communicate the FPGA and an external device, the PCIE interface is used to communicate the FPGA and an uplink server device, and the SODIMM memory and the SOC device are both interconnected with the FPGA;

the FPGA is used for respectively receiving a memory access request from the SOC device and a memory access request from the network port, distinguishing the memory access request from the SOC device from the memory access request from the network port, sending the memory access request from the SOC device to the SODIMM memory, obtaining request data and feeding the request data back to the SOC device.

The application provides a high density intelligence network card, including FPGA, net gape, PCIE interface, SOC equipment, SODIMM memory, wherein, the net gape is used for communicateing FPGA and external device, and the PCIE interface is used for communicateing FPGA and going upward server equipment, and SODIMM memory and SOC equipment all interconnect with FPGA. The FPGA is used for respectively receiving a memory access request from the SOC device and a memory access request from the network port, distinguishing the memory access request from the SOC device from the memory access request from the network port, sending the memory access request from the SOC device to the SODIMM memory, obtaining request data and feeding the request data back to the SOC device. Therefore, compared with the traditional intelligent network card architecture, the method and the system have the advantages that the memory of the FPGA and the memory of the SOC device are pooled, the space of hardware on the board card is saved, the hardware design is simplified, and the hardware design efficiency is improved.

In addition, the application also provides an FPGA applied to the high-density intelligent network card and a working method of the FPGA in the high-density intelligent network card, and the technical effect of the FPGA corresponds to that of the high-density intelligent network card, and the description is omitted here.

Drawings

For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 illustrates a conventional smart card architecture;

FIG. 2 is a block diagram of a high-density smart card architecture according to the present application;

FIG. 3 is a block diagram of an internal software architecture of an FPGA provided herein;

fig. 4 is a data processing flow of the high-density intelligent network card provided by the present application;

fig. 5 is a flowchart of an embodiment of a method for operating an FPGA in the high-density intelligent network card provided in the present application.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The application provides a high-density intelligent network card, an FPGA applied to the high-density intelligent network card and a working method of the FPGA in the high-density intelligent network card, solves the problem of tense hardware layout caused by more peripherals on the network card, reduces the development difficulty of hardware equipment, and achieves the purposes of improving the production efficiency and saving the development cost.

Referring to fig. 2, a first embodiment of the high-density intelligent network card provided by the present application is described below, where the first embodiment includes an FPGA, a network port, a PCIE interface, an SOC device, and an SODIMM memory;

the network port is used for communicating the FPGA with external equipment; the PCIE interface is used for communicating the FPGA and the uplink server equipment; the SODIMM memory and the SOC equipment are interconnected with the FPGA; the FPGA is used for respectively receiving a memory access request from the SOC device and a memory access request from the network port, distinguishing the memory access request from the SOC device from the memory access request from the network port, sending the memory access request from the SOC device to the SODIMM memory, obtaining request data and feeding the request data back to the SOC device.

As a specific implementation mode, the FPGA selects an Agilex chip of Intel to realize, a Molex QSFP28 network port is selected to be used by the network port, the SOC device selects a Xeon D series chip of Intel to realize, the SODIMM memory selects a 16GB ECC memory of Micron, and the PCIE interface is a GEN4 x16 interface. The FPGA provides a 100G network interface to the outside through a QSFP28 interface, the FPGA is interconnected with the SOC equipment, and the FPGA hangs a 16GB SODIMM memory of the Micron to respond to the memory resource requests of the FPGA and the SOC.

The embodiment provides a high-density intelligent network card, which comprises an FPGA, a network port, a PCIE interface, an SOC device and an SODIMM memory.

The second embodiment of the high-density intelligent network card provided by the present application is described in detail below, and referring to fig. 3, the FPGA in the second embodiment includes: the system comprises a memory message exchange module, a memory control module, a Slave memory module and a network module;

the Slave memory module receives a memory access request sent by the SOC device and sends the memory access request to the memory message exchange module; the memory message exchange module identifies a memory access request from the SOC device or the network module and sends the memory access request to the memory control module; the memory control module realizes the access to the SODIMM memory according to the memory access request, and feeds back the request data returned by the SODIMM memory to the memory message exchange module, and after receiving the request data, the memory exchange module feeds back the request data to the network module or the Slave memory module through identifying message information; and the Slave memory module feeds the request data back to the SOC equipment.

As a specific implementation, the FPGA further includes: the network interface control module and the PCIE module; the network port control module is used for communicating the network port with the network module, and the PCIE module is used for communicating the PCIE interface with the network module.

Specifically, the Slave memory module is interconnected with the SOC memory control interface, and is configured to provide a network interface for the SOC device.

The embodiment provides a software architecture block diagram inside an FPGA, and as shown in fig. 3, the software architecture block includes a memory message exchange module, a memory control module, a Slave memory module, a network interface control module, and a PCIE module. The memory message exchange module can identify the message from the network module and the message from the Slave memory module, and feed back the corresponding processing results to the network module or the Slave memory module respectively.

Specifically, as shown in fig. 4, after starting, the FPGA completes initialization of each module, and then waits for the SOC to send a request for accessing the memory, after receiving the request sent by the SOC, the slave memory module of the FPGA sends a message to the memory message exchange module, the memory message exchange module may identify a message from the SOC or from the network module and send the request to the memory control module, and the memory control module completes access to the sodim memory and feeds back data returned by the sodim memory to the memory message exchange module. After the memory message exchange module receives the data, the message is fed back to the network module or the Slave memory module by identifying the message information, and finally the Slave memory module feeds back the taken data to the SOC, thereby ending the whole process.

It can be seen that, compared with the traditional intelligent network card architecture, the high-density intelligent network card provided by this embodiment pools the memory of the FPGA and the memory of the SOC by the design of the memory message exchange module in the FPGA, saves the space of hardware on the board card, simplifies the hardware design, improves the efficiency of the hardware design, and brings benefits to enterprises.

The technical key point of the embodiment is that the idea of resource pooling is applied to the intelligent network card, the design of sharing the memory resource by the FPGA and the SOC is realized through the design of the memory message exchange module in the FPGA innovatively, and the scheme is not proposed in the previous hardware design.

The working method of the FPGA in the high-density intelligent network card provided in the embodiment of the present application is introduced below, and the working method of the FPGA in the high-density intelligent network card described below and the high-density intelligent network card described above may be referred to correspondingly.

The embodiment provides a working method of an FPGA in a high-density intelligent network card, where the high-density intelligent network card includes a network port, a PCIE interface, an SOC device, and an SODIMM memory, where the network port is used to communicate the FPGA with an external device, and the PCIE interface is used to communicate the FPGA with an uplink server device, and as shown in fig. 5, the method includes:

s51, respectively receiving a memory access request from the SOC device and a memory access request from the network port;

s52, distinguishing a memory access request from the SOC device from a memory access request from the network port;

and S53, sending the memory access request from the SOC device to the SODIMM memory, obtaining the request data and feeding the request data back to the SOC device.

In some specific embodiments, the FPGA includes a memory message exchange module, a Slave memory module, and a network module, which respectively receive a memory access request from the SOC device and a memory access request from the network port; distinguishing a memory access request from an SOC device from a memory access request from a portal, comprising:

the Slave memory control module receives a memory access request sent by the SOC device and sends the memory access request to the memory message exchange module;

and the control memory message exchange module identifies a memory access request from the SOC equipment or from the network module.

In some specific embodiments, the FPGA further includes a memory control module, and the sending the memory access request from the SOC device to the sodim memory to obtain the request data and feed back the request data to the SOC device includes:

controlling the memory message exchange module to send the memory access request to the memory control module;

the control memory control module realizes the access to the SODIMM memory according to the memory access request and feeds back the request data returned by the SODIMM memory to the memory message exchange module;

after receiving the request data, controlling the memory exchange module to feed back the request data to the network module or the Slave memory module through the identification message information;

and controlling the Slave memory module to feed back the request data to the SOC equipment.

In some specific embodiments, the method further comprises:

and the control Slave memory module provides a network interface for the SOC equipment through the SOC memory control interface.

The working method of the FPGA in the high-density intelligent network card of this embodiment is implemented based on the high-density intelligent network card, so that specific implementation of the method can be found in the embodiment of the high-density intelligent network card described above, and is not described here again.

In addition, the application also provides an FPGA applied to the high-density intelligent network card, the high-density intelligent network card comprises a network port, a PCIE interface, an SOC device and an SODIMM memory, wherein the network port is used for communicating the FPGA with an external device, the PCIE interface is used for communicating the FPGA with an uplink server device, and the SODIMM memory and the SOC device are interconnected with the FPGA;

the FPGA is used for respectively receiving a memory access request from the SOC device and a memory access request from the network port, distinguishing the memory access request from the SOC device from the memory access request from the network port, sending the memory access request from the SOC device to the SODIMM memory, obtaining request data and feeding the request data back to the SOC device.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The above detailed descriptions of the solutions provided in the present application, and the specific examples applied herein are set forth to explain the principles and implementations of the present application, and the above descriptions of the examples are only used to help understand the method and its core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.