阅读说明：本技术 显示面板和包括该显示面板的显示装置 (Display panel and display device including the same ) 是由 罗釉美 朴径浩 文盛载 于 2021-05-31 设计创作，主要内容包括：本发明公开了显示面板和包括该显示面板的显示装置。显示面板包括：多个被划分的驱动部分,其中,多个被划分的驱动部分中的至少一个被划分的驱动部分包括：在第一方向上延伸的第一连接线；在第一方向上延伸并且在与第一方向交叉的第二方向上与第一连接线间隔开的第二连接线；在第二方向上延伸并且电连接到第一连接线的第一栅线；在第二方向上延伸、与第一栅线间隔开并且电连接到第二连接线的第二栅线；在第一像素列和第一像素行中并且电连接到第一栅线的第一像素；以及在第一像素列和第二像素行中并且电连接到第二栅线的第二像素。(The invention discloses a display panel and a display device including the same. The display panel includes: a plurality of divided driving parts, wherein at least one of the plurality of divided driving parts includes: a first connecting line extending in a first direction; a second connection line extending in the first direction and spaced apart from the first connection line in a second direction crossing the first direction; a first gate line extending in a second direction and electrically connected to the first connection line; a second gate line extending in a second direction, spaced apart from the first gate line, and electrically connected to the second connection line; a first pixel in the first pixel column and the first pixel row and electrically connected to the first gate line; and a second pixel in the first pixel column and the second pixel row and electrically connected to the second gate line.)

1. A display panel, comprising:

a plurality of divided driving parts, wherein at least one of the plurality of divided driving parts includes:

a first connecting line extending in a first direction;

a second connection line extending in the first direction and spaced apart from the first connection line in a second direction crossing the first direction;

a first gate line extending in the second direction and electrically connected to the first connection line;

a second gate line extending in the second direction, spaced apart from the first gate line, and electrically connected to the second connection line;

a first pixel in a first pixel column and a first pixel row and electrically connected to the first gate line; and

a second pixel in the first pixel column and a second pixel row and electrically connected to the second gate line, wherein the second pixel row is spaced apart from the first pixel row in the first direction, and

wherein the first connection line and the second connection line correspond to the first pixel column.

2. The display panel of claim 1, wherein the at least one divided driving part further comprises a high power supply voltage line extending in the first direction, and

the high power supply voltage line corresponds to the first pixel column.

3. The display panel of claim 2, wherein the at least one divided driving part further includes at least one data line extending in the first direction, and

wherein the at least one data line corresponds to the first pixel column and is electrically connected to the first pixel and the second pixel.

4. The display panel according to claim 3, wherein the second connection line is between the first connection line and the first pixel in a plan view.

5. The display panel of claim 4, wherein the at least one divided driving portion further comprises a low supply voltage line extending in the first direction and spaced apart from the high supply voltage line in the second direction, and

wherein, in the plan view, the first connection line and the second connection line are between the high power supply voltage line and the low power supply voltage line.

6. The display panel of claim 3, wherein the first pixel comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel, and

wherein the at least one data line includes first to third data lines spaced apart from each other in the second direction and electrically connected to the first to third sub-pixels, respectively.

7. The display panel according to claim 3, wherein the first connection line is between the second connection line and the first pixel in a plan view.

8. The display panel according to claim 3, wherein the at least one data line is between the first pixel and the first connection line in a plan view.

9. The display panel according to claim 3, wherein the first connection line and the second connection line are between the first pixel and the at least one data line in a plan view.

10. The display panel according to any one of claims 1 to 9, wherein the at least one divided driving section further includes a dummy line extending in the first direction and in the same layer as the first connection line and the second connection line,

wherein a gate signal is supplied to each of the first connection line and the second connection line, and

wherein a constant voltage is supplied to the dummy line.

11. A display device, comprising:

a display panel including a plurality of divided driving parts and in a display area;

a gate driver in a non-display area adjacent to the display area;

a data driver in the non-display area; and

a timing controller in the non-display area and configured to control the gate driver and the data driver,

wherein at least one divided driving part of the plurality of divided driving parts includes:

a first connecting line extending in a first direction;

a second connection line extending in the first direction and spaced apart from the first connection line in a second direction crossing the first direction;

a first gate line extending in the second direction and electrically connected to the first connection line;

a second gate line extending in the second direction, spaced apart from the first gate line, and electrically connected to the second connection line;

a first pixel in a first pixel column and a first pixel row and electrically connected to the first gate line; and

a second pixel in the first pixel column and a second pixel row and electrically connected to the second gate line, wherein the second pixel row is spaced apart from the first pixel row in the first direction, and

wherein the first connection line and the second connection line correspond to the first pixel column.

12. The display device according to claim 11, wherein the gate driver and the data driver are in the non-display region adjacent to one side of the display panel.

Technical Field

Aspects of some example embodiments of the present invention relate generally to a display panel and a display apparatus including the same.

Background

A display device generally includes a display panel and a driver disposed adjacent to one side (e.g., left side) of the display panel. The display panel includes pixels and driving lines for transmitting driving signals generated from a driver. Recently, as the size of display devices is gradually increased, the transmission time of driving signals transmitted to pixels distant from a driver may be relatively delayed. In order to solve this problem, a structure has been developed in which an additional driver is additionally disposed at the other side (for example, the right side) opposite to the one side of the display panel, but the structure increases the bezel of the display device.

The above information disclosed in this background section is only for enhancement of understanding of the background, and therefore, the information discussed in this background section does not necessarily constitute prior art.

Disclosure of Invention

Aspects of some example embodiments of the present invention relate generally to a display panel and a display apparatus including the same. For example, an aspect of some example embodiments of the present invention relates to a display panel including a connection line.

Aspects of some example embodiments include a gate test portion having a reduced transmission time and a reduced bezel.

Aspects of some example embodiments include a display device including the display panel.

The display panel according to some example embodiments may include a plurality of divided driving parts. The at least one divided driving part of the plurality of divided driving parts may include: a first connecting line extending in a first direction; a second connection line extending in the first direction and spaced apart from the first connection line in a second direction crossing the first direction; a first gate line extending in a second direction and electrically connected to the first connection line; a second gate line extending in a second direction, spaced apart from the first gate line, and electrically connected to the second connection line; a first pixel in the first pixel column and the first pixel row and electrically connected to the first gate line; and a second pixel in the first pixel column and the second pixel row and electrically connected to the second gate line, wherein the second pixel row is spaced apart from the first pixel row in the first direction. The first connection line and the second connection line may be arranged to correspond to the first pixel column.

According to some example embodiments, the at least one divided driving part may further include a high power supply voltage line extending in the first direction, and the high power supply voltage line may be arranged to correspond to the first pixel column.

According to some example embodiments, the at least one divided driving part may further include at least one data line extending in the first direction. The data line may be arranged to correspond to the first pixel column and may be electrically connected to the first pixel and the second pixel.

According to some example embodiments, the second connection line may be between the first connection line and the first pixel on a plane.

According to some example embodiments, the first pixel may be between the second connection line and the data line on a plane.

According to some example embodiments, the at least one divided driving part may further include a low power supply voltage line extending in the first direction and may be spaced apart from the high power supply voltage line in the second direction. The first and second connection lines may be between the high and low supply voltage lines on the plane.

According to some example embodiments, the high supply voltage line may be between the second connection line and the first pixel on a plane.

According to some example embodiments, the first pixel may include first, second, and third sub-pixels, and the data line may include first to third data lines spaced apart from each other in the second direction and may be electrically connected to the first to third sub-pixels, respectively.

According to some example embodiments, the first subpixel may include a substrate, an active pattern on the substrate, a gate electrode on the active pattern, and a connection electrode on the gate electrode. The first gate line may be in the same layer as the connection electrode, and the first gate line may contact the first connection line through a first contact hole exposing the first connection line overlapping the first gate line.

According to some example embodiments, the first connection line may include a first metal pattern, and the first metal pattern may be between the substrate and the active pattern and may extend in the first direction.

According to some example embodiments, the first connection line may further include a second metal pattern, and the second metal pattern may be on the first metal pattern, may overlap the first metal pattern, and may be electrically connected to the first metal pattern.

According to some example embodiments, the first connection line may further include a third metal pattern, and the third metal pattern may be on the second metal pattern, may overlap the second metal pattern, and may be electrically connected to the second metal pattern.

According to some example embodiments, the second metal pattern may be in the same layer as the gate electrode, and the third metal pattern may be in the same layer as the connection electrode.

According to some example embodiments, the first subpixel may further include a first electrode on the connection electrode, an emission layer on the first electrode, and a second electrode on the emission layer.

According to some example embodiments, the second gate line may be in the same layer as the connection electrode, and the second gate line may contact the second connection line through a second contact hole exposing the second connection line overlapping the second gate line.

According to some example embodiments, the first contact hole and the second contact hole may be spaced apart from each other.

According to some example embodiments, the first connection line may be between the second connection line and the first pixel on a plane.

According to some example embodiments, the first pixel may be between the first connection line and the data line on a plane.

According to some example embodiments, the at least one divided driving part may further include a low power supply voltage line spaced apart from the high power supply voltage line in the second direction, and the first connection line and the second connection line may be between the high power supply voltage line and the low power supply voltage line on a plane.

According to some example embodiments, the high supply voltage line may be between the first connection line and the first pixel on the plane.

According to some example embodiments, the data line may be between the first pixel and the first connection line on a plane.

According to some example embodiments, the first connection line may be between the data line and the second connection line on a plane.

According to some example embodiments, the first and second connection lines may be between the first pixel and the data line on a plane.

According to some example embodiments, the at least one divided driving part may further include a dummy line extending in the first direction and may be in the same layer as the first and second connection lines, the gate signal may be provided to each of the first and second connection lines, and the constant voltage may be provided to the dummy line.

According to some example embodiments, the divided driving parts may be arranged along the second direction.

According to some example embodiments, the first connection line may not be electrically connected to the second gate line.

According to some example embodiments, the contact hole may not be formed in a region where the first connection line and the second gate line overlap.

According to some example embodiments, the second connection line may not be electrically connected to the first gate line.

According to some example embodiments, the contact hole may not be formed in a region where the second connection line and the first gate line overlap.

A display apparatus according to some example embodiments may include: a display panel including a plurality of divided driving parts and in a display area; a gate driver in a non-display area adjacent to the display area; a data driver in the non-display area; and a timing controller in the non-display region and controlling the gate driver and the data driver. The at least one divided driving part of the plurality of divided driving parts may include: a first connecting line extending in a first direction; a second connection line extending in the first direction and spaced apart from the first connection line in a second direction crossing the first direction; a first gate line extending in a second direction and electrically connected to the first connection line; a second gate line extending in a second direction, spaced apart from the first gate line, and electrically connected to the second connection line; a first pixel in the first pixel column and the first pixel row and electrically connected to the first gate line; and a second pixel in the first pixel column and the second pixel row and electrically connected to the second gate line, wherein the second pixel row is spaced apart from the first pixel row in the first direction. The first connection line and the second connection line may be arranged to correspond to the first pixel column.

According to some example embodiments, the gate driver and the data driver may be in a non-display region adjacent to one side of the display panel.

Accordingly, the display panel according to some example embodiments may include a plurality of divided driving parts, and each of the plurality of divided driving parts may include a plurality of connection lines. Since the connection lines respectively transmit the gate signals to the pixels included in the plurality of divided driving parts, the transmission time of the gate signals can be shortened. In addition, a display device including the display panel may include a gate driver at one side (e.g., a lower side) of the display panel and a data driver at the one side (e.g., the lower side). Thus, the bezel of the other side (e.g., left or right side) of the display device may be reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the invention as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate aspects of some example embodiments of the invention and together with the description serve to explain the inventive concept.

Fig. 1 is a block diagram illustrating a display device according to some example embodiments.

Fig. 2 is a plan view illustrating the display device of fig. 1.

Fig. 3 is an enlarged view of more details of the display device of fig. 2.

Fig. 4 is a circuit diagram illustrating a sub-pixel included in the display device of fig. 3.

Fig. 5 is a sectional view taken along line I-I' of fig. 3.

Fig. 6 is a sectional view taken along line II-II' of fig. 3.

Fig. 7 is a sectional view taken along line III-III' of fig. 3.

Fig. 8 is an enlarged view showing more details of the display device of fig. 2.

Fig. 9 is an enlarged view showing more details of the display device of fig. 2.

Fig. 10 is an enlarged view showing more details of the display device of fig. 2.

Detailed Description

Illustrative and non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Fig. 1 is a block diagram illustrating a display device according to some example embodiments.

Referring to fig. 1, a display device 1000 according to some example embodiments may include a display panel DPN, a gate driver GDV, a data driver DDV, and a timing controller CON.

A plurality of pixels and a plurality of lines may be disposed in the display panel DPN. The pixels may emit light by receiving signals and/or voltages from the lines.

According to some example embodiments, the display panel DPN may include a plurality of divided driving parts. For example, the display panel DPN may include first to kth (where k is an integer of 2 or more) divided driving parts SDP1 to SDPk. According to some example embodiments, each of the divided driving parts may be formed to be substantially the same. For example, (2n × m) pixels may be disposed in the first divided driving section SDP1, and (2n × m) pixels may be disposed in the k-th divided driving section SDPk. Alternatively, according to some example embodiments, each of the divided driving parts may be formed to be different from each other.

The timing controller CON may generate the gate control signal GCTRL, the data control signal DCTRL, and the output image data ODAT based on the control signal CTRL and the input image data IDAT supplied from the external device. The timing controller CON may be formed on a printed circuit board PCB (see fig. 2). For example, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, and the like, and the input image data IDAT may be RGB data including red image data, green image data, and blue image data.

The gate driver GDV may generate the gate signal based on the gate control signal GCTRL provided from the timing controller CON. For example, the gate control signal GCTRL may include a vertical start signal and a clock signal.

The gate driver GDV may be electrically connected to the display panel DPN and may sequentially output gate signals. Each of the pixels may receive a data voltage in response to each of the gate signals.

According to some example embodiments, the gate driver GDV may include a partial gate driver corresponding to the divided driving part. For example, the gate driver GDV may include first to kth local gate drivers PGDV1 to PGDVk. The first local gate driver PGDV1 may sequentially output gate signals to the first divided driving part SDP1, and the kth local gate driver PGDVk may sequentially output gate signals to the kth divided driving part SDPk.

The data driver DDV may generate the data voltage based on the data control signal DCTRL and the output image data ODAT supplied from the timing controller CON. For example, the data control signal DCTRL may include an output data enable signal, a horizontal start signal, and a load signal.

The data driver DDV may be electrically connected to the display panel DPN and may generate a data voltage. Each of the pixels may emit light having a luminance corresponding to each of the data voltages. According to some example embodiments, the data driver DDV may include a plurality of data driving circuits.

According to some example embodiments, the pixels may be arranged in a matrix arrangement. Each of the first through k-th divided driving parts SDP1 through SDPk may be divided into a plurality of rows and a plurality of columns. For example, the rows may include first to nth pixel rows PXLr (1) to PXLr (2n) arranged along a first direction D1, and the columns may include first to mth pixel columns PXLc (1) to PXLc (m) arranged along a second direction D2 intersecting the first direction D1. Thus, a pixel of the pixels may be arranged in a pixel row of the pixel rows and a pixel column of the pixel columns.

According to some example embodiments, the first partial gate driver PGDV1 may output a gate signal to pixels disposed in the first divided driving portion SDP 1. For example, the first local gate driver PGDV1 may sequentially output the first to 2 n-th gate signals. The first gate signal may be supplied to the pixels disposed in the first pixel row PXLr (1), and the 2 n-th gate signal may be supplied to the pixels disposed in the 2 n-th pixel row PXLr (2 n).

According to some example embodiments, the kth local gate driver PGDVk may output the gate signal to the pixels disposed in the kth divided driving section SDPk. For example, the kth local gate driver PGDVk may sequentially output the first to 2n gate signals. The first to 2 n-th gate signals may be substantially the same as the first to 2 n-th gate signals output from the first local gate driver PGDV 1.

Fig. 2 is a plan view illustrating the display device of fig. 1.

Referring to fig. 1 and 2, the display apparatus 1000 may be divided into a display area DA provided with a display panel DPN and a non-display area NDA not provided with the display panel DPN.

The display panel DPN may include first to k-th divided driving parts SDP1 to SDPk. For example, 12 pixels may be set in each of the first to k-th divided driving sections SDP1 to SDPk.

According to some example embodiments, the first to twelfth pixels PXL1, PXL2, PXL3, PXL4, PXL5, PXL6, PXL7, PXL8, PXL9, PXL10, PXL11, and PXL12 may be disposed in the first divided drive section SDP 1. For example, the first to fourth pixels PXL1, PXL2, PXL3 and PXL4 may be disposed in the first pixel column PXLc (1), the fifth to eighth pixels PXL5, PXL6, PXL7 and PXL8 may be disposed in the second pixel column PXLc (2), and the ninth to twelfth pixels PXL9, PXL10, PXL11 and PXL12 may be disposed in the third pixel column PXLc (3). In addition, the first, fifth, and ninth pixels PXL1, PXL5, and PXL9 may be disposed in the first pixel row PXLr (1), the second, sixth, and tenth pixels PXL2, PXL6, and PXL10 may be disposed in the second pixel row PXLr (2), the third, seventh, and eleventh pixels PXL3, PXL7, and PXL11 may be disposed in the third pixel row PXLr (3), and the fourth, eighth, and twelfth pixels PXL4, PXL8, and PXL12 may be disposed in the fourth pixel row PXLr (4).

According to some example embodiments, 6 connection lines, 4 gate lines, and 9 data lines may be disposed in each of the first to k-th divided driving parts SDP1 to SDPk. For example, the first to sixth connection lines CL1, CL2, CL3, CL4, CL5 and CL6, the first to fourth gate lines GL1, GL2, GL3, GL4, and the first to ninth data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8 and DL9 may be disposed in the first divided driving part SDP 1.

According to some example embodiments, each of the connection lines may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. For example, the first and second connection lines CL1 and CL2 may be arranged to correspond to the first pixel column PXLc (1), the third and fourth connection lines CL3 and CL4 may be arranged to correspond to the second pixel column PXLc (2), and the fifth and sixth connection lines CL5 and CL6 may be arranged to correspond to the third pixel column PXLc (3). In other words, the two connection lines may be arranged to correspond to one pixel column among the pixel columns. However, the number of connection lines arranged to correspond to one pixel column is not limited thereto. For example, according to some example embodiments, there may be additional or fewer connecting lines without departing from the spirit and scope of embodiments according to the present disclosure.

Each of the connection lines may electrically connect one of the gate lines and the gate driver GDV. For example, the first connection line CL1 may electrically connect the first gate line GL1 and the first local gate driver PGDV1, the second connection line CL2 may electrically connect the second gate line GL2 and the first local gate driver PGDV1, the third connection line CL3 may electrically connect the third gate line GL3 and the first local gate driver PGDV1, and the fourth connection line CL4 may electrically connect the fourth gate line GL4 and the first local gate driver PGDV 1.

According to some example embodiments, each of the gate lines may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. For example, the first gate lines GL1 may be arranged to correspond to the first pixel row PXLr (1), the second gate lines GL2 may be arranged to correspond to the second pixel row PXLr (2), the third gate lines GL3 may be arranged to correspond to the third pixel row PXLr (3), and the fourth gate lines GL4 may be arranged to correspond to the fourth pixel row PXLr (4).

Each of the gate lines may electrically connect the pixels disposed in one of the pixel rows and the connection line. For example, the first gate line GL1 may electrically connect the first, fifth, and ninth pixels PXL1, PXL5, and PXL9 disposed in the first pixel row PXLr (1) and the first connection line CL1, the second gate line GL2 may electrically connect the second, sixth, and tenth pixels PXL6, and PXL10 disposed in the second pixel row PXLr (2) and the second connection line CL2, the third gate line GL3 may electrically connect the third, seventh, and eleventh pixels PXL3, PXL7, and PXL11 disposed in the third pixel row PXLr (3) and the third connection line CL3, and the fourth gate line GL4 may electrically connect the fourth, eighth, and twelfth pixels PXL6, PXL8, and the twelfth pixel PXL 73727 disposed in the fourth pixel row PXLr (4) and the fourth connection line 12.

According to some example embodiments, each of the data lines may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. For example, the first to third data lines DL1, DL2 and DL3 may be arranged to correspond to the first pixel column PXLc (1), the fourth to sixth data lines DL4, DL5 and DL6 may be arranged to correspond to the second pixel column PXLc (2), and the seventh to ninth data lines DL7, DL8 and DL9 may be arranged to correspond to the third pixel column PXLc (3). In other words, three data lines may be arranged to correspond to one pixel column among the pixel columns. However, the number of data lines arranged corresponding to one pixel column is not limited thereto. For example, according to some example embodiments, there may be additional or fewer data lines without departing from the spirit and scope of embodiments according to the present disclosure.

Each of the data lines may electrically connect the pixels arranged in one of the pixel columns and the data driver DDV. For example, the first data line DL1 may electrically connect the first to fourth pixels PXL1, PXL2, PXL3 and PXL4 arranged in the first pixel column PXLc (1) and the data driver DDV.

The gate driver GDV may be disposed in the non-display area NDA adjacent to the lower side of the display panel DPN.

According to some example embodiments, the gate driver GDV may be installed in the non-display area NDA. The gate driver GDV may include first to kth local gate drivers PGDV1 to PGDVk. The first through kth partial gate drivers PGDV1 through PGDVk may output gate signals to pixels disposed in the first through kth divided driving sections SDP1 through SDPk, respectively.

The data driver DDV may be disposed in the non-display area NDA adjacent to a lower side of the display panel DPN. According to some example embodiments, the data driver DDV may be implemented in the first to kth data driving circuits DIC1 to DICk. In this case, the flexible printed circuit board FPCB may be disposed in the non-display area NDA, and each of the data driving circuits may be integrated on the flexible printed circuit board FPCB. The first to kth data driving circuits DIC1 to DICk may output the data voltages to the pixels disposed in the first to kth divided driving sections SDP1 to SDPk, respectively.

The gate driver GDV and the data driver DDV included in the display device 1000 according to some example embodiments may be disposed in the non-display area NDA adjacent to the lower side of the display panel DPN. In other words, the gate driver GDV may not be disposed in the non-display area NDA adjacent to the left or right side of the display panel DPN. Accordingly, the bezel of the left or right side of the display apparatus 1000 may be reduced.

Meanwhile, the divided driving part, the gate driver, and the data driver included in the display device 1000 are not limited to the above. For example, the number of pixels, connection lines, gate lines, or data lines may be set as desired. In addition, the gate driver may be implemented in a plurality of gate driving circuits, and each of the gate driving circuits may be integrated on the flexible printed circuit board FPCB.

According to some example embodiments, a plurality of high power voltage lines may be disposed in the first divided driving portion SDP 1. For example, the first to third high power voltage lines elvdd 1, elvdd 2, and elvdd 3 may be disposed in the first divided driving portion SDP 1.

According to some example embodiments, each of the high supply voltage lines may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. For example, the first high power voltage line elddl 1 may be disposed to correspond to the first pixel column PXLc (1), the second high power voltage line elddl 2 may be disposed to correspond to the second pixel column PXLc (2), and the third high power voltage line elddl 3 may be disposed to correspond to the third pixel column PXLc (3). In other words, the high power supply voltage line may be arranged to correspond to one pixel column among the pixel columns. However, the number of the high power supply voltage lines arranged to correspond to one pixel column is not limited thereto.

Each of the high power supply voltage lines may transmit a high power supply voltage to a pixel in a pixel column disposed among the pixel columns. For example, the first high power voltage line elddl 1 may transmit the high power voltage to the first to fourth pixels PXL1, PXL2, PXL3, and PXL4 disposed in the first pixel column PXLc (1), the second high power voltage line elddl 2 may transmit the high power voltage to the fifth to eighth pixels PXL5, PXL6, PXL7, and PXL8 disposed in the second pixel column PXLc (2), and the third high power voltage line elddl 3 may transmit the high power voltage to the ninth to twelfth pixels PXL9, PXL10, PXL11, and PXL12 disposed in the third pixel column PXLc (3).

According to some example embodiments, the fifth and sixth connection lines CL5 and CL6 may not be connected to the gate lines. For example, the fifth and sixth connection lines CL5 and CL6 may be dummy lines. Accordingly, a constant voltage may be supplied to the fifth connection line CL5 and the sixth connection line CL 6. Alternatively, the fifth and sixth connection lines CL5 and CL6 may be electrically floating.

Fig. 3 is an enlarged view showing more details of the display device of fig. 2. Fig. 4 is a circuit diagram illustrating a sub-pixel included in the display device of fig. 3. Fig. 5 is a sectional view taken along line I-I' of fig. 3. Fig. 6 is a sectional view taken along line II-II' of fig. 3. Fig. 7 is a sectional view taken along line III-III' of fig. 3. For example, fig. 3 may be an enlarged view of region a of fig. 2.

Referring to fig. 2, 3, and 4, the first pixel PXL1 may include first to third sub-pixels SPX1, SPX2, and SPX 3. For example, the first subpixel SPX1 may emit red light, the second subpixel SPX2 may emit green light, and the third subpixel SPX3 may emit blue light. The second pixel PXL2 may have substantially the same structure as the first pixel PXL1 and may be driven in substantially the same driving method.

According to some example embodiments, the first pixel PXL1 may be electrically connected to the first gate line GL 1. The first gate line GL1 may be electrically connected to the first connection line CL1 through the first contact hole CNT 1. Accordingly, the first pixel PXL1 may receive the first gate signal GS 1. In other words, the first pixel PXL1 may receive the first output gate signal from the first local gate driver PGDV 1. For example, the first to third subpixels SPX1, SPX2 and SPX3 included in the first pixel PXL1 may receive the first gate signal GS 1.

According to some example embodiments, the second pixel PXL2 may be electrically connected to the second gate line GL 2. The second gate line GL2 may be electrically connected to the second connection line CL2 through the second contact hole CNT 2. Accordingly, the second pixel PXL2 may receive the second gate signal GS 2. In other words, the second pixel PXL2 may receive the second output gate signal from the first local gate driver PGDV 1. For example, the first to third subpixels SPX1, SPX2 and SPX3 included in the second pixel PXL2 may receive the second gate signal GS 2.

According to some example embodiments, the second connection line CL2 and the first gate line GL1 may not be electrically connected to each other. For example, the contact hole may not be formed in a region where the second connection line CL2 and the first gate line GL1 overlap. In addition, the first connection line CL1 and the second gate line GL2 may not be electrically connected to each other. For example, the contact hole may not be formed in a region where the first connection line CL1 and the second gate line GL2 overlap.

According to some example embodiments, the first pixel PXL1 may be electrically connected to the first to third data lines DL1, DL2 and DL 3. In detail, the first subpixel SPX1 included in the first pixel PXL1 may be electrically connected to the first data line DL1, the second subpixel SPX2 may be electrically connected to the second data line DL2, and the third subpixel SPX3 may be electrically connected to the third data line DL 3. Accordingly, the first to third sub-pixels SPX1, SPX2, and SPX3 may receive different DATA voltages DATA.

According to some example embodiments, each of the first to third sub-pixels SPX1, SPX2, and SPX3 may receive the high power supply voltage ELVDD from the first high power supply voltage line elvdl 1, may receive the low power supply voltage ELVSS from the first low power supply voltage line elvsl 1, and may receive the initialization voltage VINT from the first sensing line SL 1.

As shown in fig. 4, the first sub-pixel SPX1 may include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor CST, and a light emitting diode LED. For example, each of the first to third transistors T1, T2, and T3 may be implemented as an n-type transistor or a p-type transistor. In addition, each of the second and third sub-pixels SPX2 and SPX3 may include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor CST, and a light emitting diode LED. The light emitting diode LED may include an organic light emitting diode ("OLED") or a nano light emitting diode ("nano LED").

The first transistor T1 may include a control terminal connected to the second transistor T2, a first terminal connected to the first high power voltage line elvdd 1, and a second terminal connected to the light emitting diode LED. For example, the first transistor T1 may be referred to as a driving transistor.

The second transistor T2 may include a control terminal connected to the first gate line GL1, a first terminal connected to the first data line DL1, and a second terminal connected to the first transistor T1. For example, the second transistor T2 may be referred to as a switching transistor.

The third transistor T3 may include a control terminal connected to the first gate line GL1, a first terminal connected to the light emitting diode LED, and a second terminal connected to the first sensing line SL 1. For example, the third transistor T3 may be referred to as a sense transistor.

The storage capacitor CST may include a first terminal connected to the control terminal of the first transistor T1 and a second terminal connected to the second terminal of the first transistor T1.

The OLED may include a first terminal connected to the first transistor T1 and a second terminal connected to the first low power voltage line elvsl 1. For example, the first terminal may be an anode terminal and the second terminal may be a cathode terminal. The OLED may include functional layers (e.g., an electron/hole injection layer and an electron/hole transport layer) and organic material layers disposed between the functional layers, and may emit light in a specific wavelength range depending on materials constituting the organic material layers.

The nano LED may include a first terminal connected to the first transistor T1 and a second terminal connected to a first low power voltage line elvsl 1. For example, the first terminal may be an anode terminal and the second terminal may be a cathode terminal. The nano-LED may include semiconductor layers (e.g., an n-type semiconductor layer and a p-type semiconductor layer) and an active material layer disposed between the semiconductor layers. Thus, light in a specific wavelength range can be emitted.

For example, the high power supply voltage ELVDD may be greater than the low power supply voltage ELVSS. The high power supply voltage ELVDD may be a high power supply voltage, and the low power supply voltage ELVSS may be a low power supply voltage.

Referring to fig. 2, 3 and 5, the first subpixel SPX1 may include a substrate 100, a first insulating layer ILD1, an active pattern 300, a second insulating layer ILD2, a gate electrode 400, a third insulating layer ILD3, a connection electrode 500, a VIA insulating layer VIA, a first electrode 610, an emission layer 620 and a second electrode 630.

The substrate 100 may include a glass substrate, a quartz substrate, a plastic substrate, or the like. According to some example embodiments, the substrate 100 may include a glass substrate. Thus, the display device 1000 may be a rigid display device. According to some example embodiments, the substrate 100 may include a plastic substrate. Thus, the display device 1000 may be a flexible display device. In this case, the substrate 100 may have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked.

The first data line DL1 may be disposed on the substrate 100. According to some example embodiments, the first DATA line DL1 may provide the DATA voltage DATA to the first subpixel SPX 1. For example, the first data line DL1 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first data line DL1 may include silver ("Ag"), an alloy containing silver, molybdenum ("Mo"), an alloy containing molybdenum, aluminum ("Al"), an alloy containing aluminum, aluminum nitride ("AlN"), tungsten ("W"), tungsten nitride ("WN"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), chromium nitride ("CrN"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), scandium ("Sc"), indium tin oxide ("ITO"), indium zinc oxide ("IZO"), or the like.

The first insulating layer ILD1 may cover the first data line DL1 and may be disposed on the substrate 100. First insulating layer ILD1 may comprise an insulating material. For example, the first insulating layer ILD1 may include silicon oxide, silicon nitride, titanium oxide, tantalum oxide, or the like.

The active pattern 300 may be disposed on the first insulating layer ILD 1. For example, the active pattern 300 may include amorphous silicon, polysilicon, or an oxide semiconductor. According to some example embodiments, ions may be selectively implanted into the active pattern 300. For example, when the first transistor T1, the second transistor T2, and the third transistor T3 are n-type transistors, the active pattern 300 may include source and drain regions implanted with anions and a channel region not implanted with anions.

The second insulating layer ILD2 may cover the active patterns 300 and may be disposed on the first insulating layer ILD 1. The second insulating layer ILD2 may include an insulating material.

The gate electrode 400 may be disposed on the second insulating layer ILD 2. According to some example embodiments, the gate electrode 400 may receive the first gate signal GS1 through the first gate line GL 1. For example, the gate electrode 400 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the gate electrode 400 may include silver ("Ag"), an alloy containing silver, molybdenum ("Mo"), an alloy containing molybdenum, aluminum ("Al"), an alloy containing aluminum, aluminum nitride ("AlN"), tungsten ("W"), tungsten nitride ("WN"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), chromium nitride ("CrN"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), scandium ("Sc"), indium tin oxide ("ITO"), indium zinc oxide ("IZO"), or the like. According to some example embodiments, the gate electrode 400 may include molybdenum ("Mo"), an alloy including molybdenum, or the like.

The third insulating layer ILD3 may cover the gate electrode 400 and may be disposed on the second insulating layer ILD 2. The third insulating layer ILD3 may include an insulating material.

The connection electrode 500 may be disposed on the third insulating layer ILD 3. For example, the connection electrode may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the connection electrode 500 may include silver ("Ag"), an alloy containing silver, molybdenum ("Mo"), an alloy containing molybdenum, aluminum ("Al"), an alloy containing aluminum, aluminum nitride ("AlN"), tungsten ("W"), tungsten nitride ("WN"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), chromium nitride ("CrN"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), scandium ("Sc"), indium tin oxide ("ITO"), indium zinc oxide ("IZO"), or the like. According to some example embodiments, in order to reduce the resistance of connection electrode 500, connection electrode 500 may include aluminum ("Al"). For example, the connection electrode 500 may have a Ti/Al/Ti structure.

According to some example embodiments, the connection electrode 500 may include a source electrode 510 and a drain electrode 520. For example, the source electrode 510 may partially overlap the first data line DL1 and the active pattern 300. The drain electrode 520 may partially overlap the active pattern 300. For example, the source electrode 510 may contact the first data line DL1 through contact holes formed in the first, second, and third insulating layers ILD1, ILD2, and ILD 3. In addition, the source electrode 510 may contact the active pattern 300 through contact holes formed in the second and third insulating layers ILD2 and ILD 3. The drain electrode 520 may contact the active pattern 300 through contact holes formed in the second and third insulating layers ILD2 and ILD 3. In addition, the source electrode 510 and the drain electrode 520 may not overlap the gate electrode 400.

According to some example embodiments, the source electrode 510 may correspond to a first terminal of the second transistor T2, the drain electrode 520 may correspond to a second terminal of the second transistor T2, and the gate electrode 400 may correspond to a control terminal of the second transistor T2. Accordingly, the active pattern 300, the gate electrode 400, the source electrode 510, and the drain electrode 520 may constitute the second transistor T2. For example, the DATA voltage DATA from the first DATA line DL1 may be applied to the source electrode 510, the active pattern 300, and the drain electrode 520 in response to the first gate signal GS 1.

The VIA insulation layer VIA may cover the connection electrode 500 and may be disposed on the third insulation layer ILD 3. For example, the VIA insulating layer VIA may have a substantially flat top surface. According to some example embodiments, the VIA insulating layer VIA may include an organic insulating material. For example, the VIA insulating layer VIA may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, or the like.

The first electrode 610 may be disposed on the VIA insulating layer VIA. For example, the first electrode 610 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. The emission layer 620 may be disposed on the first electrode 610. According to some example embodiments, a pixel defining layer including an opening exposing an upper surface of the first electrode 610 may be disposed on the first electrode 610, and an emission layer 620 may be disposed in the opening. For example, the emission layer 620 may include an organic light emitting material. The organic light emitting material may emit light by receiving current. The second electrode 630 may be disposed on the emission layer 620. For example, the second electrode 630 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. According to some example embodiments, the first electrode 610, the emission layer 620, and the second electrode 630 may constitute a light emitting diode LED.

Referring to fig. 2, 3, 5, and 6, the first connection line CL1 may include a first metal pattern MP1, a second metal pattern MP2, and a third metal pattern MP 3.

According to some example embodiments, the first metal pattern MP1 may be disposed between the substrate 100 and the active pattern 300. For example, the first metal pattern MP1 may extend in the first direction D1. The first metal pattern MP1 may include the same material as the first data line DL 1. For example, the first metal pattern MP1 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first metal pattern MP1 may include silver ("Ag"), an alloy containing silver, molybdenum ("Mo"), an alloy containing molybdenum, aluminum ("Al"), an alloy containing aluminum, aluminum nitride ("AlN"), tungsten ("W"), tungsten nitride ("WN"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), chromium nitride ("CrN"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), scandium ("Sc"), indium tin oxide ("ITO"), indium zinc oxide ("IZO"), or the like. For example, the first metal pattern MP1 may be formed together with the first data line DL 1.

According to some example embodiments, the second metal pattern MP2 may be disposed on the second insulating layer ILD2, may overlap the first metal pattern MP1, and may be electrically connected to the first metal pattern MP 1. For example, the second metal pattern MP2 may contact the first metal pattern MP1 through contact holes formed in the first and second insulating layers ILD1 and ILD 2. For example, the second metal pattern MP2 may extend in the first direction D1 and may be disposed along the first direction D1. For example, the second metal pattern MP2 may not be formed in a region where the first metal pattern MP1 and the first gate line GL1 contact each other. The second metal pattern MP2 may include the same material as the gate electrode 400. For example, the second metal pattern MP2 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the second metal pattern MP2 may be formed together with the gate electrode 400.

According to some example embodiments, the third metal pattern MP3 may be disposed on the third insulating layer ILD3, may overlap the first and second metal patterns MP1 and MP2, and may be electrically connected to the first metal pattern MP 1. For example, the third metal pattern MP3 may contact the first metal pattern MP1 through contact holes formed in the first to third insulating layers ILD1, ILD2 and ILD 3. For example, the third metal pattern MP3 may extend in the first direction D1 and may be arranged along the first direction D1. For example, the third metal pattern MP3 may not be formed in a region where the first metal pattern MP1 and the first gate line GL1 contact each other. The third metal pattern MP3 may include the same material as the connection electrode 500. For example, the third metal pattern MP3 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the third metal pattern MP3 may be formed together with the connection electrode 500.

The first gate signal GS1 may be transmitted to the first gate line GL1 through the first to third metal patterns MP1, MP2 and MP 3. When the first connection line CL1 includes the first to third metal patterns MP1, MP2 and MP3 that are vertically stacked, the resistance of the first connection line CL1 may be reduced.

The first gate line GL1 may be disposed on the third insulating layer ILD 3. For example, the first gate line GL1 may contact the first metal pattern MP1 through the first contact hole CNT1 exposing the first metal pattern MP1 overlapping with the first gate line GL 1. Accordingly, the first gate line GL1 may receive the first gate signal GS1 from the first metal pattern MP 1.

The second gate line GL2 may be disposed on the third insulating layer ILD 3. For example, the second gate line GL2 may contact the fourth metal pattern through the second contact hole CNT2 exposing the fourth metal pattern MP4 overlapping with the second gate line GL 2. Accordingly, the second gate line GL2 may receive the second gate signal from the fourth metal pattern MP 4. According to some example embodiments, the first contact hole CNT1 and the second contact hole CNT2 may be spaced apart from each other.

Referring to fig. 3 and 7, the second connection line CL2 may have substantially the same structure as the first connection line CL 1. For example, the second connection line CL2 may include a fourth metal pattern MP4, a fifth metal pattern MP5 disposed on the fourth metal pattern MP4, and a sixth metal pattern MP6 disposed on the fifth metal pattern MP 5.

The second connection line CL2 may not be electrically connected to the first gate line GL 1. For example, the contact hole may not be formed in a region where the second connection line CL2 and the first gate line GL1 overlap. Accordingly, the second gate signal GS2 flowing through the second connection line CL2 may not be transmitted to the first gate line GL 1.

Referring again to fig. 2 and 3, the first and second connection lines CL1 and CL2 may be disposed between the first high power voltage line elvdd 1 and the first low power voltage line elvss 1 on a plane (e.g., in a plan view or a perpendicular or orthogonal view with respect to a plane of the display surface). In a plane, the second connection line CL2 may be disposed between the first connection line CL1 and the first high power voltage line elvdd 1. In a plane, the first high power voltage line elddl 1 may be disposed between the second connection line CL2 and the first pixel PXL 1. In a plane, the first to third data lines DL1, DL2, and DL3 may be disposed between the first pixel PXL1 and the first sensing line SL 1.

Fig. 8 is an enlarged view showing more details of the display device of fig. 2. For example, fig. 8 may be an enlarged view of region a of fig. 2.

Referring to fig. 2 and 8, the first divided driving portion SDP1 may include a first pixel PXL1, a second pixel PXL2, a first low power voltage line elvsl 1, a second connection line CL2, a first connection line CL1, a first high power voltage line elvdd 1, a first data line DL1, a second data line DL2, a third data line DL3, a first sensing line SL1, a first gate line GL1, and a second gate line GL 2. However, the first pixel PXL1, the second pixel PXL2, the first low power supply voltage line elvsl 1, the second connection line CL2, the first connection line CL1, the first high power supply voltage line elvdd 1, the first data line DL1, the second data line DL2, the third data line DL3, the first sensing line SL1, the first gate line GL1, and the second gate line GL2 of fig. 8 may be substantially the same as the first pixel PXL1, the second pixel PXL2, the first low power supply voltage line elvsl 1, the second connection line CL2, the first connection line CL1, the first high power supply voltage line elv 1, the first data line DL1, the second data line DL2, the third data line DL3, the first sensing line SL1, the first gate line GL1, and the second gate line GL2 of fig. 3, except that a planar structure of the above-mentioned components is provided. Hereinafter, a planar structure in which the above components are provided will be described in more detail.

In a plane, the first and second connection lines CL1 and CL2 may be disposed between the first high power voltage line elvdl 1 and the first low power voltage line elvsl 1. In a plane, the first connection line CL1 may be disposed between the second connection line CL2 and the first high power voltage line elddl 1. In a plane, the first high power voltage line elddl 1 may be disposed between the first connection line CL1 and the first pixel PXL 1. In a plane, the first pixel PXL1 may be disposed between the first high power voltage line elddl 1 and the first data line DL 1. In a plane, the first to third data lines DL1, DL2, and DL3 may be disposed between the first pixel PXL1 and the first sensing line SL 1.

Fig. 9 is an enlarged view showing more details of the display device of fig. 2.

Referring to fig. 2 and 9, the first divided driving portion SDP1 may include a first pixel PXL1, a second pixel PXL2, a first low power voltage line elvsl 1, a second connection line CL2, a first connection line CL1, a first high power voltage line elvdd 1, a first data line DL1, a second data line DL2, a third data line DL3, a first sensing line SL1, a first gate line GL1, and a second gate line GL 2. However, the first pixel PXL1, the second pixel PXL2, the first low power supply voltage line elvsl 1, the second connection line CL2, the first connection line CL1, the first high power supply voltage line elvdd 1, the first data line DL1, the second data line DL2, the third data line DL3, the first sensing line SL1, the first gate line GL1, and the second gate line GL2 of fig. 9 may be substantially the same as the first pixel PXL1, the second pixel PXL2, the first low power supply voltage line elvsl 1, the second connection line CL2, the first connection line CL1, the first high power supply voltage line elv 1, the first data line DL1, the second data line DL2, the third data line DL3, the first sensing line SL1, the first gate line GL1, and the second gate line GL2 of fig. 3, except that a planar structure of the above-mentioned components is provided. Hereinafter, a planar structure in which the above components are provided will be described in more detail.

In a plane, the first and second connection lines CL1 and CL2 may be disposed between the third data line DL3 and the first sensing line SL 1. The first connection line CL1 may be disposed between the third data line DL3 and the second connection line CL 2. The first pixel PXL1 may be disposed between the first data line DL1 and the first high power voltage line elddl 1. The first high power voltage line elvdd 1 may be disposed between the first pixel PXL1 and the first low power voltage line elvsl 1.

Fig. 10 is an enlarged view showing more details of the display device of fig. 2.

Referring to fig. 2 and 10, the first divided driving portion SDP1 may include a first pixel PXL1, a second pixel PXL2, a first low power voltage line elvsl 1, a second connection line CL2, a first connection line CL1, a first high power voltage line elvdd 1, a first data line DL1, a second data line DL2, a third data line DL3, a first sensing line SL1, a first gate line GL1, and a second gate line GL 2. However, the first pixel PXL1, the second pixel PXL2, the first low power supply voltage line elvsl 1, the second connection line CL2, the first connection line CL1, the first high power supply voltage line elvdd 1, the first data line DL1, the second data line DL2, the third data line DL3, the first sensing line SL1, the first gate line GL1, and the second gate line GL2 of fig. 10 may be substantially the same as the first pixel PXL1, the second pixel PXL2, the first low power supply voltage line elvsl 1, the second connection line CL2, the first connection line CL1, the first high power supply voltage line elv 1, the first data line DL1, the second data line DL2, the third data line DL3, the first sensing line SL1, the first gate line GL1, and the second gate line GL2 of fig. 3, except that a planar structure of the above-mentioned components is provided. Hereinafter, a planar structure in which the above-described components are provided will be described.

In a plane, the first connection line CL1 and the second connection line CL2 may be disposed between the first pixel PXL1 and the first data line DL 1. In a plane, the first connection line CL1 may be disposed between the first pixel PXL1 and the second connection line CL 2.

The display panel according to some example embodiments may include a plurality of divided driving parts, and each of the gate signals may be provided to the divided driving parts. Thus, the transfer time of the gate signal transferred to the pixel far from the gate driver can be relatively shortened. In this case, in order to supply each of the gate signals to the divided driving parts, the display panel may include a plurality of connection lines arranged to correspond to the pixel columns.

In addition, the display device including the display panel may include a data driver disposed in a non-display region adjacent to one side (e.g., a lower side) of the display panel, and the gate driver may be disposed in the non-display region. Since the gate driver and the data driver are disposed at one side of the display device, a bezel of the display device may be reduced.

Although some example embodiments and implementation aspects have been described herein, other embodiments and modifications will be apparent from this description. It will thus be evident to those of ordinary skill in the art that the inventive concept is not limited to such embodiments, but is to be defined by the following claims and their equivalents, as well as the various modifications and equivalent arrangements.