阅读说明：本技术 存储装置及其操作方法 (Storage device and operation method thereof ) 是由 刘炳晟 于 2021-02-19 设计创作，主要内容包括：本公开涉及一种存储装置及其操作方法。该存储装置包括：存储器装置,其包括存储正常数据和映射数据的存储器单元阵列；以及存储控制器,其被配置为响应于来自主机的请求而控制存储器装置的包括编程操作、读操作和擦除操作在内的总体操作。存储器装置被配置为在映射数据加载操作期间通过读取存储在存储器单元阵列中的映射数据当中的第一映射数据来将第一映射数据发送到存储控制器,并且通过读取映射数据当中的第二映射数据来将第二映射数据发送到存储器装置的页缓冲器组。(The present disclosure relates to a memory device and an operating method thereof. The storage device includes: a memory device including a memory cell array storing normal data and mapping data; and a memory controller configured to control overall operations of the memory device including a program operation, a read operation, and an erase operation in response to a request from a host. The memory device is configured to transmit first mapping data to the memory controller by reading the first mapping data among the mapping data stored in the memory cell array and to transmit second mapping data to the page buffer group of the memory device by reading the second mapping data among the mapping data during the mapping data load operation.)

1. A memory device, the memory device comprising:

a memory device including a memory cell array storing normal data and mapping data; and

a memory controller configured to control overall operations of the memory device including a program operation, a read operation, and an erase operation in response to a request from a host,

wherein the memory device is configured to transmit first mapping data among the mapping data stored in the memory cell array to the memory controller by reading the first mapping data and to transmit second mapping data among the mapping data to a page buffer group of the memory device by reading the second mapping data during a mapping data load operation.

2. The storage device of claim 1, wherein the storage controller comprises a memory buffer, wherein the memory buffer is configured to store the first mapping data received from the memory device during the mapping data load operation.

3. The storage apparatus according to claim 1, wherein the first mapping data is cold data having a relatively low number of accesses among the mapping data, and the second mapping data is hot data having a relatively high number of accesses among the mapping data.

4. The memory device according to claim 1, wherein the page buffer group includes:

a main buffer stage configured to at least one of: sensing data stored in the memory cell array; and temporarily storing data to be programmed in the memory cell array;

a cache buffer stage configured to at least one of: outputting data stored in the main buffer stage to the memory controller; and sending data to be programmed received from the memory controller to the main buffer stage;

a first mapping buffer stage configured to read and store the second mapping data among the mapping data stored in the memory cell array; and

a second mapping buffer stage configured to store logical block addresses received from the storage controller.

5. The storage device of claim 4, wherein the storage controller is configured to receive the logical block address with a request from the host and to send the logical block address to the memory device when the received logical block address corresponds to the second mapping data.

6. The memory device of claim 5, wherein the page buffer set is configured to perform a mapped data search operation: searching whether search mapping data corresponding to the logical block address received from the storage controller and stored in the second mapping buffer stage is included in the second mapping data stored in the first mapping buffer stage.

7. The memory device of claim 6, wherein the memory device is configured to send a status register signal of a particular logic level to the memory controller when the search mapping data is determined to be included in the second mapping data during the mapping data search operation, and

the memory controller is configured to identify, based on the status register signal, that the logical block address matches the second mapping data stored in the first mapping buffer stage.

8. The storage device of claim 7, wherein the memory device is configured to store mapping data matching the logical block address among the second mapping data stored in the first mapping buffer stage in the memory cell array.

9. The memory device according to claim 6, wherein the memory device is configured to, when it is determined during the mapping data search operation that the search mapping data is not included in the second mapping data, store new second mapping data in the first mapping buffer stage by reading the new second mapping data among the mapping data stored in the memory cell array, and perform the mapping data search operation again.

10. The memory device of claim 1, wherein the memory cell array comprises a single level cell region and a three level cell region, and

the single level cell region is programmed using a single level cell programming method, and the three level cell region is programmed using a three level cell programming method.

11. The storage device according to claim 10, wherein the storage device is configured to program the normal data or the mapping data in the single-level cell region during a program operation of the normal data or the mapping data, and

during a background operation, the normal data or the mapping data stored in the single-level cell region is read, and the read normal data or mapping data is programmed in the three-level cell region.

12. A method of operating a memory device, the method comprising the steps of:

reading first mapping data and second mapping data among mapping data stored in a system block of a memory cell array;

sending the first mapping data to a memory controller, storing the first mapping data in a memory buffer of the memory controller, and storing the second mapping data in a set of page buffers of a memory device; and

when the page buffer group receives a logical block address from the memory controller, a mapping data search operation of searching whether search mapping data corresponding to the received logical block address is included in the second mapping data is performed.

13. The method of claim 12, further comprising the steps of:

transmitting a specific signal to the memory controller when the search mapping data is determined to be included in the second mapping data as a result of the mapping data search operation; and

when it is determined that the search mapping data is not included in the second mapping data as a result of the mapping data search operation, new second mapping data among the mapping data stored in the system block is read and stored in the page buffer group.

14. The method of claim 13, further comprising the steps of:

sending the logical block address and the normal data to be programmed from the memory controller to the memory device during a normal data programming operation;

programming the normal data in the memory cell array; and

performing a mapping data refresh operation of storing mapping data corresponding to the logical block address among the second mapping data in the memory cell array.

15. The method of claim 14, wherein the memory cell array comprises a single level cell region and a three level cell region, and

the single level cell region is programmed in a single level cell programming method, and the three level cell region is programmed in a three level cell programming method.

16. The method of claim 15, wherein the mapping data or the normal data corresponding to the logical block address is programmed in the single level cell region of the memory cell array.

17. The method of claim 12, wherein the first mapping data is cold data having a relatively low number of accesses among the mapping data, and the second mapping data is hot data having a relatively high number of accesses among the mapping data.

18. A method of operating a memory device, the method comprising the steps of:

storing first mapping data among mapping data stored in a system block in a memory controller and second mapping data among the mapping data in a page buffer group of a memory device during a mapping data load operation;

receiving, by the memory device, a logical block address from the storage controller during a mapping data search operation, and searching whether search mapping data corresponding to the received logical block address is included in the second mapping data;

receiving, by the memory device, normal data and the logical block address from the memory controller during a data programming operation, storing the normal data in a memory cell array, and then leaving mapping data corresponding to the logical block address among the second mapping data in the page buffer group; and

storing the mapping data left in the page buffer group in the memory cell array during a mapping data refresh operation.

19. The method of claim 18, wherein the first mapping data is cold data having a relatively low number of accesses among the mapping data, and the second mapping data is hot data having a relatively high number of accesses among the mapping data.

20. The method of claim 18, wherein the memory cell array comprises a single level cell region and a three level cell region,

the single-level cell region is programmed in a single-level cell programming method, the three-level cell region is programmed in a three-level cell programming method, and

the normal data or the mapping data left in the page buffer group is programmed in the single-level cell region of the memory cell array.

Technical Field

The present disclosure relates to electronic devices, and more particularly, to a memory device and a method of operating the same.

Background

A storage device is a device that stores data under the control of a host device such as a computer or a smartphone. The memory device may include a memory device to store data and a memory controller to control the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

Volatile memory devices are devices that store data only when power is applied and lose stored data when power is cut off. Volatile memory devices include, for example, Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

A nonvolatile memory device is a device that does not lose data even if power is cut off. Non-volatile memory devices include, for example, read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, and the like.

Disclosure of Invention

Embodiments of the present disclosure relate to a storage apparatus capable of increasing a loading capacity of mapping data and an improved operation speed and a method of operating the same.

The storage device according to an embodiment of the present disclosure includes: a memory device including a memory cell array storing normal data and mapping data; and a memory controller configured to control overall operations of the memory device including a program operation, a read operation, and an erase operation in response to a request from a host. The memory device is configured to transmit first mapping data to the memory controller by reading the first mapping data among the mapping data stored in the memory cell array and to transmit second mapping data to the page buffer group of the memory device by reading the second mapping data among the mapping data during the mapping data load operation.

The method of operating a storage device according to an embodiment of the present disclosure includes the steps of: reading first mapping data and second mapping data among mapping data stored in a system block of a memory cell array; transmitting the first mapping data to the memory controller, storing the first mapping data in a memory buffer of the memory controller, and storing the second mapping data in a page buffer group; and when the page buffer group receives a logical block address from the memory controller, performing a mapping data search operation of searching whether search mapping data corresponding to the received logical block address is included in the second mapping data.

The method of operating a storage device according to an embodiment of the present disclosure includes the steps of: storing first mapping data among the mapping data stored in the system block in the memory controller and second mapping data among the mapping data in a page buffer group of the memory device during a mapping data loading operation; receiving, by the memory device, a logical block address from the memory controller during the mapping data search operation, and searching whether search mapping data corresponding to the received logical block address is included in the second mapping data; receiving, by the memory device, normal data and the logical block address from the memory controller during a data programming operation, storing the normal data in the memory cell array, and then leaving mapping data corresponding to the logical block address among the second mapping data in the page buffer group; and storing the mapping data remaining in the page buffer group in the memory cell array during the mapping data refresh operation.

Drawings

Fig. 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating a structure of the memory device of fig. 1.

Fig. 3 is a diagram illustrating an embodiment of the memory cell array of fig. 2.

Fig. 4 is a circuit diagram illustrating a memory block BLKa among the memory blocks BLK1 through BLKz of fig. 3.

Fig. 5 is a circuit diagram illustrating another embodiment of a memory block BLKb among the memory blocks BLK1 through BLKz of fig. 3.

Fig. 6 is a diagram illustrating division of an area of a memory cell array according to a program operation.

Fig. 7 is a diagram illustrating page buffers included in the page buffer group of fig. 2.

Fig. 8 is a diagram illustrating a load operation of mapping data according to an embodiment of the present disclosure.

Fig. 9 is a flowchart illustrating a mapping data search operation according to an embodiment of the present disclosure.

Fig. 10 is a diagram illustrating movement of mapping data during a mapping data search operation according to an embodiment of the present disclosure.

Fig. 11 is a diagram illustrating signals transmitted between a memory controller and a memory device during a mapping data search operation according to an embodiment of the present disclosure.

Fig. 12 is a diagram illustrating movement of data during an update operation of the data according to an embodiment of the present disclosure.

Fig. 13 is a diagram illustrating signals transmitted between a memory controller and a memory device during a program operation of data according to an embodiment of the present disclosure.

Fig. 14 is a diagram illustrating movement of mapping data during a refresh operation of the mapping data according to an embodiment of the present disclosure.

Fig. 15 is a diagram illustrating signals sent between a memory controller and a memory device during a refresh operation of mapped data according to an embodiment of the present disclosure.

Fig. 16 is a diagram illustrating another embodiment of the memory controller of fig. 1.

Fig. 17 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 18 is a block diagram illustrating a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

Detailed Description

Only the specific structural or functional descriptions of embodiments according to the concepts disclosed in the present specification or application are shown to describe embodiments according to the concepts disclosed in the present disclosure. Embodiments according to the disclosed concept can be implemented in various forms, and the description is not limited to the embodiments described in the present specification or application.

Hereinafter, the present disclosure will be described in detail by describing embodiments thereof with reference to the accompanying drawings. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

Referring to fig. 1, a memory device 50 may include a memory device 100 and a memory controller 200 controlling an operation of the memory device. The storage device 50 is a device that stores data under the control of a host 300 (e.g., a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or a car infotainment system).

The storage device 50 may be manufactured as one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the storage device 50 may be configured as any of various types of storage devices, such as a multi-media card in the form of an SSD, MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Universal Serial Bus (USB) storage device, a universal flash memory (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a Compact Flash (CF) card, a smart media card, and a memory stick.

The storage device 50 may be manufactured in any of various types of packages. For example, the storage device 50 may be manufactured in any of various types of package types such as a Package On Package (POP), a System In Package (SIP), a System On Chip (SOC), a multi-chip package (MCP), a Chip On Board (COB), a wafer-level manufacturing package (WFP), and a wafer-level package on package (WSP).

The memory device 100 may store normal data and mapping data. For example, the normal data is data associated with normal operation of a device including the memory apparatus 100. The mapping data is data indicating how the normal memory is laid out in the memory device 100. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array 110, the memory cell array 110 including a plurality of memory cells storing normal data and mapping data.

Each memory cell may be configured as a Single Level Cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a Triple Level Cell (TLC) storing three data bits, or a Quadruple Level Cell (QLC) storing four data bits.

The memory cell array 110 may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. The memory block may be a unit for erasing data. In an embodiment, memory device 100 may include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4(LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory devices, Resistive Random Access Memory (RRAM), phase change memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), spin torque transfer random access memory (STT-RAM), and the like. In this specification, for convenience of description, it is assumed that the memory device 100 includes a NAND flash memory.

The memory device 100 is configured to receive a command and an address from the memory controller 200 and access a region in the memory cell array selected by the address. That is, the memory device 100 may perform a command-based operation on the area selected by the address. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. During a programming operation, the memory device 100 may program data to a region selected by an address. During a read operation, the memory device 100 may read data from an area selected by an address. During an erase operation, the memory device 100 may erase data stored in an area selected by an address.

In an embodiment, the memory device 100 may include a page buffer group 123. During a program operation, the page buffer group 123 receives and temporarily stores data to be programmed, and then stores the temporarily stored data in the memory cell array 110. In addition, during a read operation, the page buffer group 123 reads data stored in the memory cell array 110 and outputs the read data to the memory controller 200. In addition, the page buffer group 123 may read and store the mapping data stored in the memory cell array 110. The page buffer group 123 may perform an operation of searching for mapping data corresponding to a Logical Block Address (LBA) among the stored mapping data by receiving the LBA from the storage controller 200.

The memory controller 200 controls the overall operation of the memory device 50.

When power is applied to the storage device 50, the storage controller 200 may execute the firmware FW. When the memory device 100 is a flash memory device, the memory controller 200 may operate firmware such as a Flash Translation Layer (FTL) for controlling communication between the host 300 and the memory device 100.

In an embodiment, the memory controller 200 may receive mapping data from the memory device 100 and store the mapping data. In an embodiment, the storage controller 200 may receive data and Logical Block Addresses (LBAs) from the host 300 and use the mapping data to convert the LBAs into Physical Block Addresses (PBAs) indicating addresses of memory units to store the data included in the memory device 100.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. During a programming operation, the storage controller 200 may provide the memory device 100 with program commands, LBAs, and normal data. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and PBA to the memory device 100.

In an embodiment, the memory controller 200 may generate and send program commands, addresses, and data to the memory device 100 regardless of a request from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations (e.g., programming operations for wear leveling and programming operations for garbage collection).

In an embodiment, the memory controller 200 may control at least two memory devices 100. In this case, the memory controller 200 may control the memory device 100 according to the interleaving method to improve the operation performance. The interleaving method may be an operation method that overlaps operation periods of at least two memory devices 100.

In an embodiment, memory controller 200 may include a processor 210 and a memory buffer 220.

The processor 210 may control the overall operation of the memory controller 200 and perform logical operations. The processor 210 may communicate with an external host 300 and with the memory device 100. Additionally, the processor 210 may be in communication with a memory buffer 220. The processor 210 may control the operation of the storage device 50 using the memory buffer 220 as an operating memory, a cache memory, or a buffer memory.

The processor 210 may perform the functions of a Flash Translation Layer (FTL). The processor 210 may convert a Logical Block Address (LBA) provided from the host 300 into a Physical Block Address (PBA) through the FTL. The FTL can use the mapping data to convert LBAs to PBAs. The FTL may perform an address translation operation using a mapping table stored in the memory buffer 220.

For an embodiment, processor 210 is configured to randomize data received from host 300. For example, the processor 210 may randomize data received from the host 300 using a randomization seed. The randomized data is provided to the memory device 100 as data to be stored and programmed in the memory cell array 110.

The processor 210 is configured to derandomize data received from the memory device 100 during a read operation. For example, the processor 210 may use the derandomization seed to derandomize data received from the memory device. The derandomized data can be output to the host 300.

As an embodiment, the processor 210 may utilize driver software or firmware to perform the randomization and derandomization.

The memory buffer 220 may be used as an operation memory, a cache memory, or a buffer memory of the processor 210. Memory buffer 220 may store code and commands that are executed by processor 210. The memory buffer 220 may store mapping data. The memory buffer 220 may store data processed by the processor 210. Memory buffer 220 may include Static RAM (SRAM) or Dynamic RAM (DRAM).

Memory buffer 220 may include a write/read buffer 221 and a map cache buffer 222.

The write/read buffer 221 stores normal data received from the host 300 during a program operation and transmits the stored data to the memory device 100. In addition, the write/read buffer 221 stores normal data received from the memory device 100 during a read operation and transmits the stored data to the host 300.

The map cache buffer 222 may receive map data from the memory device 100 and store the map data. For example, during a power-on operation of the memory device, the memory device 100 may read some of the mapping data stored in the memory cell array 110 and transmit the read data to the memory controller 200, and the memory controller 200 may store the mapping data received from the memory device 100 in the mapping cache buffer 222.

The host 300 may communicate with the storage device 50 using AT least one of various communication methods such as Universal Serial Bus (USB), serial AT attachment (SATA), serial attached SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory AT high speed (NVMe), universal flash memory (UFS), Secure Digital (SD), Multi Media Card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered dual inline memory (rdimm), and load reduced DIMM (lrdimm).

The memory device 50 according to the above-described embodiment of the present disclosure may read first mapping data among mapping data stored in the memory cell array 110 of the memory device 100 to store the first mapping data in the mapping cache buffer 222 of the memory controller 200, and may read second mapping data to store in the page buffer group 123 of the memory device 100. Accordingly, a data storage capacity capable of storing the read mapping data may be increased.

In an embodiment, the first mapping data may be cold data having a relatively low number of accesses among the mapping data stored in the memory cell array 110, and the second mapping data may be hot data having a relatively high number of accesses among the mapping data stored in the memory cell array 110. In addition, in an embodiment, the first mapping data may be mapping data that is first read through a storage capacity of the mapping cache buffer 222 among mapping data stored in the memory cell array 110, and the second mapping data may be mapping data that is read through a mapping data storage capacity of the page buffer group 123 after reading the first mapping data among mapping data stored in the memory cell array 110.

Fig. 2 is a diagram illustrating a structure of the memory device of fig. 1.

Referring to fig. 2, the memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

Memory cell array 110 includes a plurality of memory blocks BLK1 through BLKz. A plurality of memory blocks BLK1 through BLKz are connected to address decoder 121 through row lines RL. A plurality of memory blocks BLK1 through BLKz are connected to the page buffer group 123 through bit lines BL1 through BLm. As an embodiment, at least one memory block (e.g., BLK1) among the plurality of memory blocks BLK1 through BLKz may be a system block. The system block may store the read reclamation table and the mapping data. The mapping data may include a plurality of mapping tables. A detailed description of the mapping data is provided later. Each of the plurality of memory blocks BLK1 through BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line among a plurality of memory cells are defined as one page. That is, the memory cell array 110 is configured by a plurality of pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 through BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one dummy cell may be connected in series between the drain select transistor and the memory cell and between the source select transistor and the memory cell.

Each memory cell of memory device 100 may be configured as a Single Level Cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a Triple Level Cell (TLC) storing three data bits, or a Quadruple Level Cell (QLC) storing four data bits.

The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input/output circuit 124, and a sensing circuit 125.

The peripheral circuit 120 drives the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

Address decoder 121 is connected to memory cell array 110 by row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and a common source line. According to an embodiment of the present disclosure, the word lines may include a normal word line and a dummy word line. According to an embodiment of the present disclosure, the row line RL may further include a pipe select line.

Address decoder 121 is configured to operate in response to control by control logic 130. Address decoder 121 receives address ADDR from control logic 130.

The address decoder 121 is configured to decode a block address of the received address ADDR. The address decoder 121 selects at least one memory block among the memory blocks BLK1 through BLKz according to the decoded block address. The address decoder 121 is configured to decode a row address RADD of the received address ADDR. The address decoder 121 may select at least one word line of the selected memory block by applying a voltage supplied from the voltage generator 122 to the at least one word line WL according to the decoded row address RADD.

During a program operation, the address decoder 121 may apply a program voltage to a selected word line and apply a pass voltage having a level less than that of the program voltage to unselected word lines. During a program verify operation, the address decoder 121 may apply a verify voltage to a selected word line and a verify pass voltage having a level greater than that of the verify voltage to unselected word lines.

During a read operation, the address decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage having a level greater than that of the read voltage to unselected word lines.

According to an embodiment of the present disclosure, the erase operation of the memory device 100 is performed in units of memory blocks. The address ADDR input to the memory device 100 during the erase operation includes a block address. The address decoder 121 may decode a block address and select one memory block according to the decoded block address. During an erase operation, the address decoder 121 may apply a ground voltage to word lines input to a selected memory block.

According to an embodiment of the present disclosure, the address decoder 121 may be configured to decode a column address of the transmitted address ADDR. The decoded column address may be transferred to the page buffer group 123. By way of example, address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

The voltage generator 122 is configured to generate a plurality of operating voltages Vop using an external power supply voltage supplied to the memory device 100. The voltage generator 122 operates in response to control by the control logic 130.

As an example, the voltage generator 122 may generate the internal supply voltage by adjusting the external supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operation voltage of the memory device 100.

As an embodiment, the voltage generator 122 may generate the plurality of operating voltages Vop using an external power supply voltage or an internal power supply voltage. The voltage generator 122 may be configured to generate various voltages required by the memory device 100. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

To generate the plurality of operating voltages Vop having various voltage levels, the voltage generator 122 may include a plurality of pumping capacitors that receive the internal voltage and selectively enable the plurality of pumping capacitors to generate the plurality of operating voltages Vop in response to the control logic 130.

The generated plurality of operating voltages Vop may be supplied to the memory cell array 110 through the address decoder 121.

The page buffer group 123 includes first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm are connected to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm operate in response to control of the control logic 130.

The first to mth page buffers PB1 to PBm communicate DATA with the DATA input/output circuit 124. At the time of programming, the first to mth page buffers PB1 to PBm receive DATA to be stored through the DATA input/output circuit 124 and the DATA line DL.

During a program operation, when a program pulse is applied to a selected word line, the first to mth page buffers PB1 to PBm may transfer DATA to be stored (i.e., DATA received through the DATA input/output circuit 124) to selected memory cells through the bit lines BL1 to BLm. The memory cells of the selected page are programmed according to the transferred DATA. A memory cell connected to a bit line applied with a program permission voltage (e.g., ground voltage) may have an increased threshold voltage. The threshold voltage of the memory cell connected to the bit line to which the program-inhibit voltage (e.g., power supply voltage) is applied may be maintained. During a program verify operation, the first to mth page buffers PB1 to PBm read DATA stored in the memory cells from the selected memory cells through the bit lines BL1 to BLm.

During a read operation, the page buffer group 123 may read DATA from the memory cells of the selected page through the bit line BL and store the read DATA in the first to mth page buffers PB1 to PBm.

During an erase operation, the page buffer group 123 may float the bit line BL. As an embodiment, the page buffer group 123 may include a column selection circuit.

During the map data load operation, the first to mth page buffers PB1 to PBm may read first map data among the map data stored in the system block BLK 1. The read first mapping data is transmitted to the memory controller 200 of fig. 1 through the data input/output circuit 124. In addition, during the map data load operation, the first to mth page buffers PB1 to PBm read second map data among the map data stored in the system block BLK1 and store the read second map data. During the mapping data search operation, the first to mth page buffers PB1 to PBm may search the stored second mapping data for mapping data corresponding to the LBA received from the memory controller 200.

The data input/output circuit 124 is connected to the first to mth page buffers PB1 to PBm through the data line DL. The data input/output circuit 124 operates in response to control by the control logic 130.

The DATA input/output circuit 124 may include a plurality of input/output buffers (not shown) that receive input DATA. During a program operation, the DATA input/output circuit 124 receives normal DATA to be stored from an external controller (not shown). During a read operation, the DATA input/output circuit 124 outputs normal DATA transferred from the first to mth page buffers PB1 to PBm included in the page buffer group 123 to an external controller.

During a read operation or a verify operation, the sensing circuit 125 may generate a reference current in response to a signal of the permission bit VRYBIT generated by the control logic 130, and may compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic 130.

The control logic 130 may be connected to the address decoder 121, the voltage generator 122, the page buffer group 123, the data input/output circuit 124, and the sensing circuit 125. Control logic 130 may be configured to control all operations of memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be control logic circuitry that operates according to an algorithm and/or a processor that executes control logic code.

Control logic 130 may generate various signals to control peripheral circuitry 120 in response to commands CMD and addresses ADDR. For example, the control logic 130 may generate an operation signal OPSIG, a row address RADD, a read-write circuit control signal PBSIGNALS, and a permission bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 may output an operation signal OPSIG to the voltage generator 122, a row address RADD to the address decoder 121, a read-write control signal to the page buffer group 123, and a permission bit VRYBIT to the sensing circuit 125. In addition, control logic 130 may determine whether the verify operation passed or failed in response to PASS signal PASS or FAIL signal FAIL output by sensing circuit 125.

In an embodiment, the control logic 130 may store data received from the memory controller 200 in the page buffers 123 of the page buffer group 123 under the control of the memory controller 200.

The control logic 130 may program normal data or mapping data stored in the page buffers 123 of the page buffer group 123 to the memory cell array 110 under the control of the memory controller 200.

For example, when the control logic 130 receives a program command from the memory controller 200, the control logic 130 may program normal data stored in the page buffers 123 of the page buffer group 123 in the memory cell array 110 in response to the program command. When control logic 130 receives the mapping data refresh command from memory controller 200, control logic 130 may program the searched mapping data stored in page buffers 123 of page buffer group 123 in system block BLK1 of memory cell array 110 in response to the mapping data refresh command.

The control logic 130 may read normal data stored in the memory cell array 110 under the control of the memory controller 200. Specifically, the control logic 130 may first program data stored in the page buffers 123 of the page buffer group 123 in the memory cell array 110 and then store data read from the memory cell array 110 in the page buffers 123 of the page buffer group 123. The control logic 130 may provide the data stored in the page buffers of the page buffer group 123 to the memory controller 200 through the data input/output circuit 124.

The control logic 130 may read the mapping data stored in the system block BLK1 of the memory cell array 110 under the control of the memory controller 200. Specifically, the control logic 130 may provide the first mapping data among the mapping data read from the system block BLK1 to the memory controller 200 through the data input/output circuit 124. In addition, the control logic 130 may store second mapping data among the mapping data read from the system block BLK 1.

Fig. 3 is a diagram illustrating an embodiment of the memory cell array of fig. 2.

Referring to fig. 3, the memory cell array 110 includes a plurality of memory blocks BLK1 through BLKz. Each memory block has a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. These plural memory cells are arranged along the + X direction, + Y direction, and + Z direction. The structure of each memory block is described in more detail with reference to fig. 4 and 5.

Fig. 4 is a circuit diagram illustrating a memory block BLKa among the memory blocks BLK1 through BLKz of fig. 3.

Referring to fig. 4, the memory block BLKa includes a plurality of cell strings CS11 through CS1m and CS21 through CS2 m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in the row direction (i.e., + X direction). In fig. 5, two cell strings are arranged in the column direction (i.e., + Y direction). However, this is for convenience of description, and it is understood that three or more cell strings may be arranged in the column direction.

Each of the plurality of cell strings CS11 through CS1m and CS21 through CS2m includes at least one source select transistor SST, first through nth memory cells MC1 through MCn, a tube transistor PT, and at least one drain select transistor DST.

Each of the memory cells MC1 to MCn and the selection transistors SST and DST may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating film, a charge storage film, and a barrier insulating film. As an embodiment, pillars for providing channel layers may be disposed in respective cell strings. As an embodiment, pillars for providing at least one of a channel layer, a tunnel insulating film, a charge storage film, and a blocking insulating film may be disposed in the respective cell strings.

The source selection transistors SST of the respective cell strings are connected between the common source line CSL and the memory cells MC1 to MCp.

As an embodiment, the source selection transistors of the cell strings arranged in the same row are connected to a source selection line extending in the row direction, and the source selection transistors of the cell strings arranged in different rows are connected to different source selection lines. In fig. 4, the source select transistors of the cell strings CS11 to CS1m of the first row are connected to a first source select line SSL 1. The source select transistors of the cell strings CS21 to CS2m of the second row are connected to a second source select line SSL 2.

As another embodiment, the source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

The first to nth memory cells MC1 to MCn of the respective cell strings are connected between the source selection transistor SST and the drain selection transistor DST.

The first through nth memory cells MC1 through MCn may be divided into first through pth memory cells MC1 through MCp and (p +1) th through nth memory cells MCp +1 through MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in a direction opposite to the + Z direction, and are connected in series between the source selection transistor SST and the tube transistor PT. The (p +1) th to nth memory cells MCp +1 to MCn are sequentially arranged in the + Z direction and are connected in series between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the (p +1) th to nth memory cells MCp +1 to MCn are connected to each other through a pipe transistor PT. The gates of the first through nth memory cells MC1 through MCn of the respective cell strings are connected to the first through nth word lines WL1 through WLn, respectively.

The gate of the tube transistor PT of each cell string is connected to the line PL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp +1 to MCn. The cell string arranged in the row direction is connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m of the first row are connected to a first drain select line DSL 1. The drain select transistors of the cell strings CS21 to CS2m of the second row are connected to a second drain select line DSL 2.

The cell strings arranged in the column direction are connected to bit lines extending in the column direction. In fig. 4, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL 1. The cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

Memory cells connected to the same word line in cell strings arranged in the row direction are configured into one page. For example, memory cells connected to the first word line WL1 among the cell strings CS11 through CS1m of the first row are arranged by one page. The memory cells connected to the first word line WL1 among the cell strings CS21 through CS2m of the second row configure another page. The cell strings arranged in one row direction may be selected by selecting any one of the drain select lines DSL1 and DSL 2. One page of the selected cell string may be selected by selecting any one of the word lines WL1 through WLn.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to SC2m arranged in the row direction may be connected to bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to odd-numbered bit lines, respectively.

As an embodiment, at least one of the first through nth memory cells MC1 through MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MCp +1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKa improves, however, the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa may be reduced, however, the reliability of the operation of the memory block BLKa may be reduced.

In order to effectively control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation of the memory block BLKa, a program operation for all or part of the dummy memory cells may be performed. When an erase operation is performed after a program operation is performed, the dummy memory cells may have a desired threshold voltage by controlling voltages applied to dummy word lines connected to the respective dummy memory cells.

Fig. 5 is a circuit diagram illustrating another embodiment of a memory block BLKb among the memory blocks BLK1 through BLKz of fig. 3.

Referring to fig. 5, the memory block BLKb includes a plurality of cell strings CS11 'to CS1 m' and CS21 'to CS2 m'. Each of the plurality of cell strings CS11 'to CS1 m' and CS21 'to CS2 m' extends along the + Z direction. Each of the plurality of cell strings CS11 ' to CS1m ' and CS21 ' to CS2m ' includes at least one source select transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain select transistor DST stacked on a substrate (not shown) under the memory block BLK1 '.

The source selection transistors SST of the respective cell strings are connected between the common source line CSL and the memory cells MC1 to MCn. The source selection transistors of the cell strings arranged in the same row are connected to the same source selection line. The source selection transistors of the cell strings CS11 'to CS1 m' arranged in the first row are connected to a first source selection line SSL 1. The source selection transistors of the cell strings CS21 'to CS2 m' arranged in the second row are connected to a second source selection line SSL 2. As another embodiment, the source select transistors of the cell strings CS11 'to CS1 m' and CS21 'to CS2 m' may be commonly connected to one source select line.

The first to nth memory cells MC1 to MCn of the respective cell strings are connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first through nth memory cells MC1 through MCn are connected to the first through nth word lines WL1 through WLn, respectively.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 'to CS1 m' of the first row are connected to a first drain select line DSL 1. The drain select transistors of the cell strings CS21 'to CS2 m' of the second row are connected to a second drain select line DSL 2.

As a result, the memory block BLKb of fig. 5 has an equivalent circuit similar to that of the memory block BLKa of fig. 4, except that the pipe transistors PT are excluded from the respective cell strings.

As another embodiment, an even bit line and an odd bit line may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11 'to CS1 m' or CS21 'to CS2 m' arranged in the row direction may be connected to even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 'to CS1 m' or CS21 'to CS2 m' arranged in the row direction may be connected to odd bit lines, respectively.

As an embodiment, at least one of the first through nth memory cells MC1 through MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 through MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKb improves, however, the size of the memory block BLKb increases. As fewer memory cells are provided, the size of the memory block BLKb may be reduced, however, the reliability of the operation of the memory block BLKb may be reduced.

In order to effectively control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation for the memory block BLKb, a program operation for all or part of the dummy memory cells may be performed. When an erase operation is performed after a program operation is performed, the dummy memory cells may have a desired threshold voltage by controlling voltages applied to dummy word lines connected to the respective dummy memory cells.

Fig. 6 is a diagram illustrating division of an area of a memory cell array according to a program operation.

Referring to fig. 6, the memory cell array 110 may divide a storage space into a static SLC region, a dynamic SLC region, and a TLC region according to a programming method during a programming operation.

For example, the static SLC region and the dynamic SLC region are regions programmed with the SLC programming method during a programming operation, and the TLC region is a region programmed with the TLC programming method during a programming operation.

In order to improve the program operation speed and stability during the program operation, the memory device receives data to be programmed and then programs the received data in a static SLC region or a dynamic SLC region in an SLC programming method. Thereafter, during background operation of the memory device, data stored in the static SLC region or the dynamic SLC region is read and the read data is programmed in the TLC region.

Accordingly, the programming operation speed and data reliability may be improved by performing the programming operation in an SLC programming method during the programming operation, and the data storage efficiency may be improved by programming data stored in a static SLC region or a dynamic SLC region in a TLC programming method during a background operation (e.g., a garbage collection operation).

The static SLC region is a region fixed as much as the set data capacity of the memory cell array 110, and the dynamic SLC region is a region variable according to the capacity of data to be programmed. Thus, the dynamic SLC region may be adjacent to the static SLC region or may be disposed between TLC regions.

Fig. 7 is a diagram illustrating page buffers included in the page buffer group of fig. 2.

Each of the plurality of page buffers PB1 through PBm may include a Main Buffer, a Cache Buffer, a first Map Buffer 1st Map Buffer, and a second Map Buffer 2nd Map Buffer.

The Main Buffer of each of the page buffers PB1 through PBm may be referred to as a Main Buffer stage 123A, the Cache Buffer of each of the page buffers PB1 through PBm may be referred to as a Cache Buffer stage 123B, the first Map Buffer 1st Map Buffer of each of the page buffers PB1 through PBm may be referred to as a first Map Buffer stage 123C, and the second Map Buffer 2nd Map Buffer of each of the page buffers PB1 through PBm may be referred to as a second Map Buffer stage 123D.

During a program operation, the main buffer stage 123A may adjust the potential levels of the bit lines BL 1-BLm of fig. 2 according to the stored data. During a read operation, the main buffer stage 123A may sense the potential or the amount of current of the bit lines BL1 through BLm and store the sensed data.

During a programming operation, the cache buffer stage 123B may receive data to be programmed received from outside the memory device 100 (e.g., the memory controller 200 of fig. 1), temporarily store the data, and send the temporarily stored data to the main buffer stage 123A. During a read operation, the cache buffer stage 123B may receive sensed data from the main buffer stage 123A and send the sensed data to outside of the memory device 100 (e.g., the memory controller 200 of fig. 1).

During the mapping data loading operation, the first mapping buffer stage 123C stores second mapping data among the mapping data stored in the system block.

During a mapping data search operation, the second mapping buffer stage 123D stores Logical Block Addresses (LBAs) received from outside the memory device 100 (e.g., the memory controller 200 of fig. 1).

During the mapping data search operation, each of the page buffers PB1 through PBm may search whether mapping data corresponding to LBAs stored in the second mapping buffer stage 123D are stored in the first mapping buffer stage 123C.

Fig. 8 is a diagram illustrating a load operation of mapping data according to an embodiment of the present disclosure.

Referring to fig. 8, during a load operation of the mapping data, the mapping data stored in the System Block of the memory device may be read and stored in the mapping cache buffer 222 of the memory controller and the page buffer group 123 of the memory device.

For example, the first mapping data G1 among the mapping data stored in the System Block of the memory device may be read by the page buffer group 123 of the memory device, and the read first mapping data G1 may be transmitted to the mapping cache buffer 222 of the memory controller and stored. The second mapping data G2 among the mapping data stored in the System Block can be read by the page buffer group 123 and can be stored.

For example, the first mapping data G1 may be cold data having a relatively low number of accesses among the mapping data stored in the System Block, and the second mapping data G2 may be hot data having a relatively high number of accesses among the mapping data stored in the System Block.

In another embodiment, the first mapping data G1 may be mapping data stored in the System Block that is read first by the storage capacity of the mapping cache buffer 222, and the second mapping data G2 may be mapping data stored in the System Block that is read by the mapping data storage capacity of the page buffer group 123 after reading the first mapping data G1.

Fig. 9 is a flowchart illustrating a mapping data search operation according to an embodiment of the present disclosure.

Fig. 10 is a diagram illustrating movement of mapping data during a mapping data search operation according to an embodiment of the present disclosure.

Fig. 11 is a diagram illustrating signals transmitted between a memory controller and a memory device during a mapping data search operation according to an embodiment of the present disclosure.

A mapping data search operation according to an embodiment of the present disclosure is described below with reference to fig. 1, 2, and 9 to 11.

In step S910, upon receiving the command 00h, the System address System ADDR, the logical block address LBA, and the address Length information Length of the logical block address from the memory controller 200, the memory device 100 reads mapping data corresponding to the System address System ADDR among the mapping data stored in the System blocks of the memory cell array 110, and stores the mapping data in the mapping cache buffer 222 of the memory controller 200 and the first mapping buffer stage 123C of the page buffer group 123. For example, a first mapping data among the read mapping data may be stored in the mapping cache buffer, and a second mapping data may be stored in the first mapping buffer stage 123C.

In addition, the logical block address LBA is stored in the second mapping buffer stage 123D according to the received logical block address LBA and the address Length information Length of the logical block address.

In step S920, a command 33h corresponding to the mapping data search operation is received from the storage controller 200, and the control logic 130 of the memory device 100 checks whether mapping data corresponding to the logical block address LBA stored in the second mapping buffer stage 123D is stored in the first mapping buffer stage 123C in response to the command 33 h.

As a result of the check of the above-described step S920, when the mapping data corresponding to the logical block address LBA stored in the second mapping buffer stage 123D is stored in the first mapping buffer stage 123C, yes in step S930, the control logic 130 of the memory device 100 sets the status register signal SRBUS <0> to logic high and transmits the status register signal SRBUS <0> to the memory controller 200.

The memory controller 200 may identify that the LBA sent to the memory device 100 matches (corresponds to) the second mapping data loaded in the first mapping buffer stage 123C based on the logic high status register signal SRBUS <0 >.

Thereafter, a state checking operation may be performed, and the result of the state checking operation may be output to the memory controller 200 as the state register information SR.

As a result of the check of the above-described step S920, when the mapping data corresponding to the logical block address LBA stored in the second mapping buffer stage 123D is not stored in the first mapping buffer stage 123C, no in step S950, the control logic 120 of the memory device 130 controls the peripheral circuit 120 to read other mapping data stored in the system block (e.g., BLK 1). Thus, new second mapping data is loaded to the first mapping buffer stage 123C. Thereafter, the operation is repeated from the above step S920.

As described above, according to the embodiment of the present disclosure, when the logical block address LBA is received from the storage controller 200, the second mapping data stored in the first mapping buffer stage 123C of the page buffer group 123 may be searched for mapping data corresponding to the received logical block address LBA.

When the storage controller 200 receives the logical block address LBA from the host 300, the storage controller 200 may perform a mapping data search operation among first mapping data stored in the mapping cache buffer 222 of the storage controller 200 according to the received logical block address LBA, or may perform a mapping data search operation among second mapping data stored in the first mapping buffer stage 123C by transmitting the logical block address LBA to the memory device. For example, when the logical block address LBA received from the host 300 corresponds to cold data, a mapping data search operation may be performed among first mapping data stored in the mapping cache buffer 222 of the storage controller 200, and when the logical block address LBA received from the host 300 corresponds to hot data, a mapping data search operation may be performed among second mapping data stored in the first mapping buffer stage 123C.

Fig. 12 is a diagram illustrating movement of data during an update operation of the data according to an embodiment of the present disclosure.

Fig. 13 is a diagram illustrating signals transmitted between a memory controller and a memory device during a program operation of data according to an embodiment of the present disclosure.

The operation of data programming according to an embodiment of the present disclosure is described below with reference to fig. 1, 2, 12, and 13.

As a result of the above-described mapped DATA search operation according to fig. 9, when the status register signal SRBUS <0> of logic high is received from the memory device 100, the memory controller 200 transmits a command 80h corresponding to a program operation, a logical block address LBA, address Length information Length of the logical block address, and normal DATA to be programmed to the memory device 100.

The page buffer group 123 of the memory device 100 receives and stores the inputted normal data. For example, the cache buffer stage 123B of the page buffer group 123 receives and temporarily stores normal data, and transmits the temporarily stored normal data to the main buffer stage 123A. At this time, among the mapping data stored in the first mapping buffer stage 123C, mapping data matching the logical block addresses LBA may be retained.

In response to the specific command 77h, the memory device 100 performs a refresh operation of the normal data stored in the main buffer stage 123A, i.e., a program operation of storing the normal data stored in the main buffer stage 123A in a selected region of the memory cell array 110.

The programming operation may be performed in an SLC programming method. That is, normal data is programmed in a static SLC region or a dynamic SLC region of a memory space of the memory cell array 110 in an SLC programming method. Accordingly, during a program operation, each of the page buffers PB1 through PBm of the page buffer group 123 may perform a program operation using only one buffer (i.e., a main buffer).

Thereafter, a state checking operation according to the result of the program operation may be performed, and the result of the state checking operation may be output to the memory controller 200 as the state register information SR.

According to the above-described embodiment of the present disclosure, when the logical block address LBA received from the host 300 does not match the mapping data stored in the mapping cache buffer 222 of the storage controller 200 and the first mapping buffer stage 123C of the page buffer group, new mapping data is read and stored in the first mapping buffer stage 123C of the page buffer group. In this case, the operation of loading the new mapping data to the memory controller 200 may be skipped after the new mapping data is stored in the page buffer group, thereby improving the operation speed of the memory device 50.

Fig. 14 is a diagram illustrating movement of mapping data during a refresh operation of the mapping data according to an embodiment of the present disclosure.

Fig. 15 is a diagram illustrating signals sent between a memory controller and a memory device during a refresh operation of mapped data according to an embodiment of the present disclosure.

The refresh operation of the mapping data according to the embodiment of the present disclosure will be described as follows with reference to fig. 1, 2, 14, and 15.

When the above-described update operation of the data of fig. 12 and 13 is repeatedly performed, the matched mapping data may be accumulated in the page buffer group 123 of the memory device 100.

For example, the command 80h, the logical block address LBA, and the address Length information Length of the logical block address corresponding to the program operation may be continuously transmitted to the memory device 100, and thus the memory device 100 may repeatedly perform the program operation of the normal data a plurality of times.

In this case, the matched mapping data is accumulated in the first mapping buffer stage 123C of the page buffer group 123.

When the matched mapping data is accumulated in the first mapping buffer stage 123C, the memory device 100 performs a refresh operation of the mapping data stored in the first mapping buffer stage 123C in response to the specific command 78 h.

For example, the mapping data stored in the first mapping buffer stage 123C is temporarily transmitted to the main buffer stage 123A and temporarily stored. The peripheral circuit 120 of the memory device 100 performs a refresh operation of the mapping data stored in the main buffer stage 123A, i.e., a program operation of storing the mapping data in a selected region of the memory cell array 110. At this time, the selected area may be a storage area other than the system block BLK 1.

The programming operation may be performed in an SLC programming method. That is, the mapping data is programmed in a static SLC region or a dynamic SLC region of the memory space of the memory cell array 110 in the SLC programming method. Accordingly, during a program operation, each of the page buffers PB1 through PBm of the page buffer group 123 may perform a program operation using only one buffer (i.e., a main buffer).

Thereafter, a state checking operation according to the result of the program operation may be performed, and the result of the state checking operation may be output to the memory controller 200 as the state register information SR.

According to the above-described embodiment of the present disclosure, the mapping data stored in the page buffer group 123 is programmed in the selected storage area of the memory cell array 110 during the refresh operation of the mapping data. Accordingly, an operation of receiving the mapping data from the memory controller 200 does not occur, and thus the operation speed of the memory device 50 can be improved.

Fig. 16 is a diagram illustrating another embodiment of the memory controller of fig. 1.

Referring to fig. 16, a memory controller 1000 is connected to a Host and a memory device. The memory controller 1000 is configured to access the memory device in response to a request from the Host. For example, the memory controller 1000 is configured to control write operations, read operations, erase operations, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the Host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

Memory controller 1000 may include a processor 1010, a memory buffer 1020, an Error Correction Component (ECC)1030, a host interface 1040, a buffer controller 1050, a memory interface 1060, and a bus 1070.

Bus 1070 may be configured to provide a channel between components of memory controller 1000.

The processor 1010 may control the overall operation of the memory controller 1000 and may perform logical operations. The processor 1010 may communicate with an external host through a host interface 1040 and with a memory device through a memory interface 1060. Additionally, processor 1010 may communicate with memory buffer 1020 through buffer controller 1050. The processor 1010 may control the operation of the storage device using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

Processor 1010 may perform the functions of a Flash Translation Layer (FTL). Processor 1010 may convert Logical Block Addresses (LBAs) provided by a host to Physical Block Addresses (PBAs) through the FTL. The FTL can receive LBAs using the mapping data and convert the LBAs to PBAs. The FTL may perform an address translation operation using the mapping data stored in the memory buffer 1020.

Processor 1010 is configured to randomize data received from Host. For example, processor 1010 may randomize data received from Host using a randomization seed. The randomized data is provided to the memory device as data to be stored and programmed to the memory cell array.

The processor 1010 is configured to derandomize data received from the memory device during a read operation. For example, the processor 1010 may de-randomize data received from the memory device using a de-randomization seed. The derandomized data may be output to the Host.

As an embodiment, the processor 1010 may perform randomization and derandomization by driving software or firmware.

Memory buffer 1020 may be used as an operating memory, cache memory, or buffer memory for processor 1010. Memory buffer 1020 may store codes and commands that are executed by processor 1010. Memory buffer 1020 may store mapping data. Memory buffer 1020 may store data processed by processor 1010. Memory buffer 1020 may include static ram (sram) or dynamic ram (dram).

ECC1030 may perform error correction. ECC1030 may perform error correction coding (ECC coding) based on data to be written to the memory device through memory interface 1060. The error correction encoded data may be transferred to the memory device through the memory interface 1060. ECC1030 may perform error correction decoding (ECC decoding) on data received from a memory device through memory interface 1060. For example, ECC1030 may be included in memory interface 1060 as a component of memory interface 1060.

Host interface 1040 is configured to communicate with an external host under the control of processor 1010. The host interface 1040 may be configured to perform communication using AT least one of various communication methods such as Universal Serial Bus (USB), serial AT attachment (SATA), serial attached SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), peripheral component interconnect express (PCI express), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), Multi Media Card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered memory (rdimm), and load reduced DIMM (lrdimm).

The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

The memory interface 1060 is configured to communicate with memory devices under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory devices over the channels.

For example, memory controller 1000 may not include memory buffer 1020 and buffer controller 1050.

For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a non-volatile memory device (e.g., read-only memory) disposed within the memory controller 1000. As another example, the processor 1010 may load code from a memory device through the memory interface 1060.

For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may be configured to transmit data within the memory controller 1000, and the control bus may be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus may be separate from each other and may not interfere or interact with each other. The data bus may be connected to a host interface 1040, a buffer controller 1050, an ECC1030, and a memory interface 1060. The control bus may be connected to a host interface 1040, processor 1010, buffer controller 1050, memory buffer 1202, and memory interface 1060.

Fig. 17 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 17, the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory controller 2100 may be implemented identically to the memory controller 200 described with reference to FIG. 1.

For example, memory controller 2100 may include components such as Random Access Memory (RAM), a processor, a host interface, a memory interface, and ECC.

The memory controller 2100 may communicate with an external device through the connector 2300. The storage controller 2100 may communicate with external devices (e.g., hosts) according to a particular communication standard. For example, the storage controller 2100 is configured to communicate with external devices through at least one of various communication standards such as Universal Serial Bus (USB), multi-media card (MMC), embedded MMC (mcm), Peripheral Component Interconnect (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash (UFS), Wi-Fi, bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the various communication standards described above.

For example, memory device 2200 may be configured from various non-volatile memory elements such as electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), and spin torque magnetic RAM (STT-MRAM).

The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card such as a PC card (personal computer memory card international association (PCMCIA)), a compact flash Card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a universal flash memory (UFS).

Fig. 18 is a block diagram illustrating a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 18, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through the signal connector 3001, and receives power PWR through the power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

According to an embodiment of the present disclosure, the SSD controller 3210 may perform the functions of the storage controller 200 described with reference to fig. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, signal SIG may be a signal based on an interface between host 3100 and SSD 3200. For example, the signal SIG may be a signal defined by at least one of interfaces such as Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (mcm), Peripheral Component Interconnect (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash (UFS), Wi-Fi, bluetooth, and NVMe.

The auxiliary power supply device 3230 is connected to the host 3100 through a power supply connector 3002. The auxiliary power supply device 3230 may receive power PWR from the host 3100 and may be charged with the power. When the power supply from the host 3100 is not smooth, the auxiliary power supply device 3230 may provide the power of the SSD 3200. For example, the auxiliary power supply device 3230 may be provided in the SSD 3200 or may be provided outside the SSD 3200. For example, the auxiliary power supply device 3230 may be provided on a main board and may supply auxiliary power to the SSD 3200.

The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322 n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Fig. 19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 19, the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components, an Operating System (OS), user programs, and the like included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. that controls components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may operate as a main memory, operating memory, buffer memory, or cache memory for the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR2 SDRAM, DDR3SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a Package On Package (POP) and provided as one semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communication such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), long term evolution, Wimax, WLAN, UWB, bluetooth, and Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

The memory module 4400 may store data. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transmit data stored in the memory module 4400 to the application processor 4100. For example, the memory module 4400 may be implemented as a nonvolatile semiconductor memory element such as a phase change ram (pram), a magnetic ram (mram), a resistance ram (rram), a NAND flash memory, a NOR flash memory, and a three-dimensional NAND flash memory. For example, the memory module 4400 may be provided as a removable storage device (removable drive) such as a memory card and an external drive of the user system 4000.

For example, the memory module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate the same as the memory device 100 described with reference to fig. 1. The memory module 4400 may operate the same as the memory device 50 described with reference to fig. 1.

The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, user interface 4500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touch screens, touch pads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. The user interface 4500 may include user output interfaces such as Liquid Crystal Displays (LCDs), Organic Light Emitting Diode (OLED) display devices, active matrix OLED (amoled) display devices, LEDs, speakers, and monitors.

Although the detailed description of the present disclosure describes specific embodiments, various modifications may be made without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by equivalents of the claims of the present disclosure and the following claims.

Cross Reference to Related Applications

The present application claims priority from korean patent application No. 10-2020-0068098, filed on 5.6.2020 by the korean intellectual property office, the entire disclosure of which is incorporated herein by reference.