阅读说明：本技术 半导体装置的制造方法 (Method for manufacturing semiconductor device ) 是由 陈仕承 江国诚 林志昌 于 2021-06-30 设计创作，主要内容包括：一种半导体装置的制造方法,包括提供具有半导体通道层和设置于半导体通道层之间的多层外延层的一鳍片。多层外延层包括设置于第二、第三外延层之间的第一外延层。第一外延层具有第一蚀刻速率,第二和第三外延层具有大于第一蚀刻速率的第二蚀刻速率。方法还包括横向蚀刻第一、第二和第三外延层,以在多层外延层的相对侧表面上提供外凸的侧壁轮廓。方法还包括在相邻半导体通道层之间形成内部间隔物。内部间隔物沿着第一内部间隔物侧壁表面与多层外延层的外凸的侧壁轮廓相接。方法还包括用一栅极结构的一部分替代每一个多层外延层。(A method for fabricating a semiconductor device includes providing a fin having semiconductor channel layers and a multi-layer epitaxial layer disposed between the semiconductor channel layers. The multi-layer epitaxial layer includes a first epitaxial layer disposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second and third epitaxial layers to provide convex sidewall profiles on opposite side surfaces of the multi-layer epitaxial layer. The method also includes forming an inner spacer between adjacent semiconductor channel layers. The inner spacer meets the convex sidewall profile of the multi-layer epitaxial layer along a first inner spacer sidewall surface. The method further includes replacing each of the plurality of epitaxial layers with a portion of a gate structure.)

1. A method of manufacturing a semiconductor device, comprising:

providing a fin comprising a plurality of semiconductor channel layers and a plurality of multi-layer epitaxial layers disposed between the semiconductor channel layers, wherein each of the multi-layer epitaxial layers comprises a first epitaxial layer between a second epitaxial layer and a third epitaxial layer, wherein the first epitaxial layer has a first etch rate and the second epitaxial layer and the third epitaxial layer have a second etch rate greater than the first etch rate;

laterally etching the first epitaxial layer, the second epitaxial layer and the third epitaxial layer to provide a convex sidewall profile on opposing side surfaces of the multi-layer epitaxial layer;

forming an inner spacer between adjacent layers of the semiconductor channel layer, wherein the inner spacer is along a first inner spacer sidewall surface to meet the convex sidewall profile of the multi-layer epitaxial layer; and

each of the multi-layer epitaxial layers is replaced with a portion of a gate structure that provides the convex sidewall profile provided by the multi-layer epitaxial layers that were previously laterally etched.

Technical Field

Embodiments of the present invention relate to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an optimized interface profile of an internal spacer/metal gate layer and a semiconductor device manufactured thereby.

Background

The electronics industry is increasingly demanding smaller and faster electronic devices that can simultaneously support more and more complex functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low cost, high performance and low power Integrated Circuits (ICs). To date, a significant portion of these goals have been achieved by shrinking the size (e.g., minimum feature size) of semiconductor integrated circuits and thereby increasing production efficiency and reducing associated costs. However, such size reduction also increases the complexity of the semiconductor processing steps. Accordingly, similar advances in semiconductor processing and technology are needed to achieve continued advances in semiconductor integrated circuits and devices.

Recently, multi-gate devices (multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling (gate-channel coupling), reducing OFF-state current (OFF-state current), and reducing short-channel effects (SCEs). A fin field effect transistor (FinFET) is one type of multi-gate device that has been introduced. Fin field effect transistors (finfets) are named for their fin structures that extend from a substrate on which they are formed and are used to form the channel of a field effect transistor. Another multi-gate device that aims to address performance challenges associated with fin field effect transistors (finfets) is a gate-all-around (GAA) transistor. Gate-all-around (GAA) transistors are known for their gate structure extending completely around the channel periphery, which provides better static control than fin field effect transistors (finfets). Finfet transistors and gate-all-around (GAA) transistors are compatible with conventional Complementary Metal Oxide Semiconductor (CMOS) processes, and their three-dimensional structure enables them to be actively scaled in size while maintaining gate control and reducing short channel effects.

Typically, a gate-all-around (GAA) transistor may be used, for example, in situations where a fin field effect transistor (FinFET) can no longer meet the performance requirements of the device. However, the fabrication of gate-all-around (GAA) transistors also presents new challenges to semiconductor processing and issues with reliability of related devices. Thus, the prior art is not satisfactory in all respects.

Disclosure of Invention

Some embodiments of the present invention provide a method for fabricating a semiconductor device, the method comprising providing a fin, the fin comprising a plurality of semiconductor channel layers (semiconductor channel layers) and a plurality of multi-layer epitaxial layers (multi-layer epitaxial layers) disposed between the semiconductor channel layers. In some embodiments, each of the plurality of epitaxial layers includes a first epitaxial layer disposed between a second epitaxial layer and a third epitaxial layer. The first epitaxial layer has a first etch rate, and the second epitaxial layer and the third epitaxial layer have a second etch rate (second etch rate) greater than the first etch rate. In some embodiments, the method further comprises laterally etching the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer to provide a convex sidewall profile on opposing side surfaces of the multi-layer epitaxial layer. Thereafter, the method of fabricating the semiconductor device includes forming an inner spacer (inner spacer) between adjacent layers of the semiconductor channel layer. The inner spacer is connected to the outer convex sidewall profile of the multi-layer epitaxial layer along a first inner spacer sidewall surface. In some embodiments, the method of manufacturing a semiconductor device further comprises replacing each of the plurality of epitaxial layers with a portion of a gate structure. The portion of the gate structure provides the convex sidewall profile provided by the multi-layer epitaxial layer that was previously laterally etched.

Some embodiments of the present invention also provide a method of manufacturing a semiconductor device, including providing a first fin (first fin) in a first device type region (first device type region), and providing a second fin (second fin) in a second device type region (second device type region). The first fin and the second fin each include a plurality of channel layers (channels), and a plurality of epitaxial layer stacks (epitaxial layer stacks) located between the channel layers. In some embodiments, the epitaxial layer stack includes a first silicon germanium (SiGe) layer disposed between a second silicon germanium layer and a third silicon germanium layer, the first silicon germanium layer having a first concentration of germanium (Ge), the second silicon germanium layer and the third silicon germanium layer having a second concentration of germanium (Ge), the second concentration being greater than the first concentration. In some embodiments, the method further includes performing a silicon germanium recess process (SiGe recess process) to laterally etch (laterally etch) the first silicon germanium layer, the second silicon germanium layer and the third silicon germanium layer to form an opening (opening) between adjacent channel layers of the channel layers, wherein the etched first silicon germanium layer, the etched second silicon germanium layer and the etched third silicon germanium layer commonly define a convex sidewall profile (convex sidewall profile). In some embodiments, the method further comprises forming an inner spacer (inner spacer) in the opening between adjacent ones of the via layers, wherein the inner spacer is formed along a first inner spacer side wall surface (first inner spacer side wall surface) to interface with the convex side wall profile, and wherein the first inner spacer side wall surface defines a complementary concave profile.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a fin extending from a substrate, wherein the fin includes a plurality of semiconductor channel layers. In some embodiments, the semiconductor device further comprises a portion of a gate structure disposed between adjacent ones of the semiconductor channel layers, wherein opposing sidewall surfaces (opposing side walls) of the portion of the gate structure define a convex profile. In some embodiments, the semiconductor device further comprises inner spacers disposed between adjacent ones of the semiconductor channel layers and on either side of opposing sides of the portion of the gate structure, the inner spacers contacting the convex profile along first surfaces of the inner spacers, and wherein the first surfaces of the inner spacers define a concave profile contacting the convex profile.

Drawings

The present embodiments will be understood more fully from the detailed description given below and from the accompanying drawings. It is emphasized that, according to industry standard practice, many of the components (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a simplified top layout schematic of a multi-gate device according to some embodiments;

fig. 2 is a flow diagram of a method of fabricating semiconductor devices 300 and 302 according to one or more aspects of the present disclosure;

fig. 3A, fig. 4A, fig. 5A, fig. 6A, fig. 7A, fig. 8A, fig. 9A, fig. 10A, fig. 11A, fig. 12A, fig. 13A, fig. 14A, fig. 15, fig. 16, fig. 17, fig. 18, fig. 19, fig. 20 illustrate schematic cross-sectional views of a semiconductor device 300 along a plane that is substantially parallel to a plane defined by section a-a' of fig. 1, in accordance with some embodiments of the present disclosure;

3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B illustrate schematic cross-sectional views of a semiconductor device 302 along a plane that is substantially parallel to a plane defined by section A-A' of FIG. 1, according to some embodiments of the present disclosure;

fig. 4C illustrates an enlarged schematic view of the semiconductor devices 300, 302 of the portion of fig. 4A/4B, according to some embodiments of the present disclosure;

fig. 18A illustrates an enlarged schematic view of the semiconductor device 300 of a portion of fig. 18, in accordance with some embodiments of the present disclosure;

fig. 21 and 22 illustrate a semiconductor device having a tapered sidewall profile according to some embodiments of the present disclosure;

fig. 23 illustrates a semiconductor device including source/drain regions having a T-shaped feature in accordance with some embodiments of the present disclosure;

fig. 23A illustrates an enlarged schematic view of the semiconductor device of a portion of fig. 23, in accordance with some embodiments of the present disclosure;

fig. 24 illustrates a semiconductor device according to some embodiments that includes an interfacial layer extending over the surface of the epitaxial layer, and beyond the surface of the epitaxial layer; and

fig. 24A illustrates an enlarged schematic view of the semiconductor device of a portion of fig. 24, according to some embodiments of the present disclosure.

Wherein the reference numerals are as follows:

100: multi-gate device

104: fin member

105, 107: source/drain region

108: grid structure

200: method of producing a composite material

202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232, 234: step (ii) of

300: p-type device (semiconductor device)

302: n-type device (semiconductor device)

304: substrate

306: fin plate

308, 310: epitaxial layer

312, 314: constituent layer (silicon germanium layer)

316: gate stack

319: sacrificial layer

320: dielectric layer

322: electrode layer

324, 326: hard mask layer

328: spacer layer

330: groove

402: concave (opening)

404: convex profile

502: internal spacer material

702: first dummy spacer layer

802, 1202: patterned photoresist layer

902: first source/drain parts

1102: second dummy spacer layer

1302: second source/drain feature

1502: interlayer dielectric layer

1504: contact etch stop layer

1602: gap

1604: inner concave surface

1702: interfacial layer

1802: dielectric layer with high dielectric constant

1804: metal layer

1902: contact opening

2002: silicide layer

2004: contact metal

2102, 2202: tapered profile

2402, 2404: plane surface

Angle theta

A-A': section plane

W: width of

R: distance between two adjacent plates

Leff: gate length

Detailed Description

The following provides many different embodiments, or examples, for implementing different features of embodiments of the invention. Specific examples of components and arrangements are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first feature being formed over or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. These iterations are for simplicity and clarity and do not in themselves represent a particular relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "below," "above …," "above," and the like, may be used herein to describe one element or component's relationship to another element or component as illustrated. Such spatially relative terms may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be rotated to other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted similarly to the rotated orientations.

It should also be noted that the present disclosure presents embodiments in the form of multi-gate transistors (multi-gate transistors). Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multiple gate devices may include a pmos multiple gate device or an nmos multiple gate device. Because of their fin structure, the particular example presented may refer to them as fin field effect transistors (finfets). The present disclosure also proposes an embodiment of a multi-gate transistor, which is referred to as a gate-all-around (GAA) transistor. A gate-all-around (GAA) transistor includes any device whose gate structure or portion thereof is formed on four sides of (e.g., around a portion of) a channel region. The apparatus proposed by the present disclosure also includes embodiments having a channel region disposed in a semiconductor channel layer. In various embodiments, the semiconductor channel layer may include nanosheet channels (nanosheets channels), nanowire channels (nanowire channels), strip channels, and/or other suitable channel shape configurations. Embodiments of the devices presented in this disclosure may have one or more channel regions (e.g., semiconductor channel layers) associated with a single and continuous gate structure. However, it will be apparent to those skilled in the art that the disclosure may be applied to a single channel (e.g., a single semiconductor channel layer) or any number of channels. It will be apparent to those of ordinary skill in the art that other examples of semiconductor devices may also benefit from aspects of the present disclosure.

Embodiments of the present disclosure provide advantages over the prior art, although it is understood that other embodiments may provide different advantages, that not all advantages need be discussed in the present disclosure, and that not all embodiments have a particular advantage. For example, embodiments discussed in the present disclosure include methods and structures for providing a multi-gate device (e.g., a gate-all-around (GAA) transistor) with an optimized interface profile for an inner spacer/metal gate layer (metal gate layer). For example, the inner spacer is formed between a metal gate layer and a source/drain feature. In at least some prior embodiments, the metal gate layer interfacing with the internal spacers has a concave side wall profile (concave side wall profile) such that the metal gate layer has substantially pointed end portions (e.g., at top and bottom regions of the concave side wall profile of the metal gate layer). In some examples, some existing implementations may result in reduced reliability of the metal gate-source/drain due to the pointed end portions (e.g., which may result in high electric field regions), while also resulting in poor deposition of the high-permittivity dielectric at the inner spacer/metal gate layer interface (e.g., insufficient deposition of the high-permittivity dielectric in some cases resulting in void (void) generation). In contrast, according to some embodiments, the metal gate layer in contact with the inner spacer has a convex sidewall profile (convex sidewall profile), which may avoid reliability problems associated with the pointed end portions of the metal gate layer, while also improving the deposition of high-k dielectric at the inner spacer/metal gate layer interface. In at least some embodiments, the convex sidewall profile may be initially formed during a silicon germanium recess process (SiGe receive process) of a silicon germanium (SiGe) layer, wherein the silicon germanium layer comprises a bi-layer epitaxial layer with high/low germanium concentrations, and wherein the silicon germanium etch rate is dependent on the germanium concentration. The contents and advantages of other embodiments will be apparent to those skilled in the art from a reading of the present disclosure.

For purposes of the following discussion, fig. 1 provides a simplified top-down layout schematic of a multi-gate device 100 according to some embodiments. In various embodiments, the multi-gate device 100 may include a fin field effect transistor device (FinFET device), a gate-all-around (GAA) transistor, or other aspects of multi-gate devices. A multi-gate device 100 may include: a plurality of fin members (or fins) 104 extending from a base, a gate structure 108 disposed over and around the fin members 104, and source/drain regions 105 and 107, wherein the source/drain regions 105 and 107 are in the fin 104, on the fin 104, and/or around the fin 104. Along a plane substantially parallel to a plane defined by section a-a' of fig. 1, a channel region of multi-gate device 100 is disposed within fin 104 and beneath gate structure 108, wherein the channel region may include a plurality of semiconductor channel layers (e.g., when multi-gate device 100 includes a gate-all-around (GAA) transistor). In some embodiments, sidewall spacers may also be formed on the sidewalls of the gate structure 108. Various other components of the multi-gate device 100 are discussed in more detail below with respect to the method of fig. 2.

Referring to fig. 2, a method 200 of fabricating a semiconductor device is shown, including fabrication of semiconductor devices 300 and 302 (e.g., which include multi-gate devices) with optimized inter-spacer/metal gate layer interface profiles, according to various embodiments. The method 200 is discussed below with reference to the fabrication of a gate-all-around (GAA) transistor. However, it is understood that aspects of method 200 may be equally applied to other types of multi-gate devices, or to other types of devices implemented by multi-gate devices, without departing from the scope of this disclosure. In some embodiments, the method 200 may be used to fabricate the multi-gate device 100 as described above with reference to fig. 1. Accordingly, one or more aspects discussed above with reference to the multi-gate device 100 may also be applied in the method 200. It is understood that the method 200 includes process steps characterized by a Complementary Metal Oxide Semiconductor (CMOS) technology, and only a brief description of the process flow is provided herein. Still further, additional steps may be performed before, after, and/or during the method 200.

It is noted that certain aspects of the method 200 are described as being performed in a region of the semiconductor devices 300, 302 that includes a particular device type (e.g., a P-type device or an N-type device). However, if not described as being performed in an area including a particular device type, the steps of method 200 described may be assumed to be performed in multiple areas including multiple device types (e.g., in multiple device type areas). Additionally, in at least some embodiments, the advantages of the convex sidewall profile of the metal gate layer interfacing with the internal spacers are beneficial for both P-type and N-type devices, and in some cases, the physical components of the device structure formed by method 200 may be substantially the same for both P-type and N-type devices. In addition, semiconductor devices such as P-type device 300 and N-type device 302 may include various other devices and components, such as other types of devices, e.g., additional transistors, bipolar junction transistors (bjts), resistors, capacitors, inductors, diodes, fuses, and/or other logic circuits, etc., but are simplified herein for a better understanding of the inventive concepts of the present disclosure. In some embodiments, the semiconductor devices (e.g., P-type device 300 and N-type device 302) include a plurality of semiconductor devices (e.g., transistors) that may be interconnected. Furthermore, it should be noted that the processing steps of method 200, including any illustrations or descriptions given with reference to the figures, are exemplary only and are not intended to be limiting as specifically recited in the claims.

The method 200 begins at step 202, where at step 202 a substrate is provided, the substrate comprising a partially fabricated device. Referring to the example of fig. 3A and 3B, in one embodiment of step 202, a partially fabricated P-type device 300 and a partially fabricated N-type device 302 are provided. Fig. 3A and 3B provide schematic cross-sectional views of an embodiment of a semiconductor device, such as a P-type device 300 and an N-type device 302, drawn along a plane substantially parallel to a plane defined by the cross-section a-a' of fig. 1 (e.g., along the direction of a fin 306). The P-type device 300 and the N-type device 302 may be formed on a substrate 304. In some embodiments, the substrate 304 may be a semiconductor substrate, such as a silicon substrate. The substrate 304 may include various material layers including conductive or insulating layers formed on a semiconductor substrate. As known to those of ordinary skill in the art, the substrate 304 may include various doping configurations, depending on design requirements. The substrate 304 may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 304 may include a compound semiconductor (compound semiconductor) and/or an alloy semiconductor (alloy semiconductor). In addition, the substrate 304 may optionally include an epitaxial layer (epi-layer), may be stress strained (strained) to improve performance, may include a silicon-on-insulator (SOI) structure, and/or may have other suitable reinforcing features.

As shown in fig. 3A and 3B, the P-type device 300 and the N-type device 302 include a fin 306, the fin 306 having a base portion 304A (formed by the base 304), a first constituent epitaxial layer 308, and a fin 306 of a second constituent epitaxial layer 310, wherein the second constituent epitaxial layer 310 is located between the first constituent epitaxial layer 308. In some cases, trench isolation (STI) features may be formed to separate fin 306 from adjacent fins. In one embodiment, the epitaxial layer 308 of the first composition comprises silicon germanium (SiGe) and the epitaxial layer of the second composition 310 comprises silicon (Si). In particular, the epitaxial layer 308 of the first composition further includes constituent layers (constituent layers)312 and 314, wherein the constituent layer 312 is disposed between the constituent layers 314. Thus, in some embodiments, the epitaxial layer 308 may be referred to as a multi-layer epitaxial layer(s) or an epitaxial layer stack(s). In some examples, formation layer 312 includes a silicon germanium (SiGe) layer having a first concentration of germanium and formation layer 314 includes a silicon germanium (SiGe) layer having a second concentration of germanium that is greater than the first concentration. For example, in various embodiments, the constituent layer 312 may comprise a silicon germanium (SiGe) layer having a germanium concentration in the range of about 15% -35%, and the constituent layer 314 may comprise a silicon germanium (SiGe) layer having a germanium concentration in the range of about 25% -40%. In some examples, the ratio of the germanium concentration in constituent layer 314 relative to the germanium concentration in constituent layer 312 is approximately 1.2. As discussed in more detail below, the different germanium concentrations of each of the constituent layers 312, 314 provides different etch rates during a subsequent silicon germanium recess process (SiGe process). In some embodiments, the constituent layer 314 (having a higher germanium concentration) has a higher etch rate than the constituent layer 312 (having a lower germanium concentration). For example, due to the different etch rates of the various layers that make up layers 312 and 314, embodiments of the present disclosure may form an optimized inner spacer/metal gate layer interface profile. It should also be noted that although the epitaxial layers 308, 310 are depicted as having a particular stacking order within the fin 306, where the epitaxial layer 310 is the topmost layer (toplast layer) in the stack of epitaxial layers 308, 310, other configurations are possible. For example, in some cases, epitaxial layer 308 may be the topmost layer in the stack of epitaxial layers 308, 310. In other words, the growth order of the epitaxial layers 308, 310, and thus their stacking order, may be changed or varied from what is depicted in the figures, while remaining within the scope of the present disclosure. Similarly, although the P-type device 300 and the N-type device 302 are illustrated as being formed on the same fin 306, it is understood that the P-type device 300 and the N-type device 302 may be formed on different fins, each extending from the substrate 304.

In various embodiments, the epitaxial layer 310 (e.g., comprising the second composition) or portions thereof may form a channel region of a gate-all-around (GAA) transistor of the P-type device 300 and the N-type device 302. For example, epitaxial layer 310 may be referred to as semiconductor channel layers (Semiconductor channels) used to form a channel region of a gate-all-around (GAA) transistor. In various embodiments, the semiconductor channel layer (e.g., epitaxial layer 310 or portions thereof) may include nanosheet channels (nanoshiet channels), nanowire channels (nanowire channels), stripe channels, and/or other suitable channel shape configurations. The semiconductor channel layer is also used to form a portion of the source/drain features of a gate-all-around (GAA) transistor, as described below.

It should be noted that although fin 306 is shown as including four epitaxial layers 308 and 310, this is for illustrative purposes only and is not intended to limit what is specifically recited in the claims of the present invention. It will be appreciated that any number of epitaxial layers may be formed, wherein, for example, the number of epitaxial layers is determined depending on the number of desired semiconductor channel layers for a gate-all-around (GAA) transistor. In some embodiments, the number of epitaxial layers 310, and also the number of semiconductor channel layers, is between 4 and 10 layers.

In some embodiments, the constituent layers 312, 314 (of the epitaxial layer 308) have a thickness in the range of about 4 nanometers (nm) to 8 nanometers (nm). In some cases, epitaxial layers 310 each have a thickness in the range of about 4-8 nm. As described above, epitaxial layer 310 may serve as a channel region for subsequently formed multi-gate devices (e.g., gate-all-around (GAA) transistors), and its thickness may be selected based at least in part on device performance considerations. The epitaxial layer 308 may be used to define a gap distance (gap distance) between adjacent channel regions of a subsequently formed multi-gate device, and the thickness of the epitaxial layer 308 may also be selected based at least in part on device performance considerations. Furthermore, in some embodiments, for constituent layers 312, 314 having different etch rates due to having different concentrations of germanium, the respective constituent layers 312, 314 may be selected to have a thickness that provides the desired interface profile of the inner spacer/metal gate layer.

The P-type device 300 and the N-type device 302 also include gate stacks (gates) 316 formed over each fin 306 of the P-type device 300 and the N-type device 302. In one embodiment, the gate stack 316 is a dummy (sacrificial) gate stack (gate stack) because the gate stack 316 is subsequently removed and replaced by the final gate stack at a later stage of processing of the P-type device 300 and the N-type device 302. For example, the gate stack 316 may be filled with a high-K dielectric layer (HK) and a metal gate electrode (MG) at a later stage of processing. Although the present discussion is directed to a replacement gate process by forming a dummy gate structure and then replacing it, other configurations are possible (e.g., gate-first processes). The portion of the fin 306 that is below the gate stack 316 may be referred to as the channel region of the P-type device 300 and the N-type device 302. The gate stack 316 may also define a source/drain region of the fin 306, e.g., the region of the fin 306 adjacent to and on opposite sides of the channel region.

In some embodiments, the gate stack 316 includes a dielectric layer 320 and an electrode layer 322. The gate stack 316 may also include one or more hard mask layers 324, 326. In some embodiments, the hard mask layer 324 may comprise an oxide layer, and the hard mask layer 326 may comprise a nitride layer. In some embodiments, dielectric layer 320 comprises silicon oxide. Alternatively or additionally, dielectric layer 320 may include silicon nitride, a high dielectric constant dielectric material, or other suitable materials. In some embodiments, the electrode layer 322 may include polycrystalline silicon (polysilicon). In some embodiments, the oxide of the hard mask layer 324 includes a pad oxide layer (pad oxide layer), which may be a layer includingSiO₂. In some embodiments, the nitride of the hard mask layer 326 comprises a pad nitride layer (pad nitride layer), which may comprise Si₃N₄Silicon oxynitride, or silicon carbide. In some examples, an optional sacrificial layer (sacrificial layer)319 may be formed directly below the dielectric layer 320. Optional sacrificial layer 319 may comprise silicon germanium (SiGe), germanium (Ge), or other suitable material, and may in some cases be used to prevent nanosheet loss (e.g., due to material loss of epitaxial layers 308, 310 during previous processing steps).

In some embodiments, one or more spacer layers 328 may be formed on the sidewalls of the gate stack 316. In some cases, the one or more spacer layers 328 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide nitride (SiCN), silicon oxycarbide (silicon oxycarbide), silicon oxycarbide (SiOCN), a low-k dielectric material (e.g., having a dielectric constant of 'k' <7), and/or combinations thereof. In some embodiments, the one or more spacer layers 328 include multiple layers, such as main spacer layers (main spacers), liner layers (liner layers), and the like.

The method 200 then proceeds to step 204 where a source/drain etch process is performed at step 204. Still referring to fig. 3A and 3B, in an embodiment of step 204, a source/drain etch process is performed on the P-type device 300 and the N-type device 302. In some embodiments, a source/drain etch process is performed to remove the exposed epitaxial layers 308, 310 in the source/drain regions of the P-type device 300 and the N-type device 302 to form trenches (trenches)330 that expose underlying portions of the substrate 304. The source/drain etch process may also expose the side surfaces of epitaxial layer 310, the constituent layers 312, 314, as shown in fig. 3A and 3B. In some embodiments, the source/drain etch process may also remove portions of the one or more spacer layers 328 (e.g., from the top surface of the gate stack 316). In some embodiments, the source/drain etch process may include a dry etch process, a wet etch process, and/or combinations thereof. In various embodiments, the source/drain etch process may be performed simultaneously for the P-type device 300 and the N-type device 302. Alternatively, the source/drain etching process may be performed sequentially, for example, first performing the source/drain etching process on one of the P-type device 300 and the N-type device 302, and then performing the source/drain etching process on the other of the P-type device 300 and the N-type device 302.

The method 200 then proceeds to step 206 where a silicon germanium recess process (SiGe process) is performed in step 206. Refer to fig. 3A, 3B and 4A, 4B, 4C. In an embodiment of step 206, a silicon germanium recess process is performed on the P-type device 300 and the N-type device 302. The silicon germanium recess process includes a lateral etch of each epitaxial layer 308 (including both constituent layers 312 and 314) in the P-type device 300 and the N-type device 302 to form a recess 402 (or opening 402). In some embodiments, the silicon germanium recess process is performed using a dry etch process, a wet etch process, and/or a combination of the foregoing processes. In some cases, the SiGe recessing process may include using standard clean 1(SC-1) solution, ozone (O)₃) Containing ammonium hydroxide (NH)₄OH), hydrogen peroxide (H)₂O₂) And water (H)₂O), hydrofluoric acid (hydrofluoric acid), hydrofluoric acid-containing buffer, and/or fluorine (F) -based (F)₂) The etching solution of (3) to perform etching. In some examples, the fluorine-based etch may include F₂Remote plasma etch (remote plasma etch). As described above, the formation layer 312 includes a silicon germanium (SiGe) layer having a first germanium concentration (e.g., in a range between about 15-35%), and the formation layer 314 includes a silicon germanium (SiGe) layer having a second germanium concentration (e.g., in a range between about 25-40%), with the second germanium concentration being greater than the first germanium concentration. In some embodiments, the constituent layer 314 (having a higher germanium concentration) has a higher etch rate than the constituent layer 312 (having a lower germanium concentration). Thus, during the silicon germanium (SiGe) recess process, the lateral etching of constituent layer 314 will proceed at a faster rate than the lateral etching of constituent layer 312. Depending on the result of the lateral etching,each recessed (etched) silicon germanium layer (constituent layer) 312 and an adjacent recessed silicon germanium layer (constituent layer) 314 (e.g., in contact with the top and bottom surfaces of the respective constituent layer 312) together define an outer profile (covex profiles)404 (fig. 4C) along opposing side surfaces of the constituent layers 312, 314. In various instances, the outer cam profile 404 may be a generally smooth profile. Furthermore, the outer convex profile 404 may have a shape defined by an angle "θ", where the angle "θ" is measured between the surface of the adjacent epitaxial layer 310 and a tangent of the outer convex profile 404 (at an edge of the outer convex profile 404 that meets the adjacent epitaxial layer 310). Profile 404 connecting adjacent epitaxial layers 310). For example, the angle "θ" may be in a range between about 90 degrees and 120 degrees. The angle "θ" may be determined, at least in part, by the etch rate of each of the constituent layers 312 and 314, and thus by the germanium concentration. For example, as the difference in etch rate between the constituent layers 312 and 314 increases, the angle "θ" also increases. In some embodiments, the outer cam profile 404 spans a width "W" of between about 0nm-3 nm. During subsequent stages of processing, as described below, the constituent layers 312, 314 are removed and replaced with a portion of the gate structure (e.g., a metal gate structure) such that the replacement gate structure defines the outer cam profile 404. In many examples, the replacement gate structure will be joined with an inner spacer, which is also described in more detail below. In some embodiments, the SiGe recess process may be performed for both the P-type device 300 and the N-type device 302, or the SiGe recess process may be performed for one of the P-type device 300 and the N-type device first. And then move to the other of the P-type device 300 and the N-type device 302 for the SiGe recess process.

The method 200 then proceeds to step 208 where deposition of an inner spacer material (inner spacer material) is performed in step 208. Referring to fig. 4A, 4B and 5A, 5B, in an embodiment of step 208, an inner spacer material 502 is deposited over the P-type device 300 and the N-type device 302 and within the trench 330. The deposited inner spacer material 502 is also deposited within the recess 402 formed during the silicon germanium (SiGe) recess process of step 206. In some cases, the inner spacer material 502 may have a thickness of about 4-15 nm. In some embodiments, the inner spacer material 502 may include amorphous silicon. In some examples, the inner spacer material 502 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide nitride (SiCN), silicon oxycarbide (silicon oxycarbide), silicon oxycarbide (SiOCN), a low dielectric constant dielectric material (e.g., having a dielectric constant "k" <7), and/or combinations of the foregoing. For example, the inner spacer material 502 may be formed by conformably depositing the inner spacer material 502 over the P-type device 300, the N-type device 302 using, for example, a Chemical Vapor Deposition (CVD) process, a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition (flowable CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, or other suitable process. In some embodiments, the inner spacer material 502 may be deposited on both the P-type device 300 and the N-type device 302, or the inner spacer material 502 may be deposited on one of the P-type device 300 and the N-type device 302 first and then on the other of the P-type device 300 and the N-type device 302.

The method 200 then proceeds to step 210, where an inner spacer etch-back process is performed in step 210. Refer to fig. 5A, 5B and 6A, 6B. In the embodiment of step 210, an internal spacer etch-back process may be performed on the P-type device 300 and the N-type device 302. In various examples, the inner spacer etch-back process is to etch the inner spacers from above the P-type device 300 and the N-type device 302 and along the sidewalls of the trench 330, while the inner spacer material 502 remains disposed within the recesses (receivers) 402, thereby providing inner spacers for the P-type device 300 and the N-type device 302. For example, the inner spacer etch-back process may be performed using a wet etch process, a dry etch process, or a combination of the foregoing processes. In some cases, any remaining portion of the inner spacer material 502 that remains on the top surfaces of the P-type device 300 and N-type device 302 and/or on the sidewalls or bottom surfaces of the trenches 330, such as after an inner spacer etch-back process, may be removed in a subsequent process (e.g., prior to epitaxial growth of the source/drain features). In various examples, the inner spacer material 502 (e.g., remaining disposed within the recess 402) may extend under the one or more spacer layers 328 (formed on the sidewalls of the gate stack 316) and also abut subsequently formed source/drain features, as described below. In some embodiments, the internal spacer etch-back process may be performed on both the P-type device 300 and the N-type device 302, or the internal spacer etch-back process may be performed on one of the P-type device 300 and the N-type device 302 before the other of the P-type device 300 and the N-type device 302.

The method 200 then proceeds to step 212 where a first dummy spacer layer (first dummy spacer layer) is deposited in step 212. Refer to fig. 6A, 6B and 7A, 7B. In an embodiment of step 212, a first dummy spacer layer 702 is deposited over the P-type device 300 and the N-type device 302 and within the trench 330. In some examples, the first dummy spacer layer 702 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide nitride (SiCN), silicon oxycarbide (silicon oxycarbide), silicon oxycarbide (SiOCN), a low-k dielectric material (e.g., having a dielectric constant "k" <7), and/or combinations thereof. For example, the first dummy spacer layer 702 may be formed by conformably depositing the first dummy spacer layer 702 over the P-type device 300, the N-type device 302 using, for example, a Chemical Vapor Deposition (CVD) process, a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition (flowable CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, or other suitable process. In some embodiments, the first dummy spacer layer 702 may be deposited over both the P-type device 300 and the N-type device 302, or the first dummy spacer layer 702 may be deposited over one of the P-type device 300 and the N-type device 302 and then over the other of the P-type device 300 and the N-type device 302.

The method 200 then proceeds to step 214 where the first portion (first portion) of the first dummy spacer layer is removed in step 214. Refer to fig. 7A, 7B and 8A, 8B. In the embodiment of step 214, a photoresist layer is deposited over the P-type device 300 and the N-type device 302 and patterned (e.g., by exposing the photoresist and developing the exposed photoresist) to form a patterned photoresist layer 802, the patterned photoresist layer 802 exposing the P-type device 300 while the patterned photoresist layer 802 remains disposed over the N-type device 302. In some embodiments, after the patterned photoresist layer 802 is formed, the first dummy spacer layer 702 at the P-type device 300 is removed. For example, the first dummy spacer layer 702 is removed using a wet etch process, a dry etch process, or a combination of the foregoing processes. After the first dummy spacer layer 702 is removed from the P-type device 300, the patterned photoresist layer 802 may be removed (e.g., removing the patterned photoresist layer remaining on the N-type device 302) by, for example, solvent, photoresist stripper (resist stripper), ashing (ashing), or other suitable means.

The method 200 then proceeds to step 216 where first source/drain features (first sources/drain features) are formed in step 216. Referring to fig. 9A, 9B, in an embodiment of step 216, a first source/drain feature 902 is formed in the P-type device 300. Thus, the first source/drain feature 902 may comprise a P-type source/drain feature. In some embodiments, the first source/drain feature 902 is formed in a source/drain region on both sides of the gate stack 316 of the P-type device 300 and adjacent to the gate stack 316. For example, a first source/drain feature 902 may be formed within the trench 330 of the P-type device 300 over an exposed portion of the substrate 304. And contacts the adjacent inner spacers 502 and the semiconductor channel layer (epitaxial layer 310) of the P-type device 300. In some embodiments, a clean process may be performed immediately prior to forming the first source/drain features 902. The cleaning process may include wet etching, dry etching, or a combination of the foregoing. Additionally, the cleaning process may remove any remaining portions of the inner spacer material 502 remaining on the top surface of the P-type device 300 and/or on the sidewalls or bottom surface of the trench 330 (e.g., after the inner spacer etch-back process of step 210). In various examples, and during formation of the first source/drain features 902, the N-type device 302 remains protected by the previously deposited first dummy spacer layer 702.

In some embodiments, first source/drain features 902 are formed by epitaxially growing a layer of semiconductor material in the source/drain regions. In various embodiments, the layer of semiconductor material grown to form first source/drain feature 902 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The first source/drain features 902 may be formed by one or more epitaxial (epi) processes. In some embodiments, the first source/drain feature 902 may be in-situ doped during the epitaxial process. For example, in some embodiments, epitaxially grown silicon germanium (SiGe) source/drain features may be doped with boron. In some cases, epitaxially grown silicon (Si) epitaxial source/drain features may be doped with carbon to form Si: c source/drain features doped with phosphorus to form Si: p source/drain features or carbon and phosphorus doped to form SiCP source/drain features. In some embodiments, the first source/drain features 902 are not in-situ doped, but rather the first source/drain features 902 are doped by an implantation process. In some embodiments, first source/drain feature 902 may comprise a P-type source/drain feature, as described above.

The method 200 then proceeds to step 218, where the remaining portions of the first dummy spacer layer are removed in step 218. Refer to fig. 9A, 9B and 10A, 10B. In an embodiment of step 218, the remaining portion of the first dummy spacer layer 702 previously left over the N-type device 302 is removed from the N-type device 302. For example, a wet etch process, a dry etch process, or a combination of the foregoing processes may be used to remove the remaining portion of the first dummy spacer layer 702.

The method 200 then proceeds to step 220 where a second dummy spacer layer (second dummy spacer layer) is deposited in step 220. Refer to fig. 10A, 10B and 11A, 11B. In an embodiment of step 220, a second dummy spacer layer 1102 is deposited over the device P-type device 300 and the N-type device 302 and within the trench 330. In some examples, the second dummy spacer layer 1102 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide nitride (SiCN), silicon oxycarbide (silicon oxycarbide), silicon oxycarbide (SiOCN), a low dielectric constant dielectric material (e.g., having a dielectric constant "k" <7), and/or combinations thereof. For example, the second dummy spacer layer 1102 may be formed by conformably depositing the second dummy spacer layer 1102 over the P-type device 300 and the N-type device 302 using, for example, a Chemical Vapor Deposition (CVD) process, a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition (flowable CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, or other suitable process. In some embodiments, the second dummy spacer layer 1102 may be deposited over both the P-type device 300 and the N-type device 302, or the second dummy spacer layer 1102 may be deposited over one of the P-type device 300 and the N-type device 302 first, and then over the other of the P-type device 300 and the N-type device 302.

The method 200 then proceeds to step 222 where the first portion of the second dummy spacer layer is removed in step 222. Refer to fig. 11A, 11B and 12A, 12B. In one embodiment of step 222, a photoresist layer is deposited and patterned over the P-type device 300 and the N-type device 302 (e.g., by exposing the photoresist and developing the exposed photoresist) to form a patterned photoresist layer 1202, the patterned photoresist layer 802 exposing the N-type device 302 while the patterned photoresist layer 1202 remains disposed over the P-type device 300. In some embodiments, after the patterned photoresist layer 1202 is formed, the second dummy spacer layer 1102 is removed from the N-type device 302. For example, the second dummy spacer layer 1102 is removed using a wet etch process, a dry etch process, or a combination of the foregoing processes. After the second dummy spacer layer 1102 is removed from the device 302, the patterned photoresist layer 1202 may be removed (e.g., the patterned photoresist layer remaining over the P-type device 300 is removed), such as by solvent, photoresist stripper (resist stripper), ashing (ashing), or other suitable means.

The method 200 then proceeds to step 224 where second source/drain features are formed at step 224. Referring to fig. 13A, 13B, in an embodiment of step 224, a second source/drain feature 1302 is formed in the N-type device 302. Thus, the second source/drain feature 1302 may comprise an N-type source/drain feature. In some embodiments, a second source/drain feature 1302 is formed in the source/drain region on both sides of the gate stack 316 of the N-type device 302 and adjacent to the gate stack 316. For example, a second source/drain feature 1302 may be formed within the trench 330 of the N-type device 302 over an exposed portion of the substrate 304. And contacts the adjacent inner spacers 502 and the semiconductor channel layer (epitaxial layer 310) of the N-type device 302. In some embodiments, a second row clean process (e.g., wet etch, dry etch, or a combination of the foregoing) may be performed immediately prior to forming the second source/drain features 1302. In addition, the cleaning process may remove any remaining portions of the inner spacer material 502 remaining on the top surface of the N-type device 302 and/or on the sidewalls or bottom surface of the trench 330 (e.g., after the inner spacer etch-back process of step 210). In various examples, and during the formation of the second source/drain features 1302, the P-type device 300 remains protected by the previously deposited second dummy spacer layer 1102.

In some embodiments, second source/drain features 1302 are formed by epitaxially growing a layer of semiconductor material in the source/drain regions. In various embodiments, the layer of semiconductor material grown to form the second source/drain component 1302 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The second source/drain features 1302 may be formed by one or more epitaxial (epi) processes. In some embodiments, the second source/drain feature 1302 may be in-situ doped during an epitaxial (epi) process. For example, in some embodiments, epitaxially grown silicon germanium (SiGe) source/drain features may be doped with boron. In some cases, epitaxially grown silicon (Si) epitaxial source/drain features may be doped with carbon to form Si: c source/drain features doped with phosphorus to form Si: p source/drain features or carbon and phosphorus doped to form SiCP source/drain features. In some embodiments, the second source/drain feature 1302 is not in-situ doped, but rather the second source/drain feature 1302 is doped using an implantation process.

The method 200 then proceeds to step 226, where at step 226, the remaining portion of the second dummy spacer layer is removed. Refer to fig. 13A, 13B and 14A, 14B. In the embodiment of step 226, the remaining portion of the P-type device 300, i.e., the portion above the P-type device 300, is removed prior to the second dummy spacer layer 1102 being removed from the P-type device 300. For example, the remaining portion of the second dummy spacer layer 1102 is removed using a wet etch process, a dry etch process, or a combination of the foregoing processes.

After removing the remaining portions of the second dummy spacer layer 1102 (step 226), the method 200 proceeds to step 228 where an inter-layer dielectric (ILD layer) is formed and a Chemical Mechanical Polishing (CMP) process is performed in step 228. For clarity of discussion, it should be noted that the remainder of the method 200 (e.g., steps 228, 230, 232, 234) is described with reference to the P-type device 300. It is understood that the description of the remainder of the method 200 (e.g., steps 228, 230, 232, 234) may apply equally to the N-type device 302 discussed above. Referring now to fig. 14A and 15, in one embodiment of step 228, an interlayer dielectric layer 1502 is formed over the P-type device 300 and the N-type device 302. In some embodiments, a Contact Etch Stop Layer (CESL) 1504 is formed over the P-type device 300 and the N-type device 302 before the interlayer dielectric 1502 is formed. In some examples, the contact etch stop layer 1504 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art. The contact etch stop layer 1504 may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process, and/or other suitable deposition or oxidation processes. In some embodiments, the interlayer dielectric layer 1502 comprises a material such as Tetraethoxysilane (TEOS) oxide, undoped Silicate Glass, or doped silicon oxide such as borophosphosilicate Glass (BPSG), Fused Silica Glass (FSG), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), and/or other suitable dielectric materials. The interlayer dielectric layer 1502 may be deposited by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or other suitable deposition technique. In some embodiments, after forming the interlayer dielectric layer 1502, a high temperature heat build-up process (high thermal bucket process) may be performed on the P-type device 300 and the N-type device 302 to anneal the interlayer dielectric layer 1502 (anneal).

In another embodiment of step 228, and after depositing the interlayer dielectric 1502 (and/or the contact etch stop layer 1504 or other dielectric layer), a planarization process may be performed to expose the top surface of the gate stack 316. The planarization process may include a Chemical Mechanical Polishing (CMP) process that removes a portion of the interlayer dielectric layer 1502 (and the contact etch stop layer 1504, if present) overlying the gate stack 316 and planarizes the top surfaces of the P-type device 300 and the N-type device 302. In addition, a Chemical Mechanical Polishing (CMP) process may remove the hard mask layers 324, 326 covering the gate stack 316 to expose the underlying electrode layer 322 of the dummy gate, such as a polysilicon electrode layer.

Thereafter, the method 200 proceeds to step 230, where dummy gates are removed and a channel layer release process is performed. Referring to fig. 15 and 16, in an embodiment of step 230, the exposed electrode layer 322 of the gate stack 316 may be removed by an appropriate etch process, followed by an etch process to remove the dielectric layer 320 and the optional sacrificial layer 319 (if sacrificial layer 319 is formed). In some examples, the etching process may include wet etching, dry etching, or a combination of the foregoing.

After removing the dummy gates, and in another embodiment of step 230, the silicon germanium (SiGe) layers (e.g., comprising layers 312, 314) in the channel regions of the P-type device 300 and the N-type device 302 may be selectively removed (e.g., using a selective etch process), while the silicon (Si) semiconductor channel layer 310 remains in an unetched state. In some examples, the selective removal process of the silicon germanium (SiGe) layer may be referred to as a channel layer release process (e.g., when the semiconductor channel layer 310 is released from the SiGe layer). The selective etching process may be performed by removing a trench (trench) provided by the dummy gate. In some embodiments, the selective etching process may include a selective wet etching process. In some cases, the selective wet etch includes ammonia and/or ozone. As just one example, the selective wet etch process includes tetra-methyl ammonium hydroxide (TMAH). Note that, as the constituent layers 312, 314 of the epitaxial layers are selectively removed, gaps (gaps)1602 may be formed between adjacent nanowires (nanowires) in the channel region (e.g., between adjacent epitaxial layers 310). For example, the gap 1602 may be used to expose a first portion of the epitaxial layer 310 between the opposing inner spacers 502 while a second portion of the epitaxial layer 310 remains covered by the inner spacers 502. Gap 1602 exposes inner concave surfaces (concave surfaces)1604 of inner spacers 502. As described in more detail below, portions of the gate structure for each of the P-type device 300 and the N-type device 302 will be formed within the gaps 1602.

After selectively removing the silicon germanium (SiGe) layer, the method 200 proceeds to step 232 where a gate structure is formed at step 232. The gate structure may include a dielectric layer/metal gate stack of dielectric constant, but other compositions are possible. In some embodiments, the gate structure may form a gate associated with multiple channels provided by multiple exposed semiconductor channel layers (exposed epitaxial layers 310, now with gaps 1602 between epitaxial layers 310) in the channel regions of the P-type device 300 and the N-type device 302. Referring to the example of fig. 16 and 17, in an embodiment of step 232,an Interfacial Layer (IL) 1702 is formed on exposed surfaces of the epitaxial layer 310, including on exposed first portions of the epitaxial layer 310 formed within the gaps 1602 and between the opposing inner spacers 502. In various embodiments, the interfacial layer 1702 may be formed by a thermal oxidation process. In some cases, the thermal oxidation process may include a wet thermal oxidation process or a dry thermal oxidation process. For example, the thermal oxidation process includes exposing the P-type device 300 and the N-type device 302 to an oxygen-containing gas at a temperature between approximately 900 degrees celsius and 1000 degrees celsius. In some embodiments, the interfacial layer 1702 may comprise a dielectric material, such as silicon oxide (SiO)₂) HfSiO or silicon oxynitride (SiON). Note that forming the interfacial layer 1702 by a thermal oxidation process will result in the consumption of at least some silicon (Si) on the surface of the epitaxial layer 310. Thus, the interface layer 1702 may be at least partially embedded along the exposed surface of the epitaxial layer 310. It should be noted that since the thermal oxidation process forms the interface layer 1702 on the exposed portions of the epitaxial layer 310 (between the opposing inner spacer layers 502), while the second portion of the epitaxial layer 310 covered by the inner spacer layers 502 remains protected during the thermal oxidation process, the interface layer 1702 does not extend over the entire surface of the epitaxial layer 310 (between adjacent source/drains).

In another embodiment of step 232, and referring to the example of fig. 17 and 18, a high-K dielectric layer 1802 is formed over the interfacial layer 1702. In some examples, a high-k dielectric layer 1802 may also be formed on the sidewalls 1704 of the one or more spacer layers 328 and on the inner recessed surfaces 1604 of the exposed inner spacers 502. In various embodiments, the interfacial layer 1702 and the high-k dielectric layer 1802 may be collectively defined as a gate dielectric (gate dielectric) for each gate structure in the P-type device 300 and the N-type device 302. In some embodiments, the gate dielectric has a total thickness of about 1-5 nm. As used and described herein, a high-k gate dielectric includes a dielectric material having a high dielectric constant, e.g., a dielectric material having a dielectric constant greater than that of thermal silicon oxide (-3.9).

In some embodiments, the high-k dielectric layer 1802 may include a high-k dielectric layer, such as hafnium oxide (HfO)₂). Alternatively, the high-k dielectric layer 1802 may include other high-k dielectrics, such as titanium dioxide (TiO)₂) Hafnium zirconium oxide (HfZrO), tantalum oxide (Ta)₂O₃) Hafnium silicon oxide (HfSiO)₄) Zirconium dioxide (ZrO)₂) Zirconium silicon oxide (ZrSiO)₂) Lanthanum oxide (LaO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta)₂O₅) Yttrium oxide (Y)₂O₃) Strontium titanate (SrTiO)₃(ii) a STO), barium titanate (BaTiO)₃(ii) a BTO), BaZrO, hafnium lanthanum hafnium oxide (HfLaO), hafnium silicon oxide (HfSiO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate ((Ba, Sr) TiO)₃(ii) a BST), alumina (Al)₂O₃) Silicon nitride (Si)₃N₄) Oxynitride (SiON), combinations of the foregoing, or other suitable materials. In various embodiments, the high-k dielectric layer 1802 may be formed by an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, Pulsed Laser Deposition (PLD), Chemical Vapor Deposition (CVD), and/or other suitable methods.

Still referring to the example of fig. 18, in another embodiment of step 232, a metal gate (metal gate) including a metal layer 1804 is formed over the gate dielectric (e.g., over the interfacial layer 1702 and the high-k dielectric layer 1802). Metal layer 1804 may include a metal, a metal alloy, or a metal suicide. Additionally, the formation of the gate dielectric/metal gate stack may include deposition to form various gate materials, one or more liner layers, and one or more Chemical Mechanical Polishing (CMP) processes to remove excess gate materials and thus planarize the top surfaces of the P-type device 300 and the N-type device 302.

In some embodiments, the metal layer 1804 may comprise a single layer or a multi-layer structure, such as various combinations of metal layers including selected work functions to enhance device performance (work function metal layers), a liner, a wetting layer, an adhesion layer, metal alloys or metal silicides. For example, the metal layer 1804 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metallic materials, or combinations of the foregoing. In various embodiments, metal layer 1804 may be formed by an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, e-beam evaporation, or other suitable process. Furthermore, metal layer 1804 may be formed separately for N-type transistors or P-type transistors (e.g., for P-type device 300 and N-type device 302). In addition, metal layer 1804 may provide an N-type or P-type work function to serve as a gate electrode for a transistor, and in at least some embodiments, metal layer 1804 may comprise a polysilicon layer. With respect to the related devices shown and discussed, the gate structure includes a portion that is embedded in each epitaxial layer 310, and each epitaxial layer 310 provides a semiconductor channel layer for a wrap-around Gate (GAA).

With respect to the formation of the gate structure (step 232), referring to fig. 18 and 18A (shown as a dashed circle region, which is an enlarged view showing a portion of the P-type device 300), it is noted that portions of the gate structure are formed within the regions previously occupied by the silicon germanium (SiGe) layers 312, 314 (e.g., formed within the gaps 1602). Thus, the portion of the gate structure (replacement gate structure) that replaces the silicon germanium layers 312, 314 now defines the outer cam profile 404 (fig. 4C) previously defined by the combination of the recessed silicon germanium layers 312, 314. As described above, the outer cam profile 404 spans a width "W" of between about 0-3 nm. Fig. 18 also shows that the gate structure meets (contacts) the inner spacers 502 along opposite side surfaces of the gate structure. It should also be noted that while the gate structure now defines the outer convex profile 404, the inner spacers 502 that interface (contact) the gate structure define a complementary concave profile (e.g., defined by the inner concave surface 1604). Thus, the gate structure interfacing (contacting) the inner spacer 502 avoids the reliability problems associated with pointed end tip portions (potential end tip portions) of the metal gate structures of at least some prior embodiments, while also improving the deposition of the high dielectric constant dielectric layer 1802 at the inter-spacer/metal gate layer interface.

After forming the gate structure, the method 200 proceeds to step 234 where contact features are formed in step 234. Reference is made to the examples of fig. 18 and 19. In an embodiment of step 234, an etch process may be performed to remove the interlayer dielectric layer 1502 and the contact etch stop layer 1504 in the regions above the first and second source/drain features 902 and 1302 to form contact openings (contacts openings)1902, wherein the contact openings 1902 expose the first and second source/drain features 902 and 1302. In some embodiments, the etching process may include a dry etch process, wherein a portion of the contact etch stop layer 1504 is left on the sidewalls of the contact opening 1902. Referring to fig. 19 and 20, in another embodiment of step 234, source/drain contact features may be formed within contact openings 1902. For example, a silicide layer 2002 and a contact metal 2004 may be formed over the silicide layer 2002 to provide a low resistance contact to the first source/drain portion 902 and the second source/drain portion 1302 of the P-type device 300 and the N-type device 302, respectively. For example, the silicide layer 2002 may include TiSi, NiSi, TiN, and/or other suitable materials. In some embodiments, the contact metal 2004 may include a layer of tungsten, cobalt, or other suitable metal.

In general, semiconductor devices such as P-type device 300 and N-type device 302 may undergo further processing to form various components and regions as is known in the art. For example, further processing may form various contacts/vias (vias)/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate 304 configured to connect the various features to form functional circuitry, which may include one or more gate devices (e.g., one or more gate-all-around (GAA) transistors). In a further development of this example, the multi-layer interconnect feature may include vertical interconnects (vertical interconnects), such as vias or contacts, and horizontal interconnects, such as metal lines. Various interconnect features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form copper-related multilevel interconnects. Moreover, additional processing steps may be performed before, during, and after method 200, and some of the processing steps described above may be modified, replaced, or eliminated in accordance with various embodiments of method 200.

For example, in the method 200, the sidewall profile of the trench 330 (formed by the source/drain etch process of step 204) is shown as a substantially vertical sidewall profile, as shown in fig. 3A. However, in some alternative embodiments, the trench 330 may instead be formed with a tapered sidewall profile. This is shown in the example of fig. 21. Wherein a source/drain etch recess process (step 204) may be used to form trench 330 having tapered profile 2102. Because the groove 330 is formed with the tapered profile 2102, subsequently formed devices (e.g., after forming the contact features (step 234) shown in fig. 22) may likewise have a tapered profile 2202 corresponding to the tapered profile 2102. The effective gate length (effective gate length) "Leff" of the transistor may be defined as the length of a region where the epitaxial layer 310 and adjacent portions of the gate structure contact each other. Accordingly, the gate length of the P-type device 300 and the N-type device 302 may thus be determined, at least in part, by the sidewall profile of the trench 330 (formed by the source/drain etch process of step 204) and by the silicon germanium recess process (SiGe process) (step 206). Thus, as shown in the device of fig. 22, it has a tapered profile 2202, and the gate length "Leff" near the bottom of the tapered profile 2202 will be greater than the gate length disposed up the tapered profile 2202.

As another example, in method 200, side surfaces of inner spacer 502 (e.g., surfaces interfacing with first source/drain feature 902 and/or second source/drain feature 1302) are shown substantially aligned with side surfaces of epitaxial layer 310. Such as shown in fig. 20, 310 disposed above and/or below the interior spacer 502. However, in some alternative embodiments, and in the inner spacer etch-back process of step 210, the inner spacer etch-back process may be used to over-etch the inner spacer material 502 such that the side surfaces of the inner spacer 502 (e.g., the surfaces bordering the first source/drain member 902 and/or the second source/drain member 1302) are recessed a distance "R" inward relative to the sides of the epitaxial layer 310 disposed above and/or below the inner spacer 502, as in fig. 23 (or as presented in the enlarged schematic view of fig. 23A). As a result of the overetch to inner spacer 502, subsequently formed source/drain regions (e.g., having first source/drain feature 902 and/or second source/drain feature 1302) may extend into the recessed regions to form source/drain regions having T-shaped features (e.g., as shown in fig. 23A). Thus, in this case, a portion of the source/drain region is disposed above and/or below the lateral ends (lateralends) of the adjacent epitaxial layer 310.

As yet another example, in method 200, the interface layer 1702 as shown in fig. 17 is mostly embedded along the exposed surface of the epitaxial layer 310 without extending beyond the surface of the epitaxial layer 310. However, in some embodiments, forming the interface layer 1702 (at 232) by a thermal oxidation process may result in the interface layer 1702 not only being partially embedded within the epitaxial layer 310, but also extending partially beyond the surface of the epitaxial layer 310, as shown in fig. 24. To better illustrate this feature, fig. 24A provides an enlarged view of a portion of fig. 24. Fig. 24A shows a plane 2402 that is substantially parallel to the surface of epitaxial layer 310 and a plane 2404 that is substantially parallel to the surface of interface layer 1702, where interface layer 1702 is a plane that extends beyond the surface of epitaxial layer 310 and into gap 1602. It will be appreciated that the embodiments shown in fig. 24 and 24A, with the relative position of the interface layer 1702 extending beyond the surface of the epitaxial layer 310, may also be applied in fig. 17-23 and may not be drawn to scale.

With respect to the description provided herein, methods and structures are disclosed for providing a multi-gate device (e.g., a gate-all-around (GAA) transistor) with an optimized interface profile of the inner spacer/metal gate layer. For example, in some embodiments, a metal gate structure (or a portion thereof) that interfaces with an adjacent inner spacer has a convex sidewall profile (convex sidewall profile), thereby improving device reliability and improving the deposition of high-k dielectrics at the inner spacer/metal gate structure interface. As described above, and in at least some embodiments, the convex sidewall profile may be formed during a silicon germanium recess process (SiGe process) of a silicon germanium (SiGe) layer, wherein the silicon germanium (SiGe) layer comprises a multi-layered epitaxial layer having high/low germanium concentrations, wherein the silicon germanium (SiGe) etch rate depends on the germanium concentration. Those skilled in the art will readily appreciate that the methods and structures described herein may be applied to a variety of other semiconductor devices to advantageously achieve similar benefits from such other devices without departing from the scope of the present disclosure.

Accordingly, one embodiment of the present disclosure describes a method for fabricating a semiconductor device, which includes providing a fin including a plurality of semiconductor channel layers (semiconductor channels) and a plurality of multi-layer epitaxial layers (multi-layer epitaxial layers) disposed between the semiconductor channel layers. In some embodiments, each of the plurality of epitaxial layers includes a first epitaxial layer disposed between a second epitaxial layer and a third epitaxial layer. The first epitaxial layer has a first etch rate, and the second epitaxial layer and the third epitaxial layer have a second etch rate (second etch rate) greater than the first etch rate. In some embodiments, the method further comprises laterally etching the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer to provide a convex sidewall profile on opposing side surfaces of the multi-layer epitaxial layer. Then, the method of manufacturing the semiconductor device includes forming an inner spacer (inner spacer) between adjacent layers of the semiconductor channel layer. The inner spacer is connected to the convex sidewall profile of the multi-layer epitaxial layer along a first inner spacer sidewall surface. In some embodiments, the method of manufacturing a semiconductor device further comprises replacing each of the plurality of epitaxial layers with a portion of a gate structure. The portion of the gate structure provides the convex sidewall profile provided by the multi-layer epitaxial layer that was previously laterally etched.

In some embodiments, each of the aforementioned semiconductor channel layers is comprised of silicon (Si). In some embodiments, the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer comprise silicon germanium (SiGe). In some embodiments, the first epitaxial layer has a first concentration of germanium (Ge), and wherein the second epitaxial layer and the third epitaxial layer have a second concentration of germanium (Ge) that is greater than the first concentration. In some embodiments, the first concentration of germanium is in the range of about 15% to 35%, and the second concentration of germanium is in the range of about 25% to 40%. In some embodiments, a standard clean 1(SC-1) solution, ozone (O3), containing ammonium hydroxide (NH), is used₄OH), hydrogen peroxide (H)₂O₂) And water (H)₂O), hydrofluoric acid (hydrofluoric acid), a buffer containing hydrofluoric acid, and/or a fluorine-based etching solution, and the lateral etching is performed on the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer.

In some embodiments, the fin further comprises a dummy gate stack (dummy gate stack) disposed over a channel region of the fin, and wherein the method of fabricating the semiconductor device further comprises: performing a source/drain etch process to form a trench in a source/drain region adjacent to the dummy gate stack and to expose side surfaces of the semiconductor channel layer and the multi-layer epitaxial layer, prior to the lateral etching; and laterally etching said exposed side surfaces of said multi-layer epitaxial layer to provide said outwardly convex sidewall profile on said opposing side surfaces of said multi-layer epitaxial layer.

In some embodiments, forming the inner spacers further comprises depositing an inner spacer material (inner spacer material) in the trenches and in recesses (recesses) formed by laterally etching the first, second and third epitaxial layers and performing an inner spacer etch back process to provide the inner spacers.

In some embodiments, the method further comprises epitaxially growing a source/drain feature in the trench prior to replacing each of the plurality of epitaxial layers with the portion of the gate structure, wherein the source/drain feature is connected to the inner spacer along a second inner spacer side wall surface (second inner spacer side wall surface) opposite the first inner spacer side wall surface, and wherein the source/drain feature is connected to end portions of the semiconductor channel layer.

In another embodiment, a method of fabricating a semiconductor device is provided, including providing a first fin (first fin) in a first device type region (first device type region), and providing a second fin (second fin) in a second device type region (second device type region). The first fin and the second fin each include a plurality of channel layers (channels), and a plurality of epitaxial layer stacks (epitaxial layer stacks) located between the channel layers. In some embodiments, the epitaxial layer stack includes a first silicon germanium (SiGe) layer disposed between a second silicon germanium layer and a third silicon germanium layer, the first silicon germanium layer having a first concentration of germanium (Ge), the second silicon germanium layer and the third silicon germanium layer having a second concentration of germanium (Ge), the second concentration being greater than the first concentration. In some embodiments, the method further includes performing a silicon germanium recess process (SiGe recess process) to laterally etch (laterally etch) the first silicon germanium layer, the second silicon germanium layer and the third silicon germanium layer to form an opening (opening) between adjacent channel layers of the channel layers, wherein the etched first silicon germanium layer, the etched second silicon germanium layer and the third silicon germanium layer commonly define a convex sidewall profile (convex sidewall profile). In some embodiments, the method further comprises forming an inner spacer (inner spacer) in the opening between adjacent ones of the via layers, wherein the inner spacer is formed along a first inner spacer side wall surface (first inner spacer side wall surface) to interface with the convex side wall profile, and wherein the first inner spacer side wall surface defines a complementary concave profile.

In some embodiments, the method for manufacturing a semiconductor device further includes: prior to the sige recess process, a source/drain etch process is performed to form a trench in a source/drain region.

In some embodiments, the method for manufacturing a semiconductor device further includes: after the formation of the inner spacers, a source/drain feature is epitaxially grown in the trench, wherein the source/drain feature contacts the inner spacers along a second inner spacer side wall surface opposite the first inner spacer side wall surface.

In some embodiments, the method for manufacturing a semiconductor device further includes: after forming the inner spacers and before epitaxially growing the source/drain features in the trench, a clean process is performed to remove remaining portions of the inner spacer material from one or more top surfaces of the semiconductor device, sidewalls of the trench, and a bottom surface of the trench.

In some embodiments, the method for manufacturing a semiconductor device further includes: selectively etching the first, second, and third silicon germanium layers after forming the inner spacers to form gaps (gaps) between adjacent ones of the channel layers; and forming a portion of a gate structure within each of the plurality of gaps, wherein the portion of the gate structure defines the convex sidewall profile previously defined by the etched first sige layer, the second sige layer, and the third sige layer.

In some embodiments, the first device type region comprises a P-type device region and the second device type region comprises an N-type device region.

In some embodiments, the method for manufacturing a semiconductor device further includes: after forming the inner spacer, epitaxially growing a first source/drain feature in the trench in the first device type region while protecting the second device type region with a first dummy spacer layer; and epitaxially growing a second source/drain feature in the trench in the second device type region after epitaxially growing the first source/drain feature while protecting the first device type region with a second dummy spacer layer.

In some embodiments, the first sige layer has a first etch rate, and the second sige layer and the third sige layer have a second etch rate, the second etch rate being greater than the first etch rate.

In another embodiment, a semiconductor device is disclosed that includes a fin extending from a substrate, wherein the fin includes a plurality of semiconductor channel layers. In some embodiments, the semiconductor device further comprises a portion of a gate structure disposed between adjacent ones of the semiconductor channel layers, wherein opposing sidewall surfaces (opposing side walls) of the portion of the gate structure define a convex profile. In some embodiments, the semiconductor device further comprises inner spacers disposed between adjacent ones of the semiconductor channel layers and on either side of opposing sides of the portion of the gate structure, the inner spacers contacting the convex profile along a first surface of the inner spacers, and wherein the first surface of the inner spacers defines a concave profile contacting the convex profile.

In some embodiments, the semiconductor device further comprises a source/drain feature in contact with a second surface (second surfaces) of the inner spacer opposite the first surface and in contact with end portions (end portions) of the semiconductor channel layer. In some embodiments, each of the aforementioned semiconductor channel layers is comprised of silicon (Si).

The components of several embodiments are summarized above so that those skilled in the art can more easily understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present invention should be determined by the appended claims.