阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 王姝雯 廖志腾 陈志山 谢瑞夫 罗裕智 于 2021-08-13 设计创作，主要内容包括：方法包括：在第一鳍上方形成间隔件层的第一部分并且在第二鳍上方形成间隔件层的第二部分；实施第一蚀刻工艺以使间隔件层的第一部分相对于间隔件层的第二部分凹进,以在第一鳍的侧壁上形成第一间隔件；随后实施第二蚀刻工艺以使间隔件层的第二部分相对于第一间隔件凹进,以在第二鳍的侧壁上形成第二间隔件,其中,第二间隔件形成为比第一间隔件的高度大的高度；以及在第一间隔件和第二间隔件之间分别形成第一外延源极/漏极部件和第二外延源极/漏极部件,其中,第一外延源极/漏极部件大于第二外延源极/漏极部件。本申请的实施例还涉及半导体结构及其形成方法。(The method comprises the following steps: forming a first portion of a spacer layer over the first fin and a second portion of the spacer layer over the second fin; performing a first etch process to recess a first portion of the spacer layer relative to a second portion of the spacer layer to form a first spacer on sidewalls of the first fin; subsequently performing a second etching process to recess a second portion of the spacer layer with respect to the first spacer to form a second spacer on the sidewall of the second fin, wherein the second spacer is formed to a height greater than a height of the first spacer; and forming a first epitaxial source/drain feature and a second epitaxial source/drain feature between the first spacer and the second spacer, respectively, wherein the first epitaxial source/drain feature is larger than the second epitaxial source/drain feature. Embodiments of the present application also relate to semiconductor structures and methods of forming the same.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate having a first device region and a second device region;

forming a first semiconductor fin in the first device region and a second semiconductor fin in the second device region;

forming a spacer layer over the substrate, wherein a first portion of the spacer layer is formed over the first semiconductor fin and a second portion of the spacer layer is formed over the second semiconductor fin;

performing a first etch process to recess the first portion of the spacer layer relative to the second portion of the spacer layer to form first fin spacers on sidewalls of the first semiconductor fin;

etching the first semiconductor fin to form first source/drain (S/D) recesses between the first fin spacers;

forming a first epitaxial source/drain feature in the first source/drain recess;

after forming the first epitaxial source/drain features, performing a second etch process to recess the second portion of the spacer layer relative to the first portion of the spacer layer to form second fin spacers on sidewalls of the second semiconductor fin, wherein the second fin spacers are formed to a height greater than a height of the first fin spacers;

etching the second semiconductor fin to form second source/drain recesses between the second fin spacers; and

forming a second epitaxial source/drain feature in the second source/drain recess, wherein the second epitaxial source/drain feature is formed to a size smaller than a size of the first epitaxial source/drain feature.

2. The method of claim 1, wherein the first semiconductor fin is configured to provide a logic device, and wherein the second semiconductor fin is configured to provide a memory device.

3. The method of claim 1, wherein etching the first portion of the spacer layer comprises:

forming a patterned photoresist layer to expose the first portion of the spacer layer but not the second portion of the spacer layer;

performing the first etching process; and

removing the patterned photoresist layer from the substrate after forming the first epitaxial source/drain features and before performing the second etching process.

4. The method of claim 3, wherein the patterned photoresist layer is a first patterned photoresist layer, and wherein etching the second portion of the spacer layer comprises:

forming a second patterned photoresist layer to expose the second portion of the spacer layer but not the first portion of the spacer layer;

performing the second etching process; and

removing the second patterned photoresist layer after forming the second epitaxial source/drain features.

5. The method of claim 1, wherein performing the first etch process comprises adjusting a bias power of the first etch process.

6. The method of claim 5, wherein performing the second etching process comprises intermittently applying an etchant.

7. The method of claim 6, wherein intermittently applying the etchant comprises cyclically recessing the second portion of the spacer layer and redepositing etch byproducts above the second semiconductor fin.

8. The method of claim 1, wherein the first and second semiconductor fins are configured to form devices of a same conductivity type.

9. A method of forming a semiconductor structure, comprising:

forming a first fin and a second fin protruding from a first region of a semiconductor substrate;

forming a third fin protruding from a second region of the semiconductor substrate;

forming a first dummy gate stack over the first fin and the second fin and a second dummy gate stack over the third fin;

depositing a dielectric layer over the first and second dummy gate stacks;

forming a first source/drain (S/D) feature over the first fin and the second fin, comprising:

performing a first etch process to remove portions of the dielectric layer on sidewalls of the first fin and the second fin, forming first Fin Sidewall (FSW) spacers having a first height,

recessing the first fin and the second fin, an

Performing a first epitaxial process to grow the first source/drain feature to merge the recessed first fin and the second fin;

forming a second source/drain feature over the third fin, comprising:

after forming the first source/drain features, performing a second etch process to remove portions of the dielectric layer on sidewalls of the third fin to form second fin sidewall spacers having a second height, wherein the second height is greater than the first height, and wherein the first etch process and the second etch process perform the same etchant,

recessing the third fin, an

Performing a second epitaxial process to grow the second source/drain features between the second fin sidewall spacers; and

replacing the first and second dummy gate stacks with metal gate stacks.

10. A semiconductor structure, comprising:

a first fin and a second fin extending from the semiconductor substrate;

an isolation feature disposed over the semiconductor substrate to separate the first fin and the second fin, wherein the first fin and the second fin have a fin height measured from a top surface of the isolation feature;

a first device over the first fin, the first device comprising:

a first gate stack coupled to the first channel region of the first fin,

first epitaxial source/drain (S/D) features disposed on opposite sides of the first channel region, wherein the first epitaxial source/drain features merge the first fins together, an

A first fin spacer disposed on a sidewall of the first epitaxial source/drain feature, wherein the first fin spacer has a first height measured from the top surface of the isolation feature;

a second device over the second fin, the second device comprising:

a second gate stack coupled with a second channel region of the second fin,

a second epitaxial source/drain feature disposed on an opposite side of the second channel region, an

A second fin spacer disposed on sidewalls of the second epitaxial source/drain feature, wherein the second fin spacer has a second height, measured from the top surface of the isolation feature, that is greater than the first height; and

an inter-layer dielectric (ILD) layer over the first device and the second device, wherein,

the interlevel dielectric layer separates the second epitaxial source/drain features.

Technical Field

Embodiments of the present application relate to semiconductor structures and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in generations of ICs, each of which has smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. Such a scaled-down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of handling and manufacturing the IC.

Multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing Short Channel Effects (SCE). One such multi-gate device that has been introduced is the fin field effect transistor (FinFET). Finfets are known as fin structures that extend from a substrate formed thereon, with the surface of the fin structure serving as the channel region of the FET. Finfets are compatible with conventional Complementary Metal Oxide Semiconductor (CMOS) processes, and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCE. The performance of a FinFET may be controlled and optimized by various features including source and drain features formed in a fin structure (or fin as referred to hereinafter). While current methods of forming source and drain features in finfets are generally adequate, they are not entirely satisfactory in all respects.

Disclosure of Invention

Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a substrate having a first device region and a second device region; forming a first semiconductor fin in the first device region and a second semiconductor fin in the second device region; forming a spacer layer over the substrate, wherein a first portion of the spacer layer is formed over the first semiconductor fin and a second portion of the spacer layer is formed over the second semiconductor fin; performing a first etch process to recess the first portion of the spacer layer relative to the second portion of the spacer layer to form first fin spacers on sidewalls of the first semiconductor fin; etching the first semiconductor fin to form first source/drain (S/D) recesses between the first fin spacers; forming a first epitaxial source/drain feature in the first source/drain recess; after forming the first epitaxial source/drain features, performing a second etch process to recess the second portion of the spacer layer relative to the first portion of the spacer layer to form second fin spacers on sidewalls of the second semiconductor fin, wherein the second fin spacers are formed to a height greater than a height of the first fin spacers; etching the second semiconductor fin to form second source/drain recesses between the second fin spacers; and forming a second epitaxial source/drain feature in the second source/drain recess, wherein the second epitaxial source/drain feature is formed to a size smaller than a size of the first epitaxial source/drain feature.

Other embodiments of the present application provide a method of forming a semiconductor structure, comprising: forming a first fin and a second fin protruding from a first region of a semiconductor substrate; forming a third fin protruding from a second region of the semiconductor substrate; forming a first dummy gate stack over the first fin and the second fin and a second dummy gate stack over the third fin; depositing a dielectric layer over the first and second dummy gate stacks; forming a first source/drain (S/D) feature over the first fin and the second fin, comprising: performing a first etch process to remove portions of the dielectric layer on sidewalls of the first and second fins to form first Fin Sidewall (FSW) spacers having a first height, recessing the first and second fins, and performing a first epitaxial process to grow the first source/drain features to merge the recessed first and second fins; forming a second source/drain feature over the third fin, comprising: after forming the first source/drain features, performing a second etch process to remove portions of the dielectric layer on sidewalls of the third fin to form second fin sidewall spacers having a second height, wherein the second height is greater than the first height, and wherein the first etch process and the second etch process perform the same etchant, recess the third fin, and perform a second epitaxial process to grow the second source/drain features between the second fin sidewall spacers; and replacing the first and second dummy gate stacks with metal gate stacks.

Still other embodiments of the present application provide a semiconductor structure comprising: a first fin and a second fin extending from the semiconductor substrate; an isolation feature disposed over the semiconductor substrate to separate the first fin and the second fin, wherein the first fin and the second fin have a fin height measured from a top surface of the isolation feature; a first device over the first fin, the first device comprising: a first gate stack engaged with a first channel region of the first fin, a first epitaxial source/drain (S/D) feature disposed on opposite sides of the first channel region, wherein the first epitaxial source/drain feature merges the first fins together, and a first fin spacer disposed on a sidewall of the first epitaxial source/drain feature, wherein the first fin spacer has a first height measured from the top surface of the isolation feature; a second device over the second fin, the second device comprising: a second gate stack engaged with a second channel region of the second fin, a second epitaxial source/drain feature disposed on an opposite side of the second channel region, and a second fin spacer disposed on a sidewall of the second epitaxial source/drain feature, wherein the second fin spacer has a second height measured from the top surface of the isolation feature that is greater than the first height; and an interlayer dielectric (ILD) layer over the first device and the second device, wherein the ILD layer separates the second epitaxial source/drain features.

Drawings

The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1, 2A, and 2B are flow diagrams illustrating methods of fabricating a workpiece according to various aspects of the invention.

Fig. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are top views of exemplary workpieces at various stages of manufacture of the methods of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Fig. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 15B are cross-sectional views along the dashed line AA' of the exemplary workpiece depicted in fig. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 15A, respectively, at various stages of manufacture of the method of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Fig. 3C, 4C, 5C, 6C, 7C, 8C, 9C, and 15C are cross-sectional views along dashed line CC' of the exemplary workpiece depicted in fig. 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 15A, respectively, at various stages of manufacture of the method of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Fig. 3D, 4D, 5D, 6D, 7D, 8D, and 9D are cross-sectional views along the dashed line DD' of the exemplary workpiece depicted in fig. 3A, 4A, 5A, 6A, 7A, 8A, and 9A, respectively, at various stages of manufacture of the method of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Fig. 10C, 11C, 12C, 13C, and 15D are cross-sectional views along dashed line EE' of the exemplary workpiece depicted in fig. 10A, 11A, 12A, 13A, and 15A, respectively, at various stages of manufacture of the method of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Fig. 10D, 11D, 12D, and 13D are cross-sectional views along dashed line FF' of the exemplary workpiece depicted in fig. 10A, 11A, 12A, and 13A, respectively, at various stages of manufacture of the method of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Fig. 14B and 15E are cross-sectional views along dashed lines BB' of the exemplary workpiece depicted in fig. 14A and 15A, respectively, at various stages of manufacture of the method of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Fig. 14C and 15F are cross-sectional views along dashed lines GG' of the exemplary workpiece depicted in fig. 14A and 15A, respectively, at various stages of manufacture of the methods of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Fig. 14D and 15G are cross-sectional views along dashed line HH' of the exemplary workpiece depicted in fig. 14A and 15A, respectively, at various stages of manufacture of the method of fig. 1, 2A, and/or 2B, in accordance with various aspects of the present invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following disclosure, the formation of a feature on, connected to, and/or coupled to another feature may include embodiments in which the features are formed in direct contact, and may include embodiments in which additional features may be formed intervening between the features such that the features may not be in direct contact. Also, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above …," "above …," "below …," "below …," "upward," "downward," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) are used for ease of understanding the relationship of one component to another component of the invention. Spatially relative terms are intended to encompass different orientations of the device including the component.

Further, when a value or range of values is described using "about," "about," etc., the term is intended to encompass values within a reasonable range including the value, such as within +/-10% of the value or other value as understood by one of ordinary skill in the art. For example, the term "about 5 nm" encompasses a size range from 4.5nm to 5.5 nm. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

It should be noted that the present invention presents embodiments in the form of a multi-gate transistor or fin-type multi-gate transistor, referred to herein as a FinFET. Such devices may include p-type metal oxide semiconductor FinFET devices or n-type metal oxide semiconductor FinFET devices. The FinFET device may be a double-gate device, a tri-gate device, a bulk device, a silicon-on-insulator (SOI) device, and/or other configurations. Although not depicted, other embodiments suitable for use in a Gate All Around (GAA) device, an omega gate (Ω -gate) device, or a Pi-gate (Π -gate) device may also benefit from aspects of the invention. Further, the present embodiments provide intermediate devices fabricated during processing of the IC or portions thereof, which may include memory (such as static random access memory or SRAM) and/or logic circuitry, passive components (such as resistors, capacitors, and inductors), and active devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFET), Complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

The present invention relates generally to semiconductor devices and their manufacture. More particularly, some embodiments relate to forming source/drain features in device active areas, such as fins, for finfets configured to form logic and memory devices. Finfets have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing Short Channel Effects (SCE). FinFET fabrication processes typically include, among other things, forming epitaxially grown source/drain features by etching and selective epitaxial growth to induce strain effects in the channel region of the FinFET. While current methods of forming finfets are generally adequate, they are not entirely satisfactory in all respects. For example, existing fabrication schemes may lack the ability to independently control the formation of source/drain features to meet different design requirements, such as strain effects and contact resistance, that are applicable to different finfets.

Although not intended to be limiting, the present invention provides methods of forming source and drain features with increased strain effects, reduced contact resistance, and more design freedom than existing methods of forming source/drain features with different characteristics. In some embodiments, source/drain features configured to provide different devices are individually formed to have different shapes and/or sizes. In this embodiment, such different source/drain features are formed by controlling the height of their respective Fin Sidewall (FSW) spacers, which may be fabricated by performing two patterning processes followed by two different etching processes.

Embodiments of the invention provide various advantages, and while it is understood that other embodiments may provide different advantages, not all of the advantages need be discussed herein, and no particular advantage is required for all embodiments. In at least some embodiments, by forming epitaxial source/drain features, carrier mobility is increased and device performance is enhanced.

Fig. 1 is a flow chart of a method 200 for fabricating a workpiece 100 configured to provide various FETs, such as finfets (also referred to as semiconductor structures). Fig. 2A and 2B together illustrate a flow chart of a method 220 for fabricating the workpiece 100, and in particular the source/drain features thereof (which are encompassed by block 210 as shown in fig. 1). Additional steps may be provided before, during, and after method 200 and/or method 220, and some of the steps described may be replaced or eliminated with respect to other embodiments of methods 200 and 220. The various stages of the method 200 and/or 220 are discussed in detail with respect to fig. 3A-15G, where fig. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are top views of the workpiece 100; fig. 3B, fig. 4B, fig. 5B, fig. 6B, fig. 7B, fig. 8B, fig. 9B, fig. 10B, fig. 11B, fig. 12B, fig. 13B, and fig. 15B are cross-sectional views along a broken line AA' of the workpiece 100 depicted in fig. 3A, fig. 4A, fig. 5A, fig. 6A, fig. 7A, fig. 8A, fig. 9A, fig. 10A, fig. 11A, fig. 12A, fig. 13A, and fig. 15A, respectively; fig. 3C, 4C, 5C, 6C, 7C, 8C, 9C, and 15C are cross-sectional views along the dashed line CC' of the workpiece 100 depicted in fig. 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 15A, respectively; FIG. 3D, FIG. 4D, FIG. 5D, FIG. 6D, FIG. 7D, FIG. 8D, and FIG. 9D are cross-sectional views along the dashed line DD' of the workpiece 100 depicted in FIG. 3A, FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, and FIG. 9A, respectively; fig. 10C, 11C, 12C, 13C and 15D are sectional views along the broken line EE' of the workpiece 100 depicted in fig. 10A, 11A, 12A, 13A and 15A, respectively; fig. 10D, 11D, 12D, and 13D are cross-sectional views along the dashed line FF' of the workpiece 100 depicted in fig. 10A, 11A, 12A, and 13A, respectively; fig. 14B and 15E are sectional views along a broken line BB' of the workpiece 100 depicted in fig. 14A and 15A, respectively; FIGS. 14C and 15F are cross-sectional views along dashed lines GG' of the workpiece 100 depicted in FIGS. 14A and 15A, respectively; fig. 14D and 15G are sectional views along a broken line HH' of the workpiece 100 depicted in fig. 14A and 15A, respectively.

Referring first to block 202 of fig. 1 and to fig. 3A-3D, the method 200 receives (or is provided with) a workpiece 100 including a substrate 102. In various examples, the substrate 102 may include an elemental (single element) semiconductor, such as silicon or germanium in a crystalline structure; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide and-Or indium antimonide; non-semiconductor materials, such as soda lime glass, fused silica, fused quartz and/or calcium fluoride (CaF)₂) Other suitable materials, or combinations thereof. In some embodiments, substrate 102 comprises silicon germanium (Si)_1-xGe_x) Wherein the component Ge (x) is from about 5% to about 50%. Further, the silicon-germanium containing substrate 102 may be doped with a p-type dopant, such as boron, gallium, aluminum, indium, other suitable p-type dopants, or combinations thereof.

The composition of the substrate 102 may be uniform or may include various layers. The layers may have similar or different compositions, and in various embodiments, some substrate layers have a non-uniform composition to induce device strain and thereby tune device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates 102. In some such examples, the layers of the substrate 102 may include an insulator, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable insulating materials, or combinations thereof.

In some embodiments, the workpiece 100 includes various doped regions (or wells) formed in or above the substrate 102. Each doped region may be implanted with one or more dopants according to specific design requirements. For example, the n-type well may include n-type dopants, such as phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof, and the p-type well may include p-type dopants, such as boron, indium, gallium, aluminum, other p-type dopants, or combinations thereof. In some embodiments, the substrate 102 includes a doped region having a combination of p-type dopants and n-type dopants. The various doped regions may be formed directly on and/or in the substrate 102, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or a combination thereof. Each of the respective doped regions may be formed by performing an ion implantation process, a diffusion process, other suitable doping process, or a combination thereof.

Referring to block 204 of fig. 1 and referring to fig. 3A-3D, the method 200 forms fin active areas or fins 108A, 108B, 108C, and 108D (collectively referred to as fins 108) extending or protruding from the substrate 102 and separated by the isolation features 104. In the present embodiment, the fins 108 are longitudinally elongated in the X-direction and spaced apart from each other in the Y-direction. The fin 108 may comprise any suitable semiconductor material, including silicon, germanium, silicon germanium, and/or other semiconductor materials. In some embodiments, the fins 108 comprise one or more epitaxially grown semiconductor materials. The fins 108 are formed by selectively etching the isolation features 104 to form recesses, followed by epitaxial growth of one or more semiconductor materials in the recesses and planarization of the semiconductor materials with the isolation features 104. In some embodiments, the fins 108 are formed by patterning the substrate 102 to form the fins 108 separated by trenches, then filling the trenches with a dielectric layer, planarizing the dielectric layer, and selectively etching the dielectric layer to form isolation features 104 between the fins 108. Referring to fig. 3C and 3D, the separation distance between two adjacent fins 108 may be different in different regions defined in the substrate 102. For example, the two fins 108A may be formed to a separation distance S1 that is less than the separation distance S2 between the two fins 108C.

Patterning the substrate 102 may include a series of photolithography and etching processes. The photolithography process may include: forming a photoresist layer (resist) on top of the substrate 102; exposing the resist to the pattern; carrying out a post-exposure baking process; and developing the resist to form a masking device (not shown) comprising the resist. The masking device is then used to etch a trench in the substrate 102, leaving the fin 108 protruding from the substrate 102. The etching process may include dry etching, wet etching, Reactive Ion Etching (RIE), other suitable processes, or combinations thereof. After the etching process is performed, the masking device is removed from the substrate 102 by a suitable method, such as plasma ashing or resist stripping.

Many other embodiments of methods for forming the fins 108 may be suitable. For example, the fins 108 may be patterned using a double patterning or multiple patterning process. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing for the creation of patterns, for example, with pitches less than those obtainable using a single, direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over the substrate 102 and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and then the remaining spacers or mandrels may be used to pattern the fins 108.

In the present embodiment, the isolation member 104 is formed to define and separate regions (or device regions) in the substrate 102. The isolation features 104 may comprise silicon dioxide, a low-k dielectric material (a dielectric material having a dielectric constant less than that of silicon oxide, which has a dielectric constant of approximately 3.9), other suitable materials, or combinations thereof. In some embodiments, the isolation features 104 include shallow trench isolation features (STI), deep trench isolation features (DTI), other types of isolation features, or combinations thereof. For example, the portion of the isolation feature 104 configured as the separation fin 108 may include STI, while the substrate 102 may be embedded in the portion of the isolation feature 104 configured as DTI, which may be formed by recessing the substrate 102 to form a through-thickness trench, subsequently filling the trench with a dielectric material, and planarizing the dielectric material with the substrate 102 to form the DTI. The isolation structure 40 may be deposited by any suitable method, such as Chemical Vapor Deposition (CVD), flowable CVD (fcvd), spin-on-glass (SOG), other suitable methods, or combinations thereof.

The isolation features 104 may separate the substrate 102 into various regions configured to provide different devices. In the depicted embodiment, for example, the substrate 102 includes four exemplary regions (or device regions) 102A, 102B, 102C, and 102D. In some embodiments, regions 102A-102D are designed to independently provide devices of different functionality (such as logic devices or memory (such as SRAM) devices), different conductivity types (such as n-type devices or p-type devices), or combinations thereof. For example, in some embodiments, region 102A and region 102B are configured to provide the same function but different conductivity types of devices. Of course, the present embodiments are not limited to any particular arrangement. For simplicity, in the depicted embodiment, methods 200 and 220 are discussed with reference to region 102A and region 102C configured to provide logic devices and memory devices, respectively, region 102A and region 102B are configured to provide logic devices of different conductivity types, and regions 102C and 102D are configured to provide memory devices of different conductivity types.

Referring to block 206 of fig. 1 and referring to fig. 4A-4D, the method 200 forms a dummy gate stack (alternatively referred to as a placeholder gate) 112 over the fins 108A and 108B and a dummy gate stack 114 over the fins 108C and 108D. In this embodiment, dummy gate stacks 112 and 114 will be replaced by metal gate stacks at a later stage of fabrication. Each dummy gate stack passes through a channel region of the fin 108 and is thus disposed between source/drain features subsequently formed in and/or over the fin 108. The dummy gate stacks 112 and 114 may each include at least a gate electrode including, for example, polysilicon. In some embodiments, each dummy gate stack further includes an interface layer (such as silicon oxide) over the fin 108, a gate dielectric layer (such as silicon oxide) over the interface layer, and a gate electrode (such as polysilicon) over the gate dielectric layer, a hard mask layer, a capping layer, a barrier layer, other suitable layer, or combinations thereof. As depicted herein, a hard mask 120 is formed over the top surfaces of dummy gate stacks 112 and 114 to provide protection for subsequent etch processes. The respective layers of the dummy gate stacks 112 and 114 may be formed by thermal oxidation, chemical oxidation, CVD, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), other suitable methods, or combinations thereof.

The formation of dummy gate stacks 112 and 114 may include forming respective gate material layers and patterning the gate material layers using a photolithography process and etching. The hard mask 120 may be used to pattern the gate material layer. For example, the hard mask 120 may be deposited on the gate material layer and patterned by photolithography and etching processes to include the respective openings. Then, the pattern defined on the hard mask 120 is transferred to the gate material layer by etching, thereby forming the dummy gate stacks 112 and 114. The hard mask 120 may include silicon, nitrogen, oxygen, carbon, other suitable elements, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some examples, hard mask 120 may include a plurality of films, such as a silicon nitride layer over dummy gate stacks 112 and 114 and a silicon oxide layer over the silicon nitride layer. The hard mask 120 may be patterned by any suitable method, such as the methods discussed in detail above with respect to the patterned fin 108.

In some embodiments, gate spacers (not depicted) having a single-layer or multi-layer structure are formed on sidewalls of the dummy gate stacks 112 and 114. The gate spacers may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectric materials, or combinations thereof, and may be formed by depositing a layer of dielectric material and performing an anisotropic etch process to remove portions of the layer, leaving gate spacers on the sidewalls of the dummy gate stacks 112 and 114.

Referring to block 208 of fig. 1 and referring to fig. 5A-5D, the method 200 forms a dielectric layer 126 over the substrate 102, conformally covering the fin 108 and the dummy gate stacks 112 and 114. In the present embodiment, the dielectric layer 126 is configured to provide gate spacers 124 on the sidewalls of the dummy gate stacks 112 and 114 (in addition to or optionally to the gate spacers formed on the sidewalls of the dummy gate stacks 112 and 114 in block 206), and to provide spacers (such as FSW spacers 126A, 126B, 126C, and 126D) on the sidewalls of the fin 108.

The dielectric layer 126 may include silicon, nitrogen, oxygen, carbon, other suitable elements, or combinations thereof. For example, the dielectric layer 126 may include silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, high-k dielectric materials (dielectric materials having a dielectric constant greater than that of silicon oxide, which has a dielectric constant of approximately 3.9), low-k dielectric materials, other dielectric materials, or combinations thereof. In some embodiments, the dielectric layer 126 has a single layer structure. In some embodiments, the dielectric layer 126 has a multilayer structure including at least two material layers. In one such example, the dielectric layer 126 includes a silicon nitride layer and a silicon oxycarbonitride layer. In another example, the dielectric layer 126 includes a silicon nitride layer and a silicon oxynitride layer. In yet another example, the dielectric layer 126 includes a low-k dielectric layer and a silicon nitride layer. The composition of the dielectric layer 126 (and its sublayers) may be selected based on one or more design requirements for appropriate device functions. For example, dielectric materials having different dielectric constants may be selected to achieve desired levels of parasitic capacitance and etch resistance. In some cases, dielectric materials with lower dielectric constants may be suitable for reducing parasitic capacitance, while dielectric materials with higher dielectric constants may be suitable for enhancing protection for subsequent etch processes. Each sub-layer of the dielectric layer 126 may be formed by a suitable deposition method, such as CVD, ALD, FCVD, PVD, other methods, or combinations thereof, to achieve a suitable thickness.

The method 200 proceeds to block 210 to form epitaxial source/drain features in the fin 108, which is further discussed by the method 220 and with reference to fig. 2A, 2B, and 6A-15D.

Referring to block 222 of fig. 2A and referring to fig. 6A-6D, the method 220 forms a patterned photoresist layer 130 over the substrate 102 to expose the region 102A and not the regions 102B-102D. In the present embodiment, the photoresist layer 130 is a tri-layer photoresist that includes a bottom layer 130A, a middle layer 130B over the bottom layer 130A, and a top layer 130C over the middle layer 130B, which together are configured to enhance the results of the photolithography process, such as to improve the resolution of the photolithography process. The various layers of the photoresist layer 130 may be configured with different compositions to achieve enhanced etch selectivity. For example, the bottom layer 130A can be a polymeric antireflective coating, the middle layer 130B can include a polymeric material configured to enhance the photosensitivity of the photoresist layer 130, and the top layer 130C typically includes a photosensitive material (resist). It should be noted that although three layers of the photoresist layer 130 are shown in fig. 6B, respectively, they are collectively depicted as the photoresist layer 130 in the following figures for the sake of simplicity. The photoresist layer 130 may be patterned by a series of photolithography and etching processes similar to those discussed in detail above with respect to the patterned fin 108.

Referring to block 224 of fig. 2A and referring to fig. 7A-7D, the method 220 recesses the dielectric layer 216 to form first Fin Sidewall (FSW) spacers 126A and gate spacers 124. In the present embodiment, referring to fig. 7B and 7C, the method 220 performs an etching process 302 to remove the portion of the dielectric layer 126 located in the region 102A. In the present embodiment, the etch process 302 includes one or more etch processes configured to anisotropically recess portions of the dielectric layer 126, leaving portions of the dielectric layer 126 as FSW spacers 126A on the sidewalls of the fin 108A and gate spacers 124 on the sidewalls of the dummy gate stack 112. In the present embodiment, the etch process 302 is adjusted such that the FSW spacer 126A is defined by a height H1, which height H1 is measured from the top surface of the isolation feature 104.

In some embodiments, the etch process 302 includes one or more dry etch processes that implement any suitable etchant selected according to the composition of the dielectric layer 126. Some exemplary dry etchants include CH₃F、CF₄、NF₃、SF₆、CO、CO₂、SO₂、CH₄、Ar、HBr、O₂He, other suitable etchant, or combinations thereof. In some embodiments, the etch process 302 is performed using a mechanism such as Deep Reactive Ion Etching (DRIE) to enable or enhance the anisotropic etching of the dielectric layer 126.

In the present embodiment, the etch process 302 includes at least a dry etch process that may be adjusted by adjusting one or more parameters, such as bias power, bias voltage, etch temperature, etch pressure, source power, etchant flow rate, other suitable parameters, or a combination thereof. In the present embodiment, the bias power of the etch process 302 is adjusted to control the height H1, which subsequently controls the shape and size of the source/drain features formed over the fin 108A. In this embodiment, for a given amount of etching time, increasing the bias power results in an increased amount of bombardment by the dry etchant particles, which results in a greater amount of dielectric layer 126 being removed and thus a decrease in height H1 of FSW spacer 126A. In the present embodiment, the height H1 is controlled such that the resulting source/drain features formed over two adjacent fins 108A merge together, providing an enlarged source/drain feature that suits certain design requirements. In this regard, the height H1 may be adjusted to be less than about half of the Fin Height (FH) of the fin 108, where FH is measured from the top surface of the isolation member 104. In some embodiments, the ratio of height H1 to FH is about 0.1 to about 0.3. Although the present embodiment is not limited to such dimensions, it should be noted that if the ratio is less than about 0.1, the merged source/drain features may be too small to provide sufficient landing area for subsequently formed source/drain contacts. Furthermore, if the dimensions of the resulting source/drain features are too small, the contact resistance may be inadvertently too high for desired device performance. On the other hand, a ratio greater than about 0.3 may cause the source/drain features to favor vertical growth rather than lateral merging, resulting in the formation of separate, unmerged source/drain features over adjacent fins 108A. In some examples, height H1 may be about 6nm to about 14 nm. In some embodiments, the etch process 302 is performed to remove a small amount of the gate spacers 124, thereby slightly reducing the height and/or thickness of the gate spacers 124. It should be noted that this reduction does not generally affect the overall performance of the gate spacers 124.

Referring to block 226 of fig. 2A and referring to fig. 8A-8D, the method 220 forms source/drain recesses 131 in each exposed fin 108A and between FSW spacers 126A. In the present embodiment, forming the source/drain recesses 131 includes applying an etch process 304, the etch process 304 selectively removing portions of the fin 108A without removing or substantially removing portions of the dummy gate stack 112, the isolation feature 104, or the dielectric layer 126. In the present embodiment, the source/drain recesses 131 are formed to a depth D1. In some examples, the depth D1 may be about 47nm to about 57 nm; of course, the present embodiment is not limited to such a size. In some examples, the ratio of height H1 to depth D1 may be about 1:10 to about 1: 3.

The etching process 304 may be a dry etching process, a wet etching process, other suitable etching process, or a combination thereof. In some embodiments, the wet etching process implements a wet etchant comprising a hydroxide, such as potassium hydroxide (KOH) and/or ammonium hydroxide (NH)₄OH), hydrogen peroxide (H)₂O₂) Sulfuric acid (H)₂SO₄) TMAH, other suitable wet etching solutions, or combinations thereof. For example, the wet etchant may implement NH₄OH-H₂O₂-H₂O mixtures (known as ammonia-peroxide mixtures or APM) or H₂SO₄-H₂O₂Mixture (referred to as sulfuric acid-peroxide mixture or SPM). In some embodiments, the dry etch process employs a dry etchant comprising a fluorine-containing etch gas (such as CF)₄、SF₆、CH₂F₂、CHF₃And/or C₂F₆) Oxygen-containing gas, chlorine-containing gas (such as Cl)₂、CHCl₃、CCl₄And/or BCl₃) Bromine-containing gas (such as HBr and/or CHBr)₃) Iodine-containing gas, He, Ar, O₂Other suitable gases and/or plasmas, or combinations thereof. In some embodiments, the etch process 304 additionally performs an oxidation process. For example, the etch process 304 may expose the fin 108A to an ozone environment, thereby oxidizing portions of the fin 108A exposed by the patterned photoresist layer 130, and the oxidized portions are subsequently removed by a cleaning process and/or an etch process (such as those described herein). After performing the etch process 304, the method 220 may perform a wet clean process using SPM, a diluted HF solution, other suitable solutions, or a combination thereof to remove any etch byproducts.

Referring to block 228 of fig. 2A and referring to fig. 9A-9D, the method 220 forms the first source/drain feature 132 in the source/drain recess 131. In the present embodiment, the method 220 performs an epitaxial process 306 to grow the source/drain features 132. The epitaxial process 306 may be a Selective Epitaxial Growth (SEG) process implemented using any deposition technique, such as a CVD deposition technique (e.g., Vapor Phase Epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable processes, or combinations thereof. The epitaxial process 306 may use gaseous precursors (such as including SiH)₄And/or including GeH₄A germanium-containing gas) and/or a liquid precursor that interacts with the composition of the fin 108A to form an epitaxial Si layer or an epitaxial SiGe layer in the source/drain features 132.

The source/drain features 132 may be doped in situ during the epitaxial process 306 by introducing one or more dopants. Alternatively, the source/drain features 132 (or their layers) may be epitaxially grown using a suitable SEG process, and an implantation process (such as a junction implantation process) is then applied to introduce dopants into the source/drain features 132. The dopant may comprise a p-type dopant (such as boron, BF)₂Aluminum, gallium, and/or indium), n-type dopants (such as phosphorus, arsenic, and/or antimony), other suitable dopants, or combinations thereof. The source/drain features 132 may include a dopant having the sameOne or more epitaxial layers of different concentrations. In some examples, different epitaxial layers may include different types of dopants. The composition of the source/drain features 132 may be selected based on the type of device they are configured to provide. For embodiments in which the source/drain features 132 are configured to provide an n-type device, such as an n-type logic device, the source/drain features 132 include one or more epitaxial Si layers doped with an n-type dopant, such as phosphorus (Si: P). For embodiments in which source/drain features 132 are configured to provide a p-type device, such as a p-type logic device, source/drain features 132 include one or more epitaxial SiGe layers doped with a p-type dopant, such as boron (SiGe: B). In some embodiments, the epitaxial SiGe layer configured for a p-type device further comprises antimony (SiGe: Sn: B) configured to adjust the lattice constant of the epitaxial layer. The epitaxial process 306 may also include performing one or more annealing processes to activate dopants in the source/drain features 132. Suitable annealing processes include Rapid Thermal Annealing (RTA), laser annealing, other suitable processes, or combinations thereof. After the source/drain features 132 are formed, the patterned photoresist layer 130 is removed by a suitable process, such as plasma ashing and/or resist stripping.

In the present embodiment, referring to fig. 9C, an epitaxial process 306 forms the source/drain features 132 from two adjacent source/drain recesses 131 merging adjacent fins 108A together. In the present embodiment, referring to fig. 9B, the incorporation enhances the strain effect on the channel region 140 under the dummy gate stack 112, which may improve the carrier mobility of the resulting device. Furthermore, the enlarged volume of the source/drain features 132 may result in reduced contact resistance and thus enhanced device performance. In some embodiments, the merging creates an air gap (or void) 138 formed between the FSW spacers 126A and under the bottom of the merged source/drain feature 132, providing an additional isolation function for the source/drain feature 132. In addition, the incorporation allows the top surface (ET) of source/drain features 132 to be elongated substantially to width W1' in the direction of dummy gate stack 112 (direction Y), which serves to enlarge the landing area of source/drain contacts that may be subsequently formed thereover. In addition to the height of the FSW spacers 126A (such as height H1), the size and shape of the source/drain features 132 may depend on factors such as the composition of the epitaxial layer, the separation distance S1 between the fins 108A, and/or the deposition conditions of the epitaxial process 306.

In some embodiments, the maximum width W1 of the source/drain features 132 exceeds FH. In some examples, width W1 may be about 65nm to about 75nm, and the ratio of width W1 to FH may be about 1.2 to about 1.4; of course, the present embodiment is not limited to such a size. Further, in the present embodiment, referring to fig. 9B and 9C, the distance H2 between the top surface of the fin 108a (ft) and ET is greater than zero. In some examples, the distance H2 may be about 3nm to about 10 nm; of course, the present embodiment is not limited to such a size.

Referring to block 230 of fig. 2A and referring to fig. 10A-10D, the method 220 forms a patterned photoresist layer 134 over the workpiece 100 to expose the region 102C and not the regions 102A, 102B, and 102D. Photoresist layer 134 may be a tri-layer photoresist similar to photoresist layer 130, which was discussed in detail above with respect to block 222. The photoresist layer 134 may be patterned by a series of photolithography processes similar to those discussed in detail above with respect to the patterned fin 108.

Referring to block 232 of fig. 2A and referring to fig. 11A-11D, the method 220 recesses the dielectric layer 216 to form the FSW spacer 126B. In the present embodiment, referring to fig. 11B, the method 220 performs an etching process 308 to remove the portion of the dielectric layer 126 located in the region 102C. In the present embodiment, the etch process 308 includes one or more etch processes configured to anisotropically recess portions of the dielectric layer 126, leaving portions of the dielectric layer 126 as FSW spacers 126B on the sidewalls of the fin 108C and as gate spacers 124 on the sidewalls of the dummy gate stack 114. In the present embodiment, the FSW spacer 126B is defined by a height H3, which is measured from the top surface of the isolation member 104, H3. Etch process 308 may implement one or more dry etch processes similar to or the same as those discussed above with respect to etch process 302, and may utilize the same dry etchant as etch process 302; however, the parameters of the etch process 308 are adjusted in a different manner than the parameters of the etch process 302, so that subsequently formed source/drain features in the region 102C are different in configuration from those in the region 102A.

Specifically, in the present embodiment, still referring to fig. 11B, instead of adjusting the bias power, the etch process 308 is adjusted by adjusting the frequency of the power output (a process referred to as a "sync pulse") to intermittently apply the dry etchant (discussed above with respect to the etch process 302). In other words, the etch process 308 repeats "on" (i.e., when a dry etchant (or pulse) is applied) and "off" (i.e., when no dry etchant is applied) at a specified frequency to allow for the alternation between material removal and redeposition. When the etch process 308 is "on," portions of the dielectric layer 126 are removed by chemical reaction with a dry etchant and/or particle bombardment, thereby reducing the height H3. Conversely, when the etch process 308 is "off," etch byproducts (such as a carbon-like polymer material) are redeposited on the surface of the workpiece 100 including, for example, the FSW spacers 126B and the gate spacers 124, thereby increasing the height H3 of the FSW spacers 126B and/or smoothing the surface profile. Accordingly, the height H3 may be fine tuned by adjusting the duration and/or frequency of the on/off pulses implemented during the etch process 308. For example, if the duration of the "on" state is longer than the duration of the "off state, the height H3 may be lower for a given amount of etching time than if the duration of the" off state is longer than the duration of the "on". In addition, the height H3 may be adjusted by adjusting the number of on/off cycles. For example, increasing the number of cycles decreases height H3. In addition, other factors, such as the type of dry etchant and the concentration of the dry etchant, may also be independently controlled during the synchronized pulsing process to achieve the desired FSW spacer height and morphology. For example, by adjusting the duration and/or frequency of the synchronization pulses, the top surface of the resulting FSW spacer 126B can be adjusted to have a relatively flat rather than circular profile. Furthermore, any unintentional thinning or shortening of the gate spacers 124 exposed in the third region 108C may be remedied by redeposition of etch byproducts during the "off" state of the etch process 308. In other words, due to the lack of etch/redeposition cycles during the etch process 302, the height of the gate spacers 124 formed in the region 102C may be greater than the height of the gate spacers 124 formed in the region 102A.

In the present embodiment, the height H3 is formed to be greater than the height H1, making the resulting source/drain features formed between FSW spacers 126B different in shape and size from those formed between FSW spacers 126A. In some embodiments, the height H3 is controlled such that the resulting source/drain features are formed over different fins 108C and are each smaller in size than the merged source/drain features 132 formed between the FSW spacers 126A, as discussed above. In this regard, height H3 may be at least about half of the previously defined fin height FH. In some embodiments, the ratio of height H3 to FH is about 0.5 to about 0.7. In some examples, height H3 may be about 29nm to about 37 nm. Although the present embodiment is not limited by such dimensions, it should be noted that if the ratio of the height H3 to FH is less than about 0.5, subsequently formed source/drain features above two adjacent fins 108C may merge to form a single source/drain feature. On the other hand, if the ratio of height H3 to FH is greater than about 0.7, the resulting source/drain features (although not incorporated) may introduce higher contact resistance due to their smaller size.

Referring to block 234 of fig. 2A and to fig. 12A-12D, the method 220 forms source/drain recesses 135 in each exposed fin 108C and between FSW spacers 126B. In the present embodiment, forming source/drain recesses 135 includes applying an etch process 310, the etch process 310 selectively removing portions of fin 108C without removing or substantially removing portions of dummy gate stack 114, isolation feature 104, or dielectric layer 126. The details of the etch process 310 may be similar to those of the etch process 304 discussed above. In some embodiments, the etch process 310 is followed by a wet clean process, also similar to that discussed above with respect to the etch process 304. The source/drain recesses 135 may be formed to a depth D2. In some embodiments, depth D2 is less than depth D1, such that the bottom surface of source/drain recesses 135 is above the bottom surface of source/drain recesses 131, as depicted in fig. 12B. In some examples, the ratio of height H3 to depth D2 may be about 0.6 to about 1.0, and depth D2 may be about 35nm to about 45 nm; of course, the present embodiment is not limited to such a size.

Referring to block 236 of fig. 2A and referring to fig. 13A-13D, the method 220 forms source/drain features 136 in the source/drain recesses 135. In the present embodiment, the method 220 performs an epitaxial process 312 to grow the source/drain features 136. The epitaxial process 312 may be similar to the epitaxial process 306 discussed in detail above. For example, the epitaxial process 312 may perform a suitable SEG process to form one or more epitaxial layers in the source/drain recesses 135, wherein the epitaxial layers are doped with a suitable dopant in situ or subsequently during the implantation process. As discussed above with respect to the source/drain features 132, the dopant for the source/drain features 136 is selected based on the type of device that the source/drain features 136 are configured to provide. For embodiments in which the source/drain features 136 are configured to provide an n-type device, the source/drain features 136 comprise one or more epitaxial Si layers doped with an n-type dopant, and for embodiments in which the source/drain features 136 are configured to provide a p-type device, the source/drain features 136 comprise one or more epitaxial SiGe layers doped with a p-type dopant. In some embodiments, the source/drain features 132 and the source/drain features 136 are configured to provide devices of the same conductivity type (e.g., both n-type or both p-type); optionally, the source/drain features 132 and the source/drain features 136 are configured to provide devices of different conductivity types (e.g., n-type and p-type, respectively). The epitaxial process 312 may also include performing a suitable annealing process similar to that discussed above to activate dopants in the source/drain features 136. In the present embodiment, because the depth D2 is less than the depth D1, as discussed above, the bottom surface of the source/drain feature 136 is above the bottom surface of the source/drain feature 132. After the source/drain features 136 are formed, the patterned photoresist layer 134 is removed by a suitable process, such as plasma ashing and/or resist stripping.

In the present embodiment, referring to fig. 13C, an epitaxial process 312 forms source/drain features 136 from each of the source/drain recesses 135 such that the resulting source/drain features 136 are spaced apart from one another rather than merged with one another. In this embodiment, adjusting the height H3 of the FSW spacers 126B to be greater than the height H1 of the FSW spacers 126A allows the epitaxial layers of the source/drain features 136 to grow in a substantially vertical direction between the FSW spacers 126B. In some embodiments, height H3 is adjusted to be at least half FH. Thus, the size of the source/drain features 136 is smaller than the size of the source/drain features 132. For example, in some embodiments, the maximum width W2 of the source/drain feature 136 is much less than FH, and the distance H4 between the top surface FT of the fin 108C and the top surface ET of the source/drain feature 136 is less than the distance H2 of the source/drain feature 132. In some cases, the ratio of width W2 to FH may be about 0.3 to about 0.5, where width W2 may be about 18nm to about 28 nm. In some embodiments, distance H4 is less than zero, such as about-2 nm to about 0nm, indicating that the ET is disposed below or at the same level as FT. In some embodiments, as depicted herein, distance H4 is greater than zero, such as about 0nm to about 3nm, indicating that the ET is disposed above the FT. Of course, the present embodiment is not limited to these dimensions. The reduced volume of the source/drain features 136 also results in the ET of the source/drain features 136 being elongated much less than the ET of the source/drain features 132, i.e., the distance W2 'is less than the distance W1', as discussed above.

In addition to the height of the FSW spacers (such as height H3), the size and shape of the source/drain features 136 may depend on factors such as the composition of the epitaxial layer, the separation distance S2 between the fins 108C, and/or the deposition conditions of the epitaxial process 312.

Referring now collectively to blocks 238-250 of fig. 2B and to fig. 14A-14D, method 220 forms source/drain features 142 in region 102B and source/drain features 146 in region 102D. In the depicted embodiment, region 102B is configured to provide the same functionality but different conductivity type devices as region 102A, and region 102D is configured to provide the same functionality but different conductivity type devices as region 102C. For example, in the depicted embodiment, region 102A and region 102B are configured to provide p-type and n-type logic devices, respectively, while region 102C and region 102D are configured to provide p-type and n-type SRAM devices, respectively.

In the present embodiment, blocks 238 through 250 depict a series of photolithography, etching, and epitaxy processes substantially similar to those discussed in blocks 222 through 236. For example, referring to block 238, the method 220 forms a third patterned photoresist layer (not depicted) over the workpiece 100 to expose the region 102B covered by the dielectric layer 126, without exposing the regions 102A, 102C, or 102D. The third patterned photoresist layer may be substantially similar to the patterned photoresist layer 130 as discussed above. Referring to block 240, and the method 220 performs an etch process substantially similar or identical to the etch process 302, forming gate spacers 124 on sidewalls of the dummy gate stack 112 and forming FSW spacers 126C on sidewalls of the fin 108B, as depicted in fig. 14B and 14C. In the present embodiment, FSW spacer 126C is formed to a height H5 that is less than FH by adjusting the bias power when etching dielectric layer 126. In some exemplary embodiments, height H5 is less than half FH, wherein the ratio of height H3 to FH is about 0.1 to about 0.3. Although the present embodiment does not limit the height H5 to a particular dimension, the etching process applied in block 240 is adjusted such that the resulting source/drain features formed between the FSW spacers 126C merge two adjacent fins 108B together. In some embodiments, the height H5 is substantially similar to the height H1 of the FSW spacer 126A, and thus is less than the height H3 of the FSW spacer 126B. In some examples, height H5 may be less than height H1 such that the merged source/drain feature formed therebetween is larger than merged source/drain feature 132. If height H5 is less than height H1, a greater etch bias power (higher voltage) may be applied in the etch process to form FSW spacers 126C when compared to etch process 302.

Referring to block 242, the method 220 forms source/drain recesses (not depicted) in portions of the second fin 108B between the FSW spacers 126C in an etch process similar to the etch process 304. Subsequently, referring to block 244 and referring to fig. 14B and 14C, the method 220 forms the source/drain features 142 in the source/drain recesses in an epitaxial growth process similar to the epitaxial process 306, during which the source/drain features 142 merge the two recessed fins 108B together, forming the air gaps 144 with the FSW spacers 126C. Source/drain features 142 may be configured to have a conductivity type different from the conductivity type of source/drain features 132. For embodiments in which source/drain components 132 are configured to provide a p-type device (such as a p-type logic device), source/drain components 142 are configured to provide an n-type device (such as an n-type logic device). In this regard, the source/drain features 142 may include one or more epitaxial Si layers doped with an n-type dopant (such as Si: P layers), as discussed above with respect to the source/drain features 132. An annealing process may be performed after forming the source/drain features 142 to activate dopants in the source/drain features 142. After forming the source/drain features 142, the method 220 removes the third patterned photoresist layer configured to expose the regions 102B by any suitable method described above.

Source/drain features 142 may be configured to have a geometry substantially similar to source/drain features 132, but the specific dimensions of source/drain features 142 may be different than those of source/drain features 132. For example, the merged source/drain feature 142 may be formed with a maximum width W4 of about 65nm to about 75nm, and the ratio of the width W4 to FH may be about 1.2 to about 1.4. In a further example, the top surface ET may be substantially elongated to a width W4 'similar to the width W1', and the distance H6 between the top surface FT and ET of the fin 108B is greater than zero and may be, for example, from about 3nm to about 10 nm. Of course, the present embodiment is not limited to such a size. In some embodiments, FSW spacer 126C is adjusted to be smaller than FSW spacer 126A, such that consolidated source/drain feature 142 is larger than consolidated source/drain feature 132.

Referring to block 246, the method 220 forms a fourth patterned photoresist layer (not depicted) over the workpiece 100 to expose the region 102D covered by the dielectric layer 126 and not to expose the regions 102A-102C. The fourth patterned photoresist layer may be substantially similar to the patterned photoresist layer 130 as discussed above. Referring to block 248, the method 220 performs an etch process substantially similar to the etch process 308, forming gate spacers 124 on sidewalls of the dummy gate stack 114 and forming FSW spacers 126D on sidewalls of the fin 108D, as depicted in fig. 14B and 14D. In the present embodiment, the etchant (such as the dry etchant discussed above with respect to etch process 308) is applied intermittently, i.e., alternating between an "on" state and an "off" state, by adjusting the synchronization pulses of the etch process applied in block 248. As discussed in detail above, the "on" state of the synchronization pulse actively recesses the dielectric layer 126 to form FSW spacers 126D and gate spacers 124, while the "off state allows any etch byproducts to redeposit above the workpiece 100, thereby providing control to fine tune the height H7 and smooth the recessed profile of the FSW spacers 126D. In this regard, the removal rate of the dielectric layer 126 may be adjusted by adjusting the frequency of the "on" and "off state cycles and/or the duration of time each state is applied. In some cases, unintentional recessing of the gate spacers 124 may be mitigated by such an adjustment process.

In the present embodiment, height H7 is adjusted in block 248 so that the resulting source/drain features formed between FSW spacers 126D are spaced apart from one another rather than merging with one another as is the case with source/drain features 142. In this regard, the height H7 is greater than the height H5 of FSW spacer 126C and the height H1 of FSW spacer 126A. In some embodiments, height H7 is at least about half of FH, and in some cases, the ratio of height H7 to FH may be about 0.5 to about 0.7, similar to height H3 as discussed above. In some examples, height H7 may be similar to height H3 of FSW spacer 126B.

Referring to block 250, the method 220 forms source/drain recesses (not depicted) in portions of the fin 108B located between the FSW spacers 126D in an etch process similar to the etch process 310 as discussed above. Subsequently, referring to block 252 and to fig. 14B and 14D, the method 220 implements an epitaxial growth process similar to the epitaxial growth process 312 as discussed above, such that the resulting source/drain features 146 are grown from each of the source/drain recesses formed in block 250, respectively. The source/drain features 146 may be configured to have a conductivity type different from the conductivity type of the source/drain features 136. For embodiments in which source/drain components 136 are configured to provide a p-type device (such as a p-type memory device), source/drain components 146 are configured to provide an n-type device (such as an n-type memory device). In this regard, the source/drain features 146 may include one or more epitaxial Si layers doped with an n-type dopant (such as Si: P layers), as discussed above with respect to the source/drain features 132. An annealing process may be performed after forming the source/drain features 142 to activate dopants in the source/drain features 142. After forming the source/drain features 142, the method 220 removes the third patterned photoresist layer configured to expose the regions 102B by any suitable method described above.

In this embodiment, adjusting the height H7 of the FSW spacers 126D to be greater than the height H5 of the FSW spacers 126C allows the epitaxial layers of the source/drain features 146 to grow substantially in the vertical direction between the FSW spacers 126D. In other words, increasing height H7 relative to height H5 reduces the overall size of source/drain feature 146 when compared to source/drain feature 142. For example, in some embodiments, the maximum width W5 of the source/drain feature 146 is much less than FH, and the distance H8 between the fin top surface FT and the top surface ET of the source/drain feature 146 is less than the distance H6 of the source/drain feature 142. In some examples, the ratio of width W5 to FH may be about 0.3 to about 0.5. In some embodiments, similar to the description of distance H4 above, distance H8 is less than zero, such as about-2 nm to about 0nm, indicating that the ET is disposed below the FT. In some embodiments, distance H8 is greater than zero, such as about 0nm to about 3nm, indicating that the ET is disposed above the FT. Furthermore, due to height H7, the reduced size of source/drain feature 146 results in the elongation of the ET defined by width W5 'being less than width W4' of source/drain feature 142. Further, the differences in size and shape between source/drain features 142 and source/drain features 146 may depend on factors such as the composition of the epitaxial layer, the separation distance between the fins (such as distances S3 and S4), and/or the deposition conditions of the epitaxial process.

In the depicted embodiment, although source/drain features 132 and source/drain features 142 are formed in similar sizes and geometries, and source/drain features 136 and source/drain features 146 are formed in similar sizes and geometries, the present embodiment is not limited to these configurations. For example, the present invention is also applicable to source/drain features 142 formed as separate rather than merged features by performing an etch process similar to etch process 308 rather than etch process 302. Similarly, by performing an etch process similar to etch process 302 rather than etch process 308, source/drain features 146 may be formed as merged rather than separate features. In other words, because the four regions 102A-102D are independently and separately processed, the methods provided herein allow various shapes and sizes of source/drain features to be formed in different device regions to meet various design requirements. This advantage may be achieved when existing methods of forming source/drain features in different device regions can no longer be supported with a reduced length scale.

Referring now back to block 212 of fig. 1 and to fig. 15A-15G, method 200 continues with replacing dummy gate stacks 112 and 114 with metal gate stacks 152 and 154, respectively. In the present embodiment, the metal gate stack 152 is joined with a portion of the fin 108A to form a first FET, such as a first p-type FET, and with a portion of the fin 108B to form a second FET, such as a first n-type FET, of a different conductivity type than the first FET. Similarly, the metal gate stack 154 is joined with a portion of the fin 108C to form a third FET, such as a second p-type FET, and with a portion of the fin 108D to form a fourth FET, such as a second n-type FET, of a different conductivity type than the third FET. Further, in the present embodiment, the first FET (or the second FET) and the third FET (or the fourth FET) are configured to implement different functions. For example, the first FET (or second FET) may be configured as a logic device and the third FET (or fourth FET) may be configured as a memory device. The formation of metal gate stacks 152 and 154 is described in detail below.

The method 220 may first deposit an interlayer dielectric (ILD) layer 150 over the workpiece 100 including the source/drain features 132, 136, 142 and 146. The ILD layer 150 serves as an insulator to support and isolate conductive traces formed over the workpiece 100. ILD layer 150 may comprise any suitable dielectric material, such as silicon oxide, doped silicon oxides, such as borophosphosilicate glass (BPSG), Tetraethylorthosilicate (TEOS), undoped silicate glass, Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. ILD layer 150 may be deposited by any suitable method, such as plasma enhanced cvd (pecvd), FCVD, SOG, other suitable deposition processes, or combinations thereof. A CMP process may then be performed to remove any excess dielectric material and planarize the top surface of the workpiece 100. Alternatively, the hard mask 120 may be used as a polish stop layer during a CMP process and removed by an additional etching process after CMP is performed.

Subsequently, method 220 removes dummy gate stacks 112 and 114, or portions thereof, respectively or collectively, by a suitable selective etch process. The selective etch process is configured to remove dummy gate material, such as polysilicon, relative to ILD layer 150, resulting in gate trenches (not depicted). The selective etching process may include any suitable etching technique, such as wet etching, dry etching, RIE, ashing, other etching methods, or combinations thereof. In one example, the selective etching process is a dry etching process utilizing a fluorine-based etchant. In some embodiments, the selective etch process includes multiple etch steps with different etch chemistries, each for a particular material of the dummy gate layer.

Thereafter, the method 220 fills the gate trench with various gate materials, such as a gate dielectric layer (not separately depicted) and a gate electrode (not separately depicted), each including one or more material layers. The gate dielectric layer may comprise a high-k dielectric material such as a metal oxide (e.g., LaO, AlO, ZrO, TiO, Ta)₂O₅、Y₂O₃、SrTiO₃(STO)、BaTiO₃(BTO)、BaZrO、HfZrO、HfLaO、HfTaO、HfTiO、(Ba,Sr)TiO₃(BST)、Al₂O₃Etc.), metal silicates (e.g., HfSiO, LaSiO, AlSiO, etc.), other suitable materials, or combinations thereof. In some embodiments, the gate dielectric layer is deposited in the gate trench by any suitable method, such as ALD, CVD, metal organic CVD (mocvd), PVD, other suitable methods, or combinations thereof. Subsequently, the method 220 forms a gate electrode over the gate dielectric layer, wherein the gate electrode may include one or more work function metal layers and a metal fill layer over the work function metal layers. The work function metal layer may comprise a p-type work function metal layer or an n-type work function metal layer. Exemplary work function metal layers include TiN, TaN, Ru, Mo, Al, WN, ZrSi₂、MoSi₂、TaSi₂、NiSi₂Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The work function metal layer may be deposited by CVD, PVD, other suitable process, or combinations thereof. The metal fill layer may include aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), other suitable materials, or combinations thereof. The metal fill layer may be formed by CVD, PVD, plating, other suitable process, or combinations thereof. In some embodiments, method 220 forms other material layers, such as interfacial layers, barrier layers, capping layers, and/or other suitable layers, as part of metal gate stacks 152 and/or 154. After the deposition of the metal gate material, one or more CMP processes are performed to produce substantially planar top surfaces of metal gate stacks 152 and 154.

Referring to block 214 of FIG. 1, the method 200 implements additional processing steps. For example, the method 200 may form source/drain contacts in an ILD layer disposed above the workpiece 100, wherein the source/drain contacts are configured to electrically couple with the source/drain features 132, 136, 142, and 146. Thereafter, the method 200 may continue with forming interconnect structures to couple the various devices of the workpiece 100 to the ICs. The interconnect structure includes metal lines in multiple metal layers for horizontal coupling and vias/contacts for vertical coupling between adjacent metal layers or between a bottom metal layer and device features on the substrate 102, such as source/drain features and metal gate stacks. The source/drain contacts and interconnect structures may comprise one or more suitable conductive materials, such as Cu, Al, W, Co, Ru, metal silicides, metal nitrides, or other suitable conductive materials. The source/drain contacts and interconnect structures may be formed by a damascene process, such as a single damascene process or a dual damascene process, which includes lithographic patterning, etching, deposition, and CMP. The workpiece 100 shown is merely an example of some embodiments of the methods 200 and 220. Methods 200 and 220 may have various other embodiments without departing from the scope of the present invention.

The invention provides a semiconductor structure and a manufacturing method thereof. The method includes different procedures for forming epitaxially grown source/drain features for each device. Although not intended to be limiting, one or more embodiments of the present invention provide many benefits to semiconductor devices including finfets and the formation thereof. For example, in the present embodiment, at least two types of finfets are formed by different procedures. The first type may be a logic device and the second type may be a memory (such as SRAM) device. In particular, in the present embodiment, the first type and second type source/drain features are formed by adjusting the heights of their respective FSW spacers in different photolithography and etching processes, and then performing an epitaxial growth process between the different heights of the respective FSW spacers to form differently configured source/drain features. Thus, by adjusting the height of the FSW spacers separately for different finfets, different sizes and geometries of source/drain features may be achieved to achieve various advantages, such as reduced contact resistance, increased contact area with the source/drain contacts, enhanced charge mobility due to strain effects on the channel region, and/or other advantages. Furthermore, the present invention provides design freedom to handle different finfets differently and independently to meet their respective design specifications. However, it is noted that the first type of FinFET and the second type of FinFET are not limited to logic devices and memory devices, respectively, and may be other types of devices having different specifications. For example, the first type of FinFET may be a p-type device and the second type of device may be an n-type FinFET, or vice versa, depending on various design considerations.

In one aspect, the present invention provides a method comprising: forming a first semiconductor fin in a first device region and a second semiconductor fin in a second device region over a substrate; forming a spacer layer over the substrate, wherein a first portion of the spacer layer is formed over the first semiconductor fin and a second portion of the spacer layer is formed over the second semiconductor fin; performing a first etch process to recess a first portion of the spacer layer relative to a second portion of the spacer layer to form first fin spacers on sidewalls of the first semiconductor fin; forming first epitaxial S/D features between the first fin spacers; subsequently performing a second etching process to recess a second portion of the spacer layer relative to the first portion of the spacer layer to form a second fin spacer on sidewalls of the second semiconductor fin, wherein the second fin spacer is formed to a height greater than a height of the first fin spacer; and forming second epitaxial S/D features between the second fin spacers, wherein the second epitaxial S/D features are formed to a size smaller than a size of the first epitaxial S/D features.

In another aspect, the present invention provides a method comprising: forming a first fin and a second fin protruding from a first region of a semiconductor substrate; forming a third fin protruding from the second region of the semiconductor substrate; forming a first dummy gate stack over the first fin and the second fin and a second dummy gate stack over the third fin; depositing a dielectric layer over the first and second dummy gate stacks; forming a first source/drain (S/D) feature over the first fin and the second fin, wherein the first S/D feature merges the first fin and the second fin; forming a second S/D feature over the third fin; and replacing the first and second dummy gate stacks with metal gate stacks. In this embodiment, forming the first S/D section includes: performing a first etch process to remove portions of the dielectric layer on sidewalls of the first fin and the second fin, thereby forming first Fin Sidewall (FSW) spacers having a first height; recessing the first fin and the second fin; and performing a first epitaxial process to grow the first S/D feature to merge the recessed first and second fins. In this embodiment, forming the second S/D section includes: performing a second etch process to remove portions of the dielectric layer on the sidewalls of the third fin to form a second FSW spacer having a second height, wherein the second height is greater than the first height, and wherein the first etch process and the second etch process perform the same etchant; recessing the third fin; and performing a second epitaxy process to grow a second S/D component between the second FSW spacers.

In yet another aspect, the present invention provides a semiconductor structure comprising: a first fin and a second fin extending from the semiconductor substrate; an isolation feature disposed over the semiconductor substrate to separate the first fin and the second fin, wherein the first fin and the second fin have a fin height measured from a top surface of the isolation feature; a first device over the first fin; a second device over the second fin; and an interlayer dielectric (ILD) layer over the first device and the second device. In this embodiment, the first device includes: a first gate stack coupled to the first channel region of the first fin; first epitaxial source/drain (S/D) features disposed on opposite sides of the first channel region, wherein the first epitaxial S/D features merge the first fins together; and a first fin spacer disposed on a sidewall of the first epitaxial S/D feature, wherein the first fin spacer has a first height measured from a top surface of the isolation feature. In this embodiment, the second device includes: a second gate stack coupled to the second channel region of the second fin; a second epitaxial S/D feature disposed on an opposite side of the second channel region, and a second fin spacer disposed on a sidewall of the second epitaxial S/D feature, wherein the second fin spacer has a second height measured from a top surface of the isolation feature that is greater than the first height.

Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a substrate having a first device region and a second device region; forming a first semiconductor fin in the first device region and a second semiconductor fin in the second device region; forming a spacer layer over the substrate, wherein a first portion of the spacer layer is formed over the first semiconductor fin and a second portion of the spacer layer is formed over the second semiconductor fin; performing a first etch process to recess the first portion of the spacer layer relative to the second portion of the spacer layer to form first fin spacers on sidewalls of the first semiconductor fin; etching the first semiconductor fin to form first source/drain (S/D) recesses between the first fin spacers; forming a first epitaxial source/drain feature in the first source/drain recess; after forming the first epitaxial source/drain features, performing a second etch process to recess the second portion of the spacer layer relative to the first portion of the spacer layer to form second fin spacers on sidewalls of the second semiconductor fin, wherein the second fin spacers are formed to a height greater than a height of the first fin spacers; etching the second semiconductor fin to form second source/drain recesses between the second fin spacers; and forming a second epitaxial source/drain feature in the second source/drain recess, wherein the second epitaxial source/drain feature is formed to a size smaller than a size of the first epitaxial source/drain feature.

In some embodiments, the first semiconductor fin is configured to provide a logic device, and wherein the second semiconductor fin is configured to provide a memory device. In some embodiments, etching the first portion of the spacer layer comprises: forming a patterned photoresist layer to expose the first portion of the spacer layer but not the second portion of the spacer layer; performing the first etching process; and removing the patterned photoresist layer from the substrate after forming the first epitaxial source/drain features and before performing the second etching process. In some embodiments, the patterned photoresist layer is a first patterned photoresist layer, and wherein etching the second portion of the spacer layer comprises: forming a second patterned photoresist layer to expose the second portion of the spacer layer but not the first portion of the spacer layer; performing the second etching process; and removing the second patterned photoresist layer after forming the second epitaxial source/drain features. In some embodiments, performing the first etch process includes adjusting a bias power of the first etch process. In some embodiments, performing the second etching process includes intermittently applying an etchant. In some embodiments, intermittently applying the etchant includes cyclically recessing the second portion of the spacer layer and redepositing etch byproducts above the second semiconductor fin. In some embodiments, the first and second semiconductor fins are configured to form devices of the same conductivity type. In some embodiments, the first and second semiconductor fins are configured to form devices of different conductivity types.

Other embodiments of the present application provide a method of forming a semiconductor structure, comprising: forming a first fin and a second fin protruding from a first region of a semiconductor substrate; forming a third fin protruding from a second region of the semiconductor substrate; forming a first dummy gate stack over the first fin and the second fin and a second dummy gate stack over the third fin; depositing a dielectric layer over the first and second dummy gate stacks; forming a first source/drain (S/D) feature over the first fin and the second fin, comprising: performing a first etch process to remove portions of the dielectric layer on sidewalls of the first and second fins to form first Fin Sidewall (FSW) spacers having a first height, recessing the first and second fins, and performing a first epitaxial process to grow the first source/drain features to merge the recessed first and second fins; forming a second source/drain feature over the third fin, comprising: after forming the first source/drain features, performing a second etch process to remove portions of the dielectric layer on sidewalls of the third fin to form second fin sidewall spacers having a second height, wherein the second height is greater than the first height, and wherein the first etch process and the second etch process perform the same etchant, recess the third fin, and perform a second epitaxial process to grow the second source/drain features between the second fin sidewall spacers; and replacing the first and second dummy gate stacks with metal gate stacks.

In some embodiments, the first region and the second region provide devices of different functions, different conductivity types, or a combination thereof. In some embodiments, the first region and the second region provide different functions but devices of the same conductivity type. In some embodiments, the first fin, the second fin, and the third fin are formed to a fin height, and wherein the first height is formed to be less than half the fin height and the second height is formed to be at least half the fin height. In some embodiments, performing the first and second etch processes forms first and second gate spacers on sidewalls of the first and second dummy gate stacks, respectively. In some embodiments, the second gate spacer has a height greater than the first gate spacer.

Still other embodiments of the present application provide a semiconductor structure comprising: a first fin and a second fin extending from the semiconductor substrate; an isolation feature disposed over the semiconductor substrate to separate the first fin and the second fin, wherein the first fin and the second fin have a fin height measured from a top surface of the isolation feature; a first device over the first fin, the first device comprising: a first gate stack engaged with a first channel region of the first fin, a first epitaxial source/drain (S/D) feature disposed on opposite sides of the first channel region, wherein the first epitaxial source/drain feature merges the first fins together, and a first fin spacer disposed on a sidewall of the first epitaxial source/drain feature, wherein the first fin spacer has a first height measured from the top surface of the isolation feature; a second device over the second fin, the second device comprising: a second gate stack engaged with a second channel region of the second fin, a second epitaxial source/drain feature disposed on an opposite side of the second channel region, and a second fin spacer disposed on a sidewall of the second epitaxial source/drain feature, wherein the second fin spacer has a second height measured from the top surface of the isolation feature that is greater than the first height; and an interlayer dielectric (ILD) layer over the first device and the second device, wherein the ILD layer separates the second epitaxial source/drain features.

In some embodiments, the first device is a logic device and the second device is a memory device. In some embodiments, a top surface of the first epitaxial source/drain feature is above a top surface of the first fin. In some embodiments, a bottom surface of the first epitaxial source/drain feature is below a bottom surface of the second epitaxial source/drain feature. In some embodiments, a width of the first epitaxial source/drain feature is greater than the fin height.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.