阅读说明：本技术 鳍式半导体器件的制备方法 (Preparation method of fin type semiconductor device ) 是由 耿金鹏 刘洋 杨渝书 于 2021-09-07 设计创作，主要内容包括：本发明提供了一种鳍式半导体器件的制备方法,包括：提供基底,所述基底包括PMOS区域和NMOS区域；刻蚀以去除所述PMOS区域的基底的部分厚度；在所述PMOS区域和所述NMOS区域的所述基底上保形地形成鳍片材料层；在所述鳍片材料层上依次保形地形成第一掩模层和第二掩模层；研磨以去除部分厚度的所述第二掩模层；刻蚀以去除所述第一掩模层、所述第二掩模层、所述NMOS区域的鳍片材料层及所述PMOS区域的部分厚度的鳍片材料层；在所述NMOS区域形成所述NMOS管的鳍片及在所述PMOS区域形成所述PMOS管的鳍片；本发明减小了NMOS管的鳍片与PMOS管的鳍片的高度差。(The invention provides a fin type semiconductor device preparation method, which comprises the following steps: providing a substrate, wherein the substrate comprises a PMOS area and an NMOS area; etching to remove part of the thickness of the substrate of the PMOS region; conformally forming a fin material layer on the substrate in the PMOS region and the NMOS region; sequentially and conformally forming a first mask layer and a second mask layer on the fin material layer; grinding to remove a portion of the thickness of the second mask layer; etching to remove the first mask layer, the second mask layer, the fin material layer of the NMOS region and the fin material layer of the PMOS region with partial thickness; forming a fin of the NMOS tube in the NMOS area and forming a fin of the PMOS tube in the PMOS area; the invention reduces the height difference between the fins of the NMOS tube and the fins of the PMOS tube.)

1. A method for manufacturing a fin type semiconductor device is characterized by comprising the following steps:

providing a substrate, wherein the substrate comprises a PMOS region and an NMOS region, the PMOS region is used for forming a PMOS tube, and the NMOS region is used for forming an NMOS tube;

etching to remove part of the thickness of the substrate of the PMOS region;

conformally forming a fin material layer on the substrate in the PMOS region and the NMOS region;

sequentially and conformally forming a first mask layer and a second mask layer on the fin material layer;

grinding to remove part of the thickness of the second mask layer by taking the first mask layer as a grinding stop layer;

etching to remove the first mask layer, the second mask layer, the fin material layer of the NMOS region and the fin material layer of the PMOS region with partial thickness, so that the top surface of the substrate of the NMOS region is flush with the top surface of the fin material layer of the PMOS region, and the rate of etching the first mask layer, the rate of etching the second mask layer and the rate of etching the fin material layer are equal; and the number of the first and second groups,

and etching the substrate of the NMOS region and the fin material layer of the PMOS region to form fins of the NMOS tube in the NMOS region and fins of the PMOS tube in the PMOS region.

2. The method of claim 1, wherein the substrate comprises silicon; and/or the material of the fin material layer comprises silicon germanium.

3. The method of claim 2, wherein when the first mask layer, the second mask layer, the fin material layer of the NMOS region, and the fin material layer of the PMOS region are removed by etching using a dry etching process, an etching gas of the dry etching process comprises CF₄And CHF₃Said CF₄And the CHF₃The flow ratio of (A) to (B) is 5: 1-10: 1.

4. The method of claim 1, wherein the substrate etched to remove the PMOS region has a thickness of

5. The method of claim 1, wherein after conformally forming the fin material layer over the substrate in the PMOS region and the NMOS region, a top surface of the fin material layer in the PMOS region is higher than a top surface of the substrate in the NMOS region

6. The method of claim 1, wherein the first mask layer has a thickness of about one square inch and the second mask layer is conformally formed on the fin material layerThe second mask layer has a thickness of

7. The method of claim 6, wherein the first mask layer comprises silicon nitride and the second mask layer comprises silicon oxide.

8. The method of claim 1, wherein an oxide layer is formed on the substrate before etching to remove a portion of the thickness of the substrate in the PMOS region; and after etching to remove part of the thickness of the substrate in the PMOS region, removing the oxide layer and cleaning the surface of the substrate.

9. The method of claim 8, wherein the oxide layer has a thickness of

10. The method of claim 1, wherein the etching is performed to remove a portion of the thickness of the substrate of the NMOS region while the etching is performed to remove the first mask layer, the second mask layer, the fin material layer of the NMOS region, and the fin material layer of the PMOS region, and the etching is performed to remove the substrate of the NMOS region to a thickness of

Technical Field

The invention relates to the technical field of semiconductors, in particular to a fin type semiconductor device manufacturing method.

Background

A Fin Field effect transistor (FinFET) is a complementary metal oxide semiconductor Field effect transistor, and includes a vertical channel structure, also called a Fin, where two sides of the Fin are surrounded by a gate structure, and the FinFET structure makes the device smaller and has higher performance, and the FinFET is widely used in the Field of memory and logic devices. With the continuous reduction of the size of a device, in order to improve the carrier mobility in a fin field effect transistor and improve the performance of the transistor, a PMOS transistor in a general fin field effect transistor adopts germanium-silicon to form a fin to improve the carrier mobility of the PMOS transistor, an NMOS transistor still adopts silicon to form a fin, the silicon and the germanium-silicon are located in different regions, if chemical mechanical polishing is directly adopted to planarize the surfaces of the silicon and the germanium-silicon, the surfaces of the silicon and the germanium-silicon are easily damaged, and the planarity of the germanium-silicon and the silicon surface is poor, and the poor planarity causes the difference between the heights of the fin of the PMOS transistor and the fin of the NMOS transistor, thereby affecting the working speed of the device.

Disclosure of Invention

The invention aims to provide a fin type semiconductor device manufacturing method, which is used for reducing the height difference between an NMOS tube fin and a PMOS tube fin.

In order to achieve the above object, the present invention provides a method for manufacturing a fin-type semiconductor device, including:

providing a substrate, wherein the substrate comprises a PMOS region and an NMOS region, the PMOS region is used for forming a PMOS tube, and the NMOS region is used for forming an NMOS tube;

etching to remove part of the thickness of the substrate of the PMOS region;

conformally forming a fin material layer on the substrate in the PMOS region and the NMOS region;

sequentially and conformally forming a first mask layer and a second mask layer on the fin material layer;

grinding to remove part of the thickness of the second mask layer by taking the first mask layer as a grinding stop layer; and the number of the first and second groups,

etching to remove the first mask layer, the second mask layer, the fin material layer of the NMOS region and the fin material layer of the PMOS region with partial thickness, so that the top surface of the substrate of the NMOS region is flush with the top surface of the fin material layer of the PMOS region, and the rate of etching the first mask layer, the rate of etching the second mask layer and the rate of etching the fin material layer are equal; and the number of the first and second groups,

and etching the substrate of the NMOS region and the fin material layer of the PMOS region to form fins of the NMOS tube in the NMOS region and fins of the PMOS tube in the PMOS region.

Optionally, the material of the substrate includes silicon; and/or the material of the fin material layer comprises silicon germanium.

Optionally, when the first mask layer, the second mask layer, and the fin material layer in the NMOS region are removed by etching using a dry etching process to remove the first mask layer, the second mask layer, the fin material layer in the NMOS region, and the fin material layer in the PMOS region with a partial thickness, an etching gas of the dry etching process includes CF₄And CHF₃Said CF₄And the CHF₃The flow ratio of (A) to (B) is 5: 1-10: 1.

Optionally, the thickness of the substrate etched to remove the PMOS region is

Optionally, after conformally forming the fin material layer on the substrate of the PMOS region and the NMOS region, the top surface of the fin material layer of the PMOS region is higher than the top surface of the substrate of the NMOS region

Optionally, when a first mask layer and a second mask layer are sequentially conformally formed on the fin material layer, the thickness of the first mask layer isThe second mask layer has a thickness of

Optionally, the material of the first mask layer includes silicon nitride, and the material of the second mask layer includes silicon oxide.

Optionally, before etching to remove a part of the thickness of the substrate in the PMOS region, forming an oxide layer on the substrate; and after etching to remove part of the thickness of the substrate in the PMOS region, removing the oxide layer and cleaning the surface of the substrate.

Optionally, the thickness of the oxide layer is

Optionally, while etching to remove the first mask layer, the second mask layer, the fin material layer in the NMOS region, and the fin material layer in the PMOS region, etching to remove a portion of the thickness of the substrate in the NMOS region, and etching to remove the thickness of the substrate in the NMOS region is set as

In the fin type semiconductor device manufacturing method provided by the invention, a substrate is provided, wherein the substrate comprises a PMOS region and an NMOS region, the PMOS region is used for forming a PMOS tube, and the NMOS region is used for forming an NMOS tube; etching to remove part of the thickness of the substrate of the PMOS region; then conformally forming a fin material layer on the substrate in the PMOS region and the NMOS region; sequentially and conformally forming a first mask layer and a second mask layer on the fin material layer; furthermore, the first mask layer is used as a grinding stop layer, grinding is carried out to remove the second mask layer with partial thickness, the second mask layer is ground, the phenomenon of poor flatness when different materials are ground simultaneously is reduced, and the flatness of the top surface of the first mask layer and the top surface of the second mask layer is better after grinding; etching to remove the first mask layer, the second mask layer, the fin material layer of the NMOS region and the fin material layer of the PMOS region, so that the top surface of the substrate of the NMOS region is flush with the top surface of the fin material layer of the PMOS region, the etching rate of the first mask layer and the etching rate of the second mask layer are equal to the etching rate of the fin material layer, and the second mask layer, the first mask layer and the fin material layer can be etched in equal proportion, so that the flatness of the top surface of the substrate and the top surface of the fin material layer is better; and etching the substrate of the NMOS region and the fin material layer of the PMOS region to form the fins of the NMOS tube in the NMOS region and the fins of the PMOS tube in the PMOS region.

Drawings

Fig. 1 is a flowchart illustrating a method for fabricating a fin-type semiconductor device according to an embodiment of the present invention;

fig. 2A to 2G are schematic cross-sectional views illustrating corresponding steps of a method for fabricating a fin-type semiconductor device according to an embodiment of the invention;

wherein the reference numerals are:

10-a substrate; 10A-NMOS region; 10B-PMOS region; 20-an oxide layer; 30-a fin material layer; 41-a first mask layer; 42-a second mask layer; 51-a fin of an NMOS tube; 52-the fin of the PMOS transistor.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 is a flowchart of a method for manufacturing a fin-type semiconductor device according to this embodiment. The embodiment provides a method for manufacturing a fin type semiconductor device, so as to reduce the height difference between an NMOS tube fin and a PMOS tube fin. Referring to fig. 1, the method for fabricating the fin-type semiconductor device includes:

step S1: providing a substrate, wherein the substrate comprises a PMOS region and an NMOS region, the PMOS region is used for forming a PMOS tube, and the NMOS region is used for forming an NMOS tube;

step S2: etching to remove part of the thickness of the substrate of the PMOS region;

step S3: conformally forming a fin material layer on the substrate in the PMOS region and the NMOS region;

step S4: sequentially and conformally forming a first mask layer and a second mask layer on the fin material layer;

step S5: grinding to remove part of the thickness of the second mask layer by taking the first mask layer as a grinding stop layer;

step S6: etching to remove the first mask layer, the second mask layer, the fin material layer of the NMOS region and the fin material layer of the PMOS region with partial thickness, so that the top surface of the substrate of the NMOS region is flush with the top surface of the fin material layer of the PMOS region, and the rate of etching the first mask layer, the rate of etching the second mask layer and the rate of etching the fin material layer are equal;

step S7: and etching the substrate of the NMOS region and the fin material layer of the PMOS region to form fins of the NMOS tube in the NMOS region and fins of the PMOS tube in the PMOS region.

Fig. 2A to 2G are schematic cross-sectional views illustrating corresponding steps of a method for fabricating a fin-type semiconductor device according to this embodiment, and the method for fabricating a fin-type semiconductor device according to this embodiment is described in detail with reference to fig. 2A to 2G.

Referring to fig. 2A, step S1 is executed: providing a substrate 10, wherein the substrate 10 comprises a PMOS region 10B and an NMOS region 10A, the PMOS region 10B is used for forming a PMOS tube, and the NMOS region 10A is used for forming an NMOS tube.

Specifically, the material of the substrate 10 is preferably silicon, but is not limited thereto. The substrate 10 includes the PMOS region 10B and the NMOS region 10A, where the PMOS region 10B is used to form a PMOS transistor, and the NMOS region 10A is used to form an NMOS transistor.

Further, an oxide layer 20 is formed on the substrate 10, wherein the oxide layer 20 is used to protect the substrate 10 and prevent the substrate 10 from being damaged by a subsequent process, and in this embodiment, the thickness of the oxide layer 20 may be set asBut is not limited to this thickness range.

Referring to fig. 2B, step S2 is executed: and etching to remove part of the thickness of the substrate 10 in the PMOS region 10B.

Specifically, a photoresist layer (not shown in the figure) is formed on the oxide layer 20, the photoresist layer is patterned through photolithography to obtain a patterned photoresist layer, an opening aligned with the PMOS region 10B of the substrate 10 is formed in the patterned photoresist layer, and the patterned photoresist layer is used as a mask to remove a part of the thickness of the substrate 10 in the PMOS region 10B through etching. In this embodiment, the thickness of the substrate 10 etched to remove the PMOS region 10B may beBut is not limited to this thickness range.

Further, after etching to remove a portion of the thickness of the substrate 10 in the PMOS region 10B, the oxide layer 20 is removed, and the surface of the substrate 10 is cleaned.

Referring to fig. 2C, step S3 is executed: a fin material layer 30 is conformally formed over the substrate 10 in the PMOS region 10B and the NMOS region 10A.

Specifically, the fin material layer 30 is conformally formed on the PMOS region 10B and the substrate 10 of the NMOS region 10A by epitaxial growth, and the top surface of the fin material layer 30 of the PMOS region 10B is higher than the top surface of the substrate 10 of the NMOS region 10A, so as to ensure that after a subsequent etching process, the top surface of the fin material layer 30 of the PMOS region 10B is flush with the top surface of the substrate 10 of the NMOS region 10A and does not affect the height of the substrate 10 of the NMOS region 10A. In this embodiment, conformal representation followsThe fin material layer 30 is formed along the contour of the substrate 10 in the PMOS region 10B and the NMOS region 10A, which may be equivalent to a conformal, conformal shape. In the present embodiment, the material of the fin material layer 30 is preferably silicon germanium, but is not limited thereto, and may also be silicon phosphorus. Since the PMOS transistor is formed in the PMOS region 10B, and the mobility of the carrier of the PMOS transistor is lower than that of the carrier of the NMOS transistor, in order to improve the mobility of the carrier of the PMOS transistor when the device size is reduced, the fin of the PMOS transistor is formed by using silicon germanium, that is, the channel structure of the PMOS transistor is formed by using silicon germanium. In the present embodiment, the top surface of the fin material layer 30 of the PMOS region 10B is higher than the top surface of the substrate 10 of the NMOS region 10ABut is not limited to this range.

Referring to fig. 2D, step S4 is executed: a first masking layer 41 and a second masking layer 42 are sequentially conformally formed over the fin material layer 30.

Specifically, the first mask layer 41 and the second mask layer 42 are sequentially and conformally formed on the fin material layer 30, wherein the first mask layer 41 is used for protecting the fin material layer 30 from being exposed during a subsequent grinding process, and the second mask layer 42 is used for being ground by the subsequent grinding process; and the top surface of the second mask layer 42 of the PMOS region 10B is higher than the top surface of the first mask layer 41 of the NMOS region 10A to increase the process window, so that the flatness of the top surface of the first mask layer 41 of the NMOS region 10A and the top surface of the second mask layer 42 of the PMOS region 10B is better after the subsequent grinding process. In the present embodiment, conformal means that the first mask layer 41 and the second mask layer 42 are sequentially formed along the profile of the fin material layer 30, which may be equivalent to conformal and conformal. In this embodiment, the material of the first mask layer 41 is preferably silicon nitride, the material of the second mask layer 42 is preferably silicon oxide, and when the silicon oxide is polished in a subsequent process, the polishing process of the silicon oxide is easier to control. In thatIn the present embodiment, when the first mask layer 41 and the second mask layer 42 are sequentially conformally formed on the fin material layer 30, the thickness of the first mask layer 41 can beThe second mask layer 42 may have a thickness ofBut is not limited to this thickness range.

Referring to fig. 2E, step S5 is executed: and grinding to remove a part of the thickness of the second mask layer 42 by using the first mask layer 41 as a grinding stop layer.

Specifically, the second mask layer 42 is removed by grinding to a partial thickness, so that the grinding is stopped on the first mask layer 41 of the NMOS region 10A, and the grinding machine is prevented from contacting the fin material layer 30 during the grinding process. Since the top surface of the second mask layer 42 of the PMOS region 10B is higher than the top surface of the first mask layer 41 of the NMOS region 10A, the second mask layer 42 is mainly polished by using the first mask layer 41 as a polishing stop layer, so as to reduce the problem of poor flatness when different materials are polished at the same time, and the flatness of the top surface of the second mask layer 42 and the top surface of the first mask layer 41 is better after polishing. During the grinding process, the first mask layer 41 is allowed to be ground and touched, and a certain amount of over grinding can be added, wherein the thickness of the first mask layer 41 which is ground and removed is not more thanThe flatness of the top surface of the second mask layer 42 and the top surface of the first mask layer 41 after grinding is prevented from being greatly affected.

Referring to fig. 2F, step S6 is executed: etching to remove the first mask layer 41, the second mask layer 42, the fin material layer 30 of the NMOS region 10A, and the fin material layer 30 of the PMOS region 10B with a partial thickness, so that the top surface of the substrate 10 of the NMOS region 10A is flush with the top surface of the fin material layer 30 of the PMOS region 10B, and the rate of etching the first mask layer 41 and the rate of etching the second mask layer 42 are equal to the rate of etching the fin material layer 30.

Specifically, a dry etching process is adopted to remove the first mask layer 41, the second mask layer 42, the fin material layer 30 in the NMOS region 10A, and the fin material layer 30 in the PMOS region 10B with a partial thickness, in the dry etching process, the etching rate of the first mask layer 41 and the etching rate of the second mask layer 42 are equal to the etching rate of the fin material layer 30, so that the second mask layer 42, the first mask layer 41, and the fin material layer 30 can be etched in equal proportion, and the etching thicknesses are the same. After etching, the top surface of the substrate 10 of the NMOS region 10A is flush with the top surface of the fin material layer 30 of the PMOS region 10B, so that the flatness of the top surface of the substrate 10 of the NMOS region 10A and the top surface of the fin material layer 30 of the PMOS region 10B is improved. In this embodiment, when the dry etching process is used to remove the first mask layer 41, the second mask layer 42, the fin material layer 30 in the NMOS region 10A, and the fin material layer 30 in the PMOS region 10B with a partial thickness, the etching gas used includes CF₄And CHF₃，CF₄And CHF₃When etching silicon nitride, silicon oxide and silicon germanium, the etching rate is similar, and by controlling the flow ratio of the two gases, the etching rate of silicon nitride, silicon oxide and silicon germanium can be controlled₄And the CHF₃The flow ratio of (a) to (b) is 5:1 to 10:1, but not limited to the above gas and flow ratio. In order to completely remove the fin material layer 30 of the NMOS region 10A, the etching time of the dry etching process may be controlled, so that the substrate of the NMOS region 10A is over-etched to remove a portion of the thickness, and the thickness of the substrate of the NMOS region 10A removed by the over-etching may be equal toBut is not limited to this thickness range.

Referring to fig. 2G, step S7 is executed: and etching the substrate 10 of the NMOS region 10A and the fin material layer 30 of the PMOS region 10B to form a fin 51 of the NMOS transistor in the NMOS region 10A and a fin 52 of the PMOS transistor in the PMOS region 10B.

Specifically, the substrate 10 of the NMOS area 10A and the fin material layer 30 of the PMOS area 10B are etched to form a plurality of protrusions, the protrusions of the NMOS area 10A form the fins 51 of the NMOS transistor, the protrusions of the PMOS area 10B form the fins 52 of the PMOS transistor, the fins 51 of the NMOS transistor are the channel structure of the NMOS transistor, and the fins 52 of the PMOS transistor are the channel structure of the PMOS transistor.

In summary, in the fin type semiconductor device manufacturing method provided by the invention, a substrate is provided, the substrate includes a PMOS region and an NMOS region, the PMOS region is used for forming a PMOS transistor, and the NMOS region is used for forming an NMOS transistor; etching to remove part of the thickness of the substrate of the PMOS region; then conformally forming a fin material layer on the substrate in the PMOS region and the NMOS region; sequentially and conformally forming a first mask layer and a second mask layer on the fin material layer; furthermore, the first mask layer is used as a grinding stop layer, grinding is carried out to remove the second mask layer with partial thickness, the second mask layer is ground, the phenomenon of poor flatness when different materials are ground simultaneously is reduced, and the flatness of the top surface of the first mask layer and the top surface of the second mask layer is better after grinding; etching to remove the first mask layer, the second mask layer, the fin material layer of the NMOS region and the fin material layer of the PMOS region, so that the top surface of the substrate of the NMOS region is flush with the top surface of the fin material layer of the PMOS region, the etching rate of the first mask layer and the etching rate of the second mask layer are equal to the etching rate of the fin material layer, and the second mask layer, the first mask layer and the fin material layer can be etched in equal proportion, so that the flatness of the top surface of the substrate and the top surface of the fin material layer is better; and etching the substrate of the NMOS region and the fin material layer of the PMOS region to form the fins of the NMOS tube in the NMOS region and the fins of the PMOS tube in the PMOS region.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.