Three-level direct current converter, power supply system and chip

文档序号：1941083 发布日期：2021-12-07 浏览：6次中文

阅读说明：本技术 一种三电平直流转换器、电源系统及芯片 (Three-level direct current converter, power supply system and chip ) 是由于国磊宋树超秦俊良向志强于 2021-07-30 设计创作，主要内容包括：本申请提供了一种三电平直流转换器、电源系统及芯片,包括：飞跨电容、多个开关组、驱动电路和控制电路；控制电路至少包括导通时间发生器；导通时间发生器在飞跨电容上的电压偏离电源电压的一半时,改变导通时间发生器的电容的充电电流来调整输出的导通时间信号,导通时间信号输出给驱动电路；驱动电路根据导通时间信号生成驱动脉冲信号驱动多个开关组的开关状态来调整飞跨电容的充放电时间,飞跨电容上的电压与电源电压的一半之差的绝对值小于等于预设阈值。直流转换器的开关点的电压较为稳定,电感上的纹波电流较小,降低电感的纹波电流的额外损耗,改变导通时间发生器的充电电流调整飞跨电容上的电压大小,方案简单易于实现。(The application provides three-level direct current converter, power supply system and chip, include: the flying capacitor, a plurality of switch groups, a driving circuit and a control circuit; the control circuit at least comprises a conduction time generator; when the voltage of the flying capacitor deviates from half of the power supply voltage, the conduction time generator changes the charging current of the capacitor of the conduction time generator to adjust the output conduction time signal, and the conduction time signal is output to the driving circuit; the driving circuit generates a driving pulse signal according to the conducting time signal to drive the switch states of the switch groups to adjust the charging and discharging time of the flying capacitor, and the absolute value of the difference between the voltage on the flying capacitor and half of the power supply voltage is smaller than or equal to a preset threshold value. The voltage of a switch point of the direct current converter is stable, ripple current on the inductor is small, extra loss of the ripple current of the inductor is reduced, the voltage of the flying capacitor is adjusted by changing the charging current of the conduction time generator, and the scheme is simple and easy to implement.)

1. A three-level dc converter, comprising: the flying capacitor, a plurality of switch groups, a driving circuit and a control circuit; the control circuit at least comprises a conduction time generator;

the on-time generator is used for changing the charging current of the capacitor of the on-time generator to adjust the output on-time signal when the voltage on the flying capacitor deviates from half of the power supply voltage, and the on-time signal is output to the driving circuit;

the driving circuit is used for generating a driving pulse signal according to the conducting time signal to drive the switch states of the switch groups to adjust the charging and discharging time of the flying capacitor, so that the absolute value of the difference between the voltage on the flying capacitor and half of the power supply voltage is smaller than or equal to a preset threshold value.

2. The dc converter of claim 1, wherein the plurality of switch sets comprises: a first switch group, a second switch group, a third switch group and a fourth switch group; the on-time generator is used for outputting a first on-time signal to the first switch group and outputting a second on-time signal to the second switch group; in a continuous conduction mode, the switch state of the fourth switch set is complementary to the switch state of the first switch set, and the switch state of the third switch set is complementary to the switch state of the second switch set; and in each switching period of the four switching groups, the sum of the conducting time of the first switching group and the conducting time of the second switching group is within a preset time range.

3. The dc converter of claim 2, wherein the control circuit further comprises: an error amplifier, a conduction time separator and a charging current control circuit; the on-time generator comprises a first on-time generator and a second on-time generator;

two input ends of the error amplifier are respectively connected with the output voltage of the direct current converter and a preset voltage and used for outputting an error signal according to the difference value of the output voltage of the direct current converter and the preset voltage;

the on-time separator is used for outputting a first enable signal of the first on-time generator and a second enable signal of the second on-time generator according to the error signal;

the charging current control circuit is used for comparing the voltage of the flying capacitor with a half of the power supply voltage and generating a first charging current of the first conduction time generator and a second charging current of the second conduction time generator according to a comparison result; the sum of the first charging current and the second charging current is within a preset current range.

4. The dc converter according to claim 3, wherein the charge current control circuit comprises: the first PMOS tube and the second PMOS tube;

the source electrode of the first PMOS tube is connected with a first constant current source, and the source electrode of the second PMOS tube is connected with the first constant current source;

the grid electrode of the first PMOS tube is connected with half of the power supply voltage, and the grid electrode of the second PMOS tube is connected with the voltage on the flying capacitor;

the drain electrode of the first PMOS tube generates the first charging current to be output to the first conduction time generator, and the drain electrode of the second PMOS tube generates the second charging current to be output to the second conduction time generator.

5. The dc converter of claim 1, wherein the control circuit further comprises: an on-time separator;

the on-time separator is configured to separate a first on-time signal and a second on-time signal to the driving circuit according to the on-time signal output by the on-time generator, where the first on-time signal corresponds to the first switch group, and the second on-time signal corresponds to the second switch group; in a continuous conduction mode, the switch state of the fourth switch set is complementary to the switch state of the first switch set, and the switch state of the third switch set is complementary to the switch state of the second switch set; and in each switching period of the four switching groups, the sum of the conducting time of the first switching group and the conducting time of the second switching group is within a preset time range.

6. The dc converter of claim 5, wherein the control circuit further comprises: an error amplifier and a charging current control circuit;

two input ends of the error amplifier are respectively connected with the output voltage of the direct current converter and a preset voltage and used for outputting an error signal according to the difference value between the voltage on the flying capacitor and the preset voltage;

and the charging current control circuit is used for comparing the voltage on the flying capacitor with a half of the power supply voltage and generating the charging current of the conduction time generator according to a comparison result and two complementary signals output by a D trigger in the conduction time separator.

7. The dc converter of claim 6, wherein the charge current control circuit comprises: the third PMOS tube, the fourth PMOS tube, the first switch tube and the second switch tube;

the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are both connected with a second constant current source, the grid electrode of the third PMOS tube is connected with half of the power supply voltage, and the grid electrode of the fourth PMOS tube is connected with the voltage on the flying capacitor;

the drain electrode of the third PMOS tube is connected with the first end of the first switch tube, the drain electrode of the fourth PMOS tube is connected with the first end of the second switch tube, and the second end of the first switch tube and the second end of the second switch tube are connected together to output the charging current;

the first output end of the D trigger is connected with the control end of the first switch tube, and the second output end of the D trigger is connected with the control end of the second switch tube.

8. The DC converter according to claim 7, wherein the first switch tube and the second switch tube are NMOS tubes.

9. The dc converter according to any one of claims 2 to 8, wherein a sum of the on-time of the first switch group and the on-time of the second switch group in each switch cycle of the four switch groups is within a preset time range, and specifically comprises: the on-time of the first switch group is changed by a first time, and the on-time of the second switch group is changed by the first time in the opposite direction.

10. The dc converter of any of claims 1-9, wherein the deviation of the voltage on the flying capacitor from half the supply voltage specifically comprises: the absolute value of the difference between the voltage on the flying capacitor and half of the power supply voltage is greater than the preset threshold.

11. A power supply system comprising the dc converter of any one of claims 1-10, and further comprising: a rectifier and a buck converter;

the input end of the rectifier is used for connecting an alternating current power supply;

the output end of the rectifier is connected with the input end of the buck converter;

the output end of the buck converter is connected with the input end of the direct current converter.

12. The system of claim 11, wherein the buck converter is an open-loop buck converter.

13. The system of claim 11 or 12, wherein the input voltage of the buck converter is 48V, the output voltage of the buck converter is 12V; the output voltage of the direct current converter supplies power to the chip.

14. A driving chip of a three-level DC converter is characterized by comprising: the driving circuit and the control circuit are used for driving the three-level direct current converter, and the three-level converter comprises a flying capacitor and a plurality of switch groups; the control circuit at least comprises a conduction time generator;

the on-time generator is used for changing the charging current of the capacitor of the on-time generator to adjust the output on-time when the voltage of the flying capacitor deviates from half of the power supply voltage, and the on-time is output to the driving circuit;

the driving circuit is used for generating a driving pulse signal according to the conducting time to drive the switching states of the plurality of switch groups to adjust the charging and discharging time of the flying capacitor, so that the absolute value of the difference between the voltage on the flying capacitor and half of the power supply voltage is smaller than or equal to a preset threshold value.

15. The chip of claim 14, wherein the plurality of switch sets comprises: a first switch group, a second switch group, a third switch group and a fourth switch group; the on-time generator is used for outputting a first on-time signal to the first switch group and outputting a second on-time signal to the second switch group; in a continuous conduction mode, the switch state of the fourth switch set is complementary to the switch state of the first switch set, and the switch state of the third switch set is complementary to the switch state of the second switch set; and the sum of the first conduction time and the second conduction time in each switching period of the four switching groups is within a preset time range.

16. The chip of claim 15, wherein the control circuit further comprises: an error amplifier, a conduction time separator and a charging current control circuit; the on-time generator control circuit comprises a first on-time generator and a second on-time generator;

the on-time separator is used for outputting a first enable signal of the first on-time generator and a second enable signal of the second on-time generator according to the error signal;

17. The chip of claim 14, wherein the control circuit further comprises: an on-time separator;

18. The chip of claim 17, wherein the control circuit further comprises: an error amplifier and a charging current control circuit;

two input ends of the error amplifier are respectively connected with the output voltage of the direct current converter and a preset voltage and used for outputting an error signal according to the difference value between the voltage on the flying capacitor and the preset voltage;

Technical Field

The application relates to the technical field of power electronics, in particular to a three-level direct current converter, a power supply system and a chip.

Background

A Direct Current (DC)/DC converter is a commonly used switching power converter in an electronic system, and is used for performing DC-DC conversion, either step-up conversion or step-down conversion.

The DC/DC converter can be classified into a two-level topology and a multi-level topology according to the level state of the switching point. The switching point levels of the two-level topology include both 0 and the input voltage, while the multi-level topology exceeds both levels. At present, a commonly used DC/DC converter is a flying capacitor clamped three-level DC converter, which is referred to as a DC converter with a flying capacitor for short, and stores half of the input voltage through the flying voltage, so that the switching point voltage includes three types of input voltages, i.e., 0, 1/2 and the input voltage, and the variation range of the switching point voltage is changed into half of a two-level topology, and further, a low-voltage-resistant switching tube can be used to improve the performance of an electronic system.

The direct current converter with the flying capacitor comprises the flying capacitor and at least four switch groups which are sequentially connected in series: the first switch group, the second switch group, the third switch group and the fourth switch group. The voltage on the flying capacitor in the dc converter with the flying capacitor needs to be maintained at half of the power supply voltage, otherwise, the voltage at the switching point when the first switch group and the third switch group are turned on is different from the voltage at the switching point when the second switch group and the fourth switch group are turned on, and further ripple current of the inductor in the circuit is increased, which results in extra power loss.

Disclosure of Invention

In order to solve the above technical problem, the present application provides a three-level dc converter, a power supply system, and a chip, which can reduce ripple current of an inductor in a circuit, thereby reducing extra power loss.

The three-level direct current converter provided by the embodiment of the application comprises a flying capacitor, a plurality of switch groups, a driving circuit and a control circuit; when the voltage of the flying capacitor deviates from half of the power supply voltage, the control circuit changes the charging current of the capacitor of the conduction time generator by controlling the conduction time generator so as to adjust the conduction time signal output by the conduction time generator, wherein the conduction time signal corresponds to the switching time of a plurality of switching tubes; the driving circuit generates a driving pulse signal according to the conducting time signal to drive the switch states of the switch groups, so as to adjust the charging and discharging time of the flying capacitor, and the absolute value of the difference between the voltage on the flying capacitor and half of the power supply voltage is less than or equal to a preset threshold value, even if the voltage on the flying capacitor is half of the power supply voltage. The smaller the value of the preset threshold value is, the closer the voltage on the flying capacitor is to half of the power supply voltage.

Therefore, the dc converter provided in the embodiment of the present application compares half of the power supply voltage with the voltage across the flying capacitor, and adjusts the magnitude of the charging current of the capacitor of the on-time generator when the voltage across the flying capacitor deviates from half of the power supply voltage, thereby adjusting the on-time signal output by the on-time generator. The control circuit controls the conduction time of the switch groups according to the conduction time signal output by the conduction time generator, namely the conduction time of the switch groups is controlled, so that the charging time of the flying capacitor and the discharging time of the flying capacitor are adjusted, when the charging time and the discharging time of the flying capacitor are changed, the voltage on the flying capacitor is changed, and finally the voltage on the flying capacitor is maintained at half of the power supply voltage. Therefore, the voltage of a switching point of the direct current converter can be ensured to be relatively stable, the ripple current on the inductor connected with the switching point is relatively small, and the extra loss caused by the ripple current on the inductor can be reduced. In addition, the voltage of the flying capacitor can be adjusted only by changing the charging current of the on-time generator, and the scheme is simple and easy to implement.

As a possible implementation manner, a plurality of switch groups provided in the embodiments of the present application include: a first switch group, a second switch group, a third switch group and a fourth switch group; the conduction time generator is used for outputting a first conduction time signal to the first switch group and outputting a second conduction time signal to the second switch group; in the continuous conduction mode, the switch state of the fourth switch group is complementary with the switch state of the first switch group, and the switch state of the third switch group is complementary with the switch state of the second switch group; the sum of the conducting time of the first switch group and the conducting time of the second switch group in each switching period of the four switch groups is within a preset time range. Therefore, when the voltage on the flying capacitor is adjusted through the first conduction time and the second conduction time, the sum of the first conduction time and the second conduction time is ensured to be basically constant, namely, the increase value of the first conduction time is equal to the decrease value of the second conduction time, or the increase value of the second conduction time is equal to the decrease value of the first conduction time. Therefore, the on-time generator provided by the embodiment of the application can maintain the voltage on the flying capacitor to be stabilized at half of the power supply voltage on the premise of reducing the fluctuation of the output voltage.

As a possible implementation manner, the control circuit provided in the embodiment of the present application further includes: an error amplifier, a conduction time separator and a charging current control circuit; the on-time generator comprises a first on-time generator and a second on-time generator; the two input ends of the error amplifier are respectively connected with the output voltage of the direct current converter and a preset voltage and used for outputting an error signal according to the difference value of the output voltage of the direct current converter and the preset voltage; a turn-on time separator for outputting a first enable signal of the first turn-on time generator and a second enable signal of the second turn-on time generator according to the error signal; the charging current control circuit is used for comparing the voltage on the flying capacitor with a half of the power supply voltage and generating a first charging current of the first conduction time generator and a second charging current of the second conduction time generator according to a comparison result; the sum of the first charging current and the second charging current is within a preset current range. For example, when the voltage across the flying capacitor is greater than half of the power supply voltage, the first charging current becomes larger, and the voltage at the positive input terminal of the comparator in the first on-time generator rises faster, so that the first on-time becomes shorter, and further the time during which the first switch group is on, that is, the charging time of the flying capacitor becomes shorter. Accordingly, the second charging current decreases, and the voltage at the positive input terminal of the comparator in the second on-time generator increases slowly, so that the second on-time is increased, and further the on-time of the second switch group is increased, that is, the discharge time of the flying capacitor is increased. The charging time and the discharging time of the flying capacitor become longer, and the voltage on the flying capacitor becomes smaller and equal to half of the power supply voltage. And because the sum of the first charging current and the second charging current is equal to a constant current, the sum of the first conduction time and the second conduction time is basically fixed and unchanged, and therefore, the influence on the output voltage is small in the process of changing the first charging current and the second charging current.

As a possible implementation manner, a charging current control circuit provided in an embodiment of the present application includes: the first PMOS tube and the second PMOS tube; the source electrode of the first PMOS tube is connected with a first constant current source, and the source electrode of the second PMOS tube is connected with the first constant current source; the grid electrode of the first PMOS tube is connected with half of the power supply voltage, and the grid electrode of the second PMOS tube is connected with the voltage on the flying capacitor; the drain electrode of the first PMOS tube generates a first charging current to be output to the first conduction time generator, and the drain electrode of the second PMOS tube generates a second charging current to be output to the second conduction time generator.

As a possible implementation manner, the control circuit provided in the embodiment of the present application further includes: an on-time separator; the conduction time separator is used for separating a first conduction time signal and a second conduction time signal according to the conduction time signal output by the conduction time generator and sending the first conduction time signal and the second conduction time signal to the driving circuit, the first conduction time signal corresponds to the first switch group, and the second conduction time signal corresponds to the second switch group; in the continuous conduction mode, the switch state of the fourth switch group is complementary with the switch state of the first switch group, and the switch state of the third switch group is complementary with the switch state of the second switch group; the sum of the conducting time of the first switch group and the conducting time of the second switch group in each switching period of the four switch groups is within a preset time range. It should be understood that the period of the on-time signal is such that the waveform of the on-time signal in the first period is the same as the waveform of the first on-time signal in the first period, and the waveform of the on-time signal in the second period is the same as the waveform of the second on-time signal in the second period. The first on time plus the second on time equals the on time.

As a possible implementation manner, the control circuit provided in the embodiment of the present application further includes: an error amplifier and a charging current control circuit; two input ends of the error amplifier are respectively connected with the output voltage of the direct current converter and a preset voltage and used for outputting an error signal according to the difference value of the voltage on the flying capacitor and the preset voltage; and the charging current control circuit is used for comparing the voltage on the flying capacitor with a half of the power supply voltage and generating the charging current of the conduction time generator according to the comparison result and two complementary signals output by the D trigger in the conduction time separator. Therefore, the on-time generator of the dc converter provided in the embodiment of the present application is connected to the error amplifier through the pulse generator, the on-time generator directly generates a comprehensive on-time according to the signal output by the pulse generator, and outputs the comprehensive on-time to the on-time separator, and the on-time separator separates the first on-time and the second on-time according to the comprehensive on-time to control the four switch sets, so as to maintain the voltage on the flying capacitor at half of the power supply voltage. Therefore, the voltage of the switching point of the direct current converter provided by the embodiment of the application is stable, the ripple current of the inductor is reduced, and the extra loss caused by the ripple current is reduced.

As a possible implementation manner, a charging current control circuit provided in an embodiment of the present application includes: the third PMOS tube, the fourth PMOS tube, the first switch tube and the second switch tube; the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are both connected with a second constant current source, the grid electrode of the third PMOS tube is connected with half of the power supply voltage, and the grid electrode of the fourth PMOS tube is connected with the voltage on the flying capacitor; the drain electrode of the third PMOS tube is connected with the first end of the first switch tube, the drain electrode of the fourth PMOS tube is connected with the first end of the second switch tube, and the second end of the first switch tube and the second end of the second switch tube are connected together to output charging current; the first output end of the D trigger is connected with the control end of the first switch tube, and the second output end of the D trigger is connected with the control end of the second switch tube.

As a possible implementation manner, the first switching tube and the second switching tube provided in the embodiments of the present application are both NMOS tubes.

As a possible implementation manner, in each switching period of the four switching groups, a sum of the on time of the first switching group and the on time of the second switching group is within a preset time range, which specifically includes: the on-time of the first switch group is changed by a first time, and the on-time of the second switch group is changed by a first time in the opposite direction.

As a possible implementation manner, the deviation of the voltage on the flying capacitor from half of the power supply voltage provided by the embodiment of the present application specifically includes: the absolute value of the difference between the voltage on the flying capacitor and half of the supply voltage is greater than a preset threshold.

According to the three-level dc converter provided in the foregoing embodiment, an embodiment of the present application further provides a power supply system, including the dc converter in the foregoing embodiment, further including: a rectifier and a buck converter; the input end of the rectifier is used for connecting an alternating current power supply; the output end of the rectifier is connected with the input end of the buck converter; the output end of the buck converter is connected with the input end of the direct current converter.

As a possible implementation, the buck converter provided in the embodiments of the present application is an open-loop buck converter.

As a possible implementation manner, the input voltage of the buck converter provided in the embodiment of the present application is 48V, and the output voltage of the buck converter is 12V; the output voltage of the direct current converter supplies power for the chip.

According to the three-level dc converter and the power supply system provided in the above embodiments, an embodiment of the present application further provides a driving chip of the three-level dc converter, including: the driving circuit and the control circuit are used for driving the three-level direct current converter, and the three-level converter comprises a flying capacitor and a plurality of switch groups; the control circuit at least comprises a conduction time generator; the on-time generator is used for changing the charging current of the capacitor of the on-time generator to adjust the on-time output by the on-time generator when the voltage on the flying capacitor deviates from half of the power supply voltage, and the on-time is output to the driving circuit; and the driving circuit is used for generating a driving pulse signal according to the conducting time to drive the switching states of the plurality of switch groups to adjust the charging and discharging time of the flying capacitor, so that the absolute value of the difference between the voltage on the flying capacitor and half of the power supply voltage is smaller than or equal to a preset threshold value.

The application has at least the following advantages:

the direct current converter provided by the embodiment of the application compares half of a power supply voltage with a voltage on the flying capacitor, and adjusts the magnitude of a charging current of a capacitor of the conduction time generator when the voltage on the flying capacitor deviates from half of the power supply voltage, so that a conduction time signal output by the conduction time generator is adjusted. The control circuit controls the conduction time of the switch groups according to the conduction time signal output by the conduction time generator, namely the conduction time of the switch groups is controlled, so that the charging time of the flying capacitor and the discharging time of the flying capacitor are adjusted, when the charging time and the discharging time of the flying capacitor are changed, the voltage on the flying capacitor is changed, and finally the voltage on the flying capacitor is maintained at half of the power supply voltage. Therefore, the voltage of a switching point of the direct current converter can be ensured to be relatively stable, the ripple current on the inductor connected with the switching point is relatively small, and the extra loss caused by the ripple current on the inductor can be reduced. In addition, the voltage of the flying capacitor can be adjusted only by changing the charging current of the on-time generator, and the scheme is simple and easy to implement.

Drawings

Fig. 1 is a schematic diagram of a power supply system according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a driving portion of a dc converter with a flying capacitor according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a three-level dc converter according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of an on-time generator according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram of a waveform of an on-time generator according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a control circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a on-time separator according to an embodiment of the present application;

fig. 8 is a signal waveform diagram of a control circuit according to an embodiment of the present application;

fig. 9 is a schematic diagram of a charging current control circuit according to an embodiment of the present disclosure;

fig. 10 is a circuit diagram of a charging current control circuit corresponding to the schematic diagram of fig. 9;

fig. 11 is a schematic diagram of a dc converter according to an embodiment of the present application;

fig. 12 is a circuit diagram of a pulse generator according to an embodiment of the present application;

fig. 13 is a circuit diagram of a on-time separator according to an embodiment of the present application;

fig. 14 is a schematic diagram of a charging current control circuit according to an embodiment of the present disclosure;

fig. 15 is a circuit diagram of a charging current control circuit corresponding to the schematic diagram of fig. 14;

fig. 16 is a signal waveform diagram of a control circuit according to an embodiment of the present application;

fig. 17 is a schematic diagram of a power supply system according to an embodiment of the present application;

fig. 18 is a schematic diagram of a driving chip according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

The terms "first," "second," and the like in the following description are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

In the present application, unless expressly stated or limited otherwise, the term "coupled" is to be construed broadly, e.g., "coupled" may be a fixed connection, a removable connection, or an integral part; may be directly connected or indirectly connected through an intermediate. Furthermore, the term "coupled" may be a manner of making electrical connections that communicate signals. "coupled" may be a direct electrical connection or an indirect electrical connection through intervening media.

The embodiment of the present application relates to a three-level dc converter, which is used for performing dc-dc electric energy conversion, for example, boost conversion or buck conversion. In addition, the embodiment of the present application does not limit the specific application scenario of the three-level dc converter, and for example, the present application may be applied to various application scenarios requiring dc-dc conversion, such as a server, a communication base station, a photovoltaic device, and a terminal device. When the three-level dc converter is applied to a switching power supply, the switching power supply may be applied to a terminal device, for example, a power adapter of the terminal device, and the three-level dc converter may convert an input voltage into a voltage suitable for a load, for example, the load may be a chip or a control circuit. The embodiment of the application does not specifically limit the type of the terminal device, and the terminal device may be a mobile phone (mobile phone), a tablet computer (pad), a computer, an intelligent wearable product (e.g., a smart watch, a smart bracelet, an earphone, etc.), a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, and other devices.

In order to make those skilled in the art better understand the technical solution provided by the embodiment of the present application, an application scenario of the three-level dc converter provided by the embodiment of the present application is described below with reference to the drawings.

The following description will take the application of the three-level dc converter provided in the embodiments of the present application to a switching power supply as an example

Referring to fig. 1, the figure is a schematic diagram of a power supply system according to an embodiment of the present application.

As shown in fig. 1, a power supply system provided in an embodiment of the present application includes an Alternating Current (AC)/DC converter 100, a first DC/DC converter 200, and a second DC/DC converter 300.

The first DC/DC converter 200 and the second DC/DC converter 300 may be implemented by three-level DC converters provided in the embodiments of the present application.

Wherein, the input end of the AC/DC converter 100 is used for connecting an alternating current power supply, such as a commercial alternating current 220V; the output end of the AC/DC converter 100 is connected to the input end of the first DC/DC converter 200; the output terminal of the first DC/DC converter 200 is connected to the input terminal of the second DC/DC converter 300; the output of the second DC/DC converter 300 is used for connecting a load.

In the present embodiment, the first DC/DC converter 200 and the second DC/DC converter 300 are both implemented as buck converters, where the first DC/DC converter 200 is configured to receive the output voltage of the AC/DC converter 100, and output the output voltage to the second DC/DC converter 300 after being stepped down, and the output voltage may be implemented by using an open-loop control buck converter or a closed-loop control buck converter. The second DC/DC converter 300 is configured to receive the output voltage of the first DC/DC converter 200, and output the output voltage to a load after voltage reduction, which may be implemented by using a closed-loop controlled buck converter.

The voltage output by the second DC/DC converter 300 is used to power a load. Since the second DC/DC converter 300 can realize closed-loop control, it has both voltage reduction and voltage stabilization functions, so that the output voltage is stable and controllable.

As a possible implementation manner, the AC/DC converter 100 provided in this embodiment of the application is configured to convert 220V alternating current into 48V direct current, the first DC/DC converter 200 is configured to convert 48V direct current into 12V direct current, and the second DC/DC converter 300 is configured to further step down the 12V direct current, for example, the voltage may be stepped down to 5V, 3.3V, or 1.2V to supply power to a load such as a chip.

It should be understood that the first DC/DC converter 200 provided in the embodiment of the present application is only used to reduce the input voltage of 48V to 12V, and the output voltage thereof is not directly supplied to the chip or other loads, but is further stepped down and stabilized by the second DC/DC converter 300. The voltage output by the second DC/DC converter 300 is more stable and accurate, so that the power supply requirements of loads such as chips can be met.

The 12V voltage output by the first DC/DC converter 200 provided in the embodiment of the present application can be controlled in an open loop manner, and the output voltage is allowed to fluctuate within a certain range as long as the input voltage range of the second DC/DC converter 300 is satisfied. Therefore, the first DC/DC converter 200 for the first stage step-down can be designed as an open-loop converter.

Accordingly, the output voltage of the second DC/DC converter 300 provided by the embodiment of the present application must meet the power supply requirement of the chip or other loads, provide a more accurate and stable output voltage, and perform negative feedback closed-loop control by detecting the voltage at the output terminal and feeding the detected voltage back to the input terminal for the purpose of more stable and accurate output voltage. That is, the second DC/DC converter 300 provided in the embodiment of the present application can perform closed-loop control, so that the voltage at the output terminal thereof is more stable. Therefore, the second DC/DC converter 300 for the second stage step-down can be designed as a closed-loop converter.

The second DC/DC converter described above is implemented by using a DC converter with a flying capacitor, and a specific architecture of the DC converter with a flying capacitor is described below with reference to the drawings.

The flying capacitor-equipped dc converter provided by the embodiments of the present application includes a plurality of switch groups, where each switch group may include one controllable switch or a plurality of controllable switches. The controllable switch provided in the embodiment of the present application may be specifically implemented by a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), or may be implemented by an Insulated Gate Bipolar Transistor (IGBT) or a Bipolar Junction Transistor (BJT). For the convenience of understanding the scheme provided by the embodiment of the present application, the following description will take the example that the dc converter includes four switch groups, and each switch group includes one controllable switch.

Referring to fig. 2, the figure is a schematic diagram of a dc converter driving portion with a flying capacitor according to an embodiment of the present application.

The flying capacitor clamp type three-level direct current converter provided by the embodiment of the application comprises: flying capacitor CF, a plurality of switch groups (first switch group M1, second switch group M2, third switch group M3, and fourth switch group M4).

As shown in fig. 2, a first terminal of the first switch group M1 is connected to the power supply voltage VIN, a second terminal of the first switch group M1 is connected to a first terminal of the second switch group M2, a second terminal of the second switch group M2 is connected to a first terminal of the third switch group M3, a second terminal of the third switch group M3 is connected to a first terminal of the fourth switch group, and a second terminal of the fourth switch group is connected to ground.

A first terminal of the flying capacitor CF is connected between the first switch group M1 and the second switch group M2; a second terminal of the flying capacitor CF is connected between the third switch group M3 and the fourth switch group M4; the switch point SW is located between the second switch group M2 and the third switch group M3; the switching point SW is used to output the output voltage Vout through the inductor LOUT.

In the dc converter with flying capacitor provided in the embodiment of the present application, the first switch group M1 and the second switch group M2 alternately operate when the system reaches a steady state, that is, the phase difference between the driving signal corresponding to the first switch group M1 and the driving signal corresponding to the second switch group M2 is half of the driving signal period. Accordingly, the third switch group M3 and the fourth switch group M4 are also alternately operated, and the phase of the driving signal corresponding to the third switch group M3 is different from that of the driving signal corresponding to the fourth switch group M4 by half of the driving signal period.

The switch states of the first switch group M1 and the fourth switch group M4 are complementary, that is, the fourth switch group M4 is turned off when the first switch group M1 is turned on, and the fourth switch group M4 is turned on when the first switch group M1 is turned off. The switch states of the second switch group M2 and the third switch group M3 are complementary, the third switch group M3 is turned off when the second switch group M2 is turned on, and the third switch group M3 is turned on when the second switch group M2 is turned off.

In normal operation of a dc converter with a flying capacitor, the voltage VCF across the flying capacitor CF should be equal to half the supply voltage VIN, i.e., 1/2 VIN. If the voltage VCF deviates from 1/2VIN, when the first switch group M1 and the third switch group M3 are turned on, and when the second switch group M2 and the fourth switch group are turned on, the voltage at the switch point SW may deviate, which may cause the ripple current of the inductor LOUT to rise, resulting in additional loss. Meanwhile, voltage stress larger than 1/2VIN is generated on the switch group, and a power tube with higher withstand voltage is needed.

The embodiment of the application provides a direct current converter with a flying capacitor, which adjusts the output conduction time of the direct current converter by changing the charging current of a capacitor of a conduction time Generator (TON Generator), and outputs the conduction time to a driving circuit so as to maintain the voltage VCF on the flying capacitor CF to be stable at 1/2VIN, so that the voltage of a switch point SW is stable, the ripple current of an inductor LOUT is reduced, and the extra loss caused by the ripple current is reduced. And meanwhile, the voltage stress of the switch group is kept near 1/2VIN, and a power tube with higher voltage resistance does not need to be used. The capacitor is a capacitor inside the on-time generator.

The dc converter with flying capacitor provided by the embodiments of the present application will be described below by taking a dc converter including four switch groups as an example, and with reference to the accompanying drawings.

Referring to fig. 3, the diagram is a schematic diagram of a three-level dc converter according to an embodiment of the present disclosure.

As shown in fig. 3, the three-level dc converter provided in the embodiment of the present application includes: flying capacitor CF, driver circuit 400, and control circuit 500, control circuit 500 includes at least on-time generator 501. Still include the following at least four switch groups that connect in series in proper order: the structure and relationship of the first switch group M1, the second switch group M2, the third switch group M3 and the fourth switch group M4 are the same as those in fig. 2, and are not described herein again.

The on-time generator 501 is configured to change the charging current of the internal capacitor to adjust the output on-time signal when the voltage VCF on the flying capacitor CF deviates from 1/2VIN, and the on-time signal is output to the driving circuit 400.

The driving circuit 400 is configured to generate a driving pulse signal according to the on-time signal to drive the plurality of switch groups, that is, the switching states of the first switch group M1, the second switch group M2, the third switch group M3, and the fourth switch group M4 to adjust the charging and discharging time of the flying capacitor CF, so that the absolute value of the difference between the voltages VCF and 1/2VIN on the flying capacitor CF is less than or equal to a preset threshold.

It should be noted that the difference between VCF and 1/2VIN in the embodiment of the present application may be positive or negative, that is, VCF may be greater than 1/2VIN, and VCF may also be smaller than 1/2 VIN. The absolute value of the difference between the voltages VCF and 1/2VIN on the flying capacitor CF is less than or equal to a preset threshold, i.e., there may be a certain difference between VCF and 1/2VIN in practical applications. The preset threshold may actually be selected according to the accuracy required by the dc converter on the VCF, and when the preset threshold is smaller, it indicates that the smaller the difference between VCF and 1/2VIN, the closer the VCF and 1/2VIN are in value, and the more accurate the dc converter is in controlling the VCF. For convenience, the voltage VCF across the flying capacitor CF is substantially equal to 1/2 VIN.

The voltage VCF on the flying capacitor CF can be obtained by a voltage sampling circuit, and in order to enable a later-stage circuit to conveniently process a voltage signal, a voltage signal proportional to the VCF can be collected, that is, the voltage signal can represent the size of the VCF. The embodiment of the present application also does not limit the execution body for completing VCFs and 1/2VIN, and may be implemented by an analog circuit or a chip, for example.

The magnitude of the charging current provided by the embodiment of the present application can be determined according to the degree to which the voltage VCF on the flying capacitor CF deviates from the power supply voltage 1/2 VIN. The input end of the on-time generator 501 provided in the embodiment of the present application may be connected to a charging current, and when the charging current changes, the on-time signal output by the on-time generator 501 changes, the duty ratio of the driving signal output by the driving circuit changes, and the switching states of the four switch groups M1-M4 change, that is, the on-off time changes, so as to affect the charging and discharging time of the flying capacitor CF, and further affect the voltage on the CF, and stabilize the voltage VCF on the flying capacitor CF at 1/2 VIN. As a possible implementation, the charging current of the on-time generator and the on-time of its output, which are used for illustration in the examples of the present application, may be inversely related, i.e. the time during which the on-time signal is high becomes shorter as the charging current increases. As another possible implementation manner, the charging current of the on-time generator and the on-time of the output thereof may be positively correlated, that is, when the charging current increases, the time during which the on-time signal is high becomes longer, and the embodiment of the present application is not limited herein.

The operation principle of the on-time generator provided by the embodiment of the present application is described below with reference to the accompanying drawings.

Referring to fig. 4, the figure is a schematic diagram of an on-time generator according to an embodiment of the present disclosure.

Referring to fig. 5, a waveform timing diagram of an on-time generator according to an embodiment of the present application is shown.

The on-time generator provided by the embodiment of the application comprises: a switch P, a capacitor CT, a constant voltage source VR and a comparator AMP. The capacitor CT in fig. 4 is an internal capacitor of the on-time generator, and the technical solution provided in the embodiment of the present application is to change the on-time output by the on-time generator by changing the charging current I of the capacitor CT, and specifically may be determined according to the degree of deviation of the voltage VCF on the flying capacitor CF from 1/2 VIN.

When the enable signal ST has a pulse signal, the switch P is turned on and the capacitor CT is discharged. As shown in fig. 5, the voltage at the point VC at this time is 0V, and since the positive input voltage VC, i.e., 0V, of the comparator AMP is less than the negative input voltage VR of the comparator AMP, the output voltage COMP of the comparator AMP is at a low level. The output voltage of the comparator AMP and the enable signal output the on-time signal TON through a nor gate. Since the enable signal becomes low after a pulse, the output voltage COMP of the comparator AMP also becomes low, and the on-time signal TON output by the on-time generator changes from low to high.

When the pulse signal of the enable signal ST is ended, the switch P is turned off, and the charging current I starts to charge the capacitor CT. As shown in fig. 5, the voltage across the capacitor C starts to rise, i.e. the voltage VC starts to rise, and the rising speed is proportional to the magnitude of the charging current I, when the voltage VC is equal to or higher than the constant voltage VR, the output voltage COMP of the comparator AMP is at a high level, and the on-time signal TON output by the on-time generator changes from a high level to a low level.

Specifically, when the first switch group M1 and the third switch group M3 are turned on, the flying capacitor is charged by the power supply voltage VIN, and when the second switch group M2 and the fourth switch group M4 are turned on, the flying capacitor is discharged. According to the driving circuit 400 provided by the embodiment of the application, when the voltage VCF across the flying capacitor is less than 1/2VIN, the on time of the first switch group M1 and the third switch group M3 is prolonged, and/or the on time of the second switch group M2 and the fourth switch group M4 is reduced, so that the voltage VCF across the flying capacitor is increased to be consistent with 1/2 VIN. Accordingly, when the voltage VCF across the flying capacitor is greater than 1/2VIN, the time that the first and third switch groups M1 and M3 are turned on is reduced and/or the time that the second and fourth switch groups M2 and M4 are turned on is extended according to the turn-on time, so that the voltage VCF across the flying capacitor is reduced to coincide with 1/2 VIN.

As can be seen from the above, the dc converter provided in the embodiment of the present application can adjust the magnitude of the charging current in the on-time generator according to the voltage across the flying capacitor and half of the power supply voltage, so as to adjust the on-time signal output by the on-time generator. According to the on-time signal output by the on-time generator, the on-time of the four switch groups is controlled, namely the on-off time of the four switch groups is controlled, namely the charging time and the discharging time of the flying capacitor are controlled, so that the voltage on the flying capacitor is influenced, and the voltage on the flying capacitor is maintained at half of the power supply voltage. Therefore, the voltage of the switching point of the direct current converter provided by the embodiment of the application is stable, the ripple current of the inductor is reduced, and the extra loss caused by the ripple current is reduced.

In practical application, the on-time generator provided by the embodiment of the application can output two different on-time signals to control a plurality of switch groups; in addition, the on-time generator provided by the embodiment of the application can also output one on-time signal to control a plurality of switch groups. First, a scheme of controlling four switch groups by outputting two different on-time signals by an on-time generator, that is, a scheme of a dual on-time generator, will be described with reference to a dc converter including four switch groups as an example.

When the on-time generator outputs two different on-time signals to control the four switch sets, the on-time generator may output a first on-time signal to the first switch set and a second on-time signal to the second switch set. The conducting state of the first switch group is complementary with the conducting state of the fourth switch group, and the conducting state of the second switch group is complementary with the conducting state of the third switch group. In each switching period of the four switching groups, the sum of the first conduction time and the second conduction time is kept consistent, namely is basically constant, and fluctuation of the output voltage Vout of the three-level direct current converter can be effectively inhibited, wherein the consistency means that the sum of the conduction time of the first switching group (hereinafter referred to as the first conduction time) and the conduction time of the second switching group (hereinafter referred to as the second conduction time) is within a preset time range compared with each switching period. It should be understood that the sum of the first on-time and the second on-time may have a certain error from the ideal preset time, but the sum of the first on-time and the first on-time should be within the preset time range. The preset time range should include an ideal preset time, and the size of the preset time range can be selected according to the precision of the first on time and the second on time. The smaller the preset time range is, the higher the accuracy of the first on time and the second on time is.

The sum of the first on-time and the second on-time provided by the embodiment of the present application does not change much in each period, and for convenience of description, the sum of the first on-time and the second on-time is basically fixed. Therefore, when the voltage VCF on the flying capacitor CF is adjusted by the first on-time and the second on-time, the embodiment of the present application ensures that the sum of the first on-time and the second on-time is substantially constant, that is, the increase value of the first on-time is equal to the decrease value of the second on-time, or the increase value of the second on-time is equal to the decrease value of the first on-time. Therefore, the on-time generator provided by the embodiment of the present application can maintain the voltage VCF on the flying capacitor CF stable at 1/2VIN on the premise of reducing the fluctuation of the output voltage Vout.

The control circuit of the embodiment of the present application may further include an error amplifier, a conduction time separator, and a charging current control circuit, in addition to the conduction time generator described in the above embodiment. The control circuit provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

Referring to fig. 6, the figure is a schematic diagram of a control circuit according to an embodiment of the present disclosure.

As shown in fig. 6, the control circuit provided in the embodiment of the present application further includes: an error amplifier EA, a conduction time separator Sep and a charging current control circuit ADJ; the on-time generator 501 includes a first on-time generator TON1 and a second on-time generator TON 2;

two input ends of the error amplifier EA are respectively connected with a preset voltage Vref and an output voltage Vout of the direct-current converter, and are used for outputting an error signal EAO according to the difference value of the Vout and the preset voltage Vref; the preset voltage Vref may be set as needed, for example, the preset voltage Vref in the embodiment of the present application is set according to a load connected to the output terminal of the dc converter provided in the embodiment of the present application. For example, when the load connected to the output terminal of the dc converter requires a supply voltage of 1.2V, the preset voltage Vref is 1.2V.

A on-time separator Sep for outputting a first enable signal TON1_ ST of the first on-time generator TON1 and a second enable signal TON2_ ST of the second on-time generator TON2 according to the error signal EAO;

a charging current control circuit ADJ for comparing the voltages VCF and 1/2VIN across the flying capacitor CF and generating a first charging current IC1 of the first on-time generator TON1 and a second charging current IC2 of the second on-time generator TON2 according to the comparison result; the sum of the first charging current IC1 and the second charging current IC2 is within a preset current range, so that the sum of the first conduction time and the second conduction time is within a preset time range, thereby causing the embodiment of the present application to have less influence on the output voltage Vout when adjusting the first charging current IC1 and the second charging current IC 2.

It should be understood that the sum of the first charging current and the second charging current may have a certain error from the ideal charging current, but the sum of the first charging current and the first charging current should be within a preset current range. The preset current range should include the ideal charging current, and the size of the preset current range can be selected according to the precision of the first charging current and the second charging current. The smaller the preset current range is, the higher the accuracy of the first charging current and the second charging current is. The sum of the first charging current and the second charging current is within a preset time range, that is, the sum of the first charging current and the second charging current does not change greatly in each cycle, and hereinafter, for convenience of description, the sum of the first charging current and the second charging current is simply referred to as the sum of the first charging current and the second charging current is basically constant.

An error amplifier EA in the embodiment of the application outputs an error signal EAO to a conduction time separator Sep; the on-time separator outputs a first enable signal to enable the first on-time generator TON1, and outputs a second enable signal to enable the second on-time generator TON 2; the first on-time generator TON1 outputs a first on-time signal D to the driving circuit 400, and the second on-time generator TON2 outputs a second on-time signal DS to the driving circuit 400; the driving circuit 400 drives the first, second, third and fourth switch groups M1, M2, M3 and M4 to generate a three-level output at the switching point SW; the voltage at the switch point SW is filtered by the inductor LOUT and the capacitor COUT to output the output voltage Vout.

The first on-time signal D provided in the embodiment of the present application indicates a first on-time; the second on-time signal DS indicates a second on-time. As a possible implementation, the time when the first on-time signal D is at the high level is the first on-time, and the time when the second on-time signal DS is at the high level is the second on-time.

The on-time generator provided in the embodiment of the present application includes a first on-time generator TON1 and a second on-time generator TON 2. The internal structure of the first on-time generator TON1 is substantially the same as that of the on-time generator in fig. 4. As shown in fig. 4, the charging current IC1 of the first on-time generator TON1 provided in the embodiment of the present application is equivalent to the charging current I in the above embodiment; the enable signal TON1_ ST of the first on-time generator TON1 provided in the embodiment of the present application is equivalent to the enable signal ST in the above embodiment; the first on-time signal D output by the first on-time generator TON1 provided in the present embodiment is equivalent to the on-time signal TON in the above embodiments.

Accordingly, the second on-time generator TON2 provided in the embodiment of the present application has substantially the same internal structure as the on-time generator in fig. 4. The charging current IC2 of the second on-time generator TON2 provided in the embodiment of the present application is equivalent to the charging current I in the above embodiment; the enable signal TON2_ ST of the second on-time generator TON2 provided in the embodiment of the present application is equivalent to the enable signal ST in the above embodiment; the second on-time signal DS output by the second on-time generator TON2 provided in the present embodiment is equivalent to the on-time signal TON in the above embodiments.

The foregoing mainly describes an on-time separator provided in the present application, and the on-time separator provided in the present application may enable a driving circuit to control four switch sets to change from an off state to an on state through an enable signal.

Referring to fig. 7, the figure is a schematic diagram of a conduction time separator according to an embodiment of the present application.

Referring to fig. 8, a signal waveform diagram of a control circuit according to an embodiment of the present application is shown.

As shown in fig. 7, the on-time separator according to the embodiment of the present invention receives the error signal EAO output from the error amplifier, and outputs the first enable signal TON1_ ST and the second enable signal TON2_ ST according to the error signal EAO. The first enable signal TON1_ ST is used to enable the first on-time generator TON1, and the second enable signal TON2_ ST is used to enable the second on-time generator TON 2.

As shown in fig. 4 and 8, at time t1, the output voltage Vout of the dc converter changes from lower than the preset voltage Vref to higher than the preset voltage Vref, and the error signal EAO output by the error amplifier changes from high to low. At time t2, the output voltage Vout changes from higher than the predetermined voltage Vref to lower than the predetermined voltage Vref, the error signal EAO output by the error amplifier changes from low to high, the second enable signal TON2_ ST output by the on-time separator generates a pulse, and the second on-time signal DS output by the second on-time generator TON2 changes to high. As a possible implementation manner, when the second on-time signal DS is at a high level, the driving circuit controls the second switch group M2 to be turned on, and the third switch group M3 to be turned off.

At time t3, when the output voltage VOT changes from higher than the preset voltage Vref to lower than the preset voltage Vref again, the error signal EAO output by the error amplifier changes from low to high, the first enable signal TON1_ ST output by the on-time separator generates a pulse, and the first on-time signal D output by the first on-time generator TON1 changes to high level. As a possible implementation manner, when the first on-time signal D is at a high level, the driving circuit controls the first switch group M1 to be turned on, and the fourth switch group M4 to be turned off.

Therefore, the on-time separator provided by the embodiment of the application enables the driving circuit to control the four switch groups to be conducted through the enabling signal. Accordingly, the charging current control circuit provided in the embodiment of the present application is mainly used for adjusting the off-time of the four switch sets through the charging current, and the operation principle of the on-time separator provided in the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

Referring to fig. 9, the schematic diagram of a charging current control circuit according to an embodiment of the present disclosure is shown.

As shown in fig. 9, the current IC in the charging current control circuit provided in the embodiment of the present application is the sum of IC1 and IC2, and remains constant. The first output end of the charging current control circuit outputs a first charging current IC1 of 0.5 IC + delta I, and the second output end of the charging current control circuit outputs a second charging current IC2 of 0.5 IC-delta I. That is, in the charging current control circuit provided in the embodiment of the present application, the amount of increase of the first charging current IC1 is equal to the amount of decrease of the second charging current IC2, and the sum of the first charging current IC1 and the second charging current IC2 is equal to the constant current IC, so that the sum of the first on time and the second on time is substantially constant, thereby making the influence on the output voltage Vout when the embodiment of the present application adjusts the voltage VCF across the flying capacitor small. In this embodiment of the present application, the sum of the first on-time and the second on-time is substantially constant, and specifically includes: the first conduction time is changed to a first time, and the second conduction time is changed to the opposite direction to approximate the first time.

For better understanding of the charging current control circuit provided in the embodiments of the present application, a possible implementation of the charging current control circuit provided in the present application is described below with reference to the accompanying drawings.

Referring to fig. 10, a circuit diagram of a charging current control circuit corresponding to the schematic diagram of fig. 9 is shown.

As shown in fig. 10, the charging current control circuit provided in the embodiment of the present application includes: a first PMOS transistor P1 and a second PMOS transistor P2.

The source electrode of the first PMOS tube P1 is connected with a first constant current source IC, and the source electrode of the second PMOS tube P2 is connected with the first constant current source IC; the gate of the first PMOS transistor is connected to 1/2VIN, i.e., 1/2 VIN; the grid electrode of the second PMOS tube is connected with the voltage VCF on the flying capacitor; the drain of the first PMOS transistor is a first output terminal of the charging current control circuit, and outputs a first charging current IC1 to the first on-time generator TON 1; the drain of the second PMOS transistor is a second output terminal of the charging current control circuit, and outputs a second charging current IC2 to the second on-time generator TON 2.

It should be appreciated that when the voltage VCF across the flying capacitor is greater than 1/2VIN, the first charging current IC1 becomes larger, and the voltage VC at the positive input terminal of the comparator AMP in the first on-time generator TON1 rises faster, thereby causing the first on-time to be shorter, which in turn causes the first switch group M1 to be shorter in on-time, i.e., the charging time of the flying capacitor to be shorter. Accordingly, the second charging current IC2 becomes smaller, and the voltage VC at the positive input terminal of the comparator AMP in the second on-time generator TON2 becomes slower to rise, so that the second on-time becomes longer, and further the on-time of the second switch group M2 becomes longer, that is, the discharging time of the flying capacitor becomes longer. The charging time and the discharging time of the flying capacitor become longer, and the voltage across the flying capacitor becomes smaller and equal to 1/2 VIN.

When the voltage VCF on the flying capacitor is less than 1/2VIN, the first charging current IC1 becomes smaller, and the voltage VC at the positive input terminal of the comparator AMP in the first on-time generator TON1 rises slowly, so that the first on-time becomes longer, and further the on-time of the first switch group M1 becomes longer, that is, the charging time of the flying capacitor becomes longer. Accordingly, the second charging current IC2 becomes larger, and the voltage VC at the positive input terminal of the comparator AMP in the second on-time generator TON2 rises faster, so that the second on-time becomes shorter, and the time for which the second switch group M2 is turned on becomes shorter, that is, the discharge time period of the flying capacitor becomes shorter. The charging time and the discharging time of the flying capacitor become short, and the voltage across the flying capacitor becomes large and equal to 1/2 VIN.

And since the sum of the first charging current IC1 and the second charging current IC2 is equal to the constant current IC, and thus the sum of the first on-time and the second on-time is substantially constant, the influence on the output voltage Vout during variations of the first charging current IC1 and the second charging current IC2 is small. In an actual application process, in order to avoid too frequent adjustment of the voltage VCF on the flying capacitor, when a difference between the voltage VCF on the flying capacitor and the power supply voltage VIN is smaller than a preset threshold, the voltage VCF on the flying capacitor may not be adjusted. The voltage VCF on the flying capacitor is adjusted only when the absolute value of the difference between the voltage VCF on the flying capacitor and the power supply voltage VIN is greater than a preset threshold.

To sum up, the signal separator of the dc converter provided in the embodiment of the present application is connected to the error signal output by the error amplifier, and directly converts the error signal into the first enable signal and the second enable signal, and outputs the first enable signal and the second enable signal to the first on-time generator and the second on-time generator, so as to generate the first on-time and the second on-time to control the four switch sets, and further maintain the voltage on the flying capacitor at half of the power supply voltage. Therefore, the voltage of the switching point of the direct current converter provided by the embodiment of the application is stable, the ripple current of the inductor is reduced, and the extra loss caused by the ripple current is reduced.

The embodiment described above is implemented by using a dual on-time generator, and the on-time generator provided in the embodiment of the present application may also output one on-time signal to control four switch groups. Since the dual on-time generator includes two on-time generators, the duty cycle of the four switch sets may be greater than 50% for the dual on-time generator scheme. For a single on-time generator, because there is only one on-time generator, the duty ratios of the four switch groups only reach 50% at most, that is, the duty ratios are less than or equal to 50% and not more than 50%. For example, for a scheme with a duty ratio greater than 50%, when the dc converter is used as a buck converter, an output voltage greater than half of the input voltage can be achieved, for example, the input voltage is 12V, and an output voltage greater than 6V can be achieved. However, for the scheme with the duty ratio less than 50%, when the direct current converter is used as a buck converter, the output voltage is less than or equal to 6V.

Referring to fig. 11, the diagram is a schematic diagram of a dc converter according to an embodiment of the present application.

As shown in fig. 11, a control circuit 500 of a dc converter provided in an embodiment of the present application includes: an error amplifier EA, a pulse generator OS, a conduction time generator TON, a conduction time separator Sep and a charging current control circuit ADJ.

The first input end of the error amplifier EA is connected with a preset voltage Vref of the direct-current converter; a second input end of the error amplifier EA is connected with the output voltage Vout of the direct current converter; the output end of the error amplifier EA outputs an error signal EAO to the pulse generator OS; the pulse generator OS outputs an enable signal TON _ ST to the on-time generator TON according to the error signal EAO. A first input end of the charging current control circuit ADJ is connected with the voltage VCF on the flying capacitor CF, and a second input end of the charging current control circuit ADJ is connected with a half of the power voltage VIN, namely 1/2 VIN; a third input end of the charging current control circuit ADJ is connected with a first switching signal QD output by a D trigger in the conduction time separator; a fourth input end of the charging current control circuit ADJ is connected with a second switching signal QDS output by a D trigger in the conduction time separator; the output terminal of the charging current control circuit ADJ outputs a charging current IC to the on-time generator.

The on-time generator TON outputs an on-time signal TON to the on-time separator Sep according to the enable signal TON _ ST and the charging current IC; the on-time separator Sep outputs a first on-time signal D and a second on-time signal DS to the driving circuit 400 according to the on-time signal TON to control the on-off states of the four switch groups M1-M4, so as to adjust the charge-discharge state of the flying capacitor CF, and thus the voltage VCF on the flying capacitor CF is consistent with 1/2 VIN. The on-time signal TON indicates the on-time of the four switch groups M1-M4, the first on-time signal D indicates the first on-time of the first switch group M1, and the second on-time signal DS indicates the second on-time of the second switch group M2.

The function of the on-time generator TON in the embodiment of the present application is substantially the same as that of the on-time generator TON in the above-mentioned embodiment, and the details thereof are not repeated herein.

A conduction time separator Sep for separating a first conduction time and a second conduction time according to the conduction time output by the conduction time generator TON to the driving circuit 400, wherein the first conduction time signal D corresponds to the first switch group M1, and the second conduction time signal DS corresponds to the second switch group M2; in the continuous conduction mode, the switch state M4 of the fourth switch group is complementary to the switch state of the first switch group M1; the switching states of the third switch group M3 are complementary to the switching states of the second switch group M2. The sum of the first conduction time and the second conduction time is within a preset time range so as to inhibit the fluctuation of the output voltage Vout of the direct current converter. The sum of the first on-time and the second on-time does not change much in each period, and hereinafter, for convenience of description, the sum of the first on-time and the second on-time is simply referred to as being substantially constant.

And the error amplifier EA is used for outputting an error signal EAO according to the difference value of the voltage VCF on the flying capacitor CF and the preset voltage Vref.

And the charging current control circuit ADJ is used for comparing the voltage VCF on the flying capacitor CF with a half of the power supply voltage VIN and generating a charging current IC of the on-time generator TON according to a comparison result and two complementary signals (QD and QDS) output by a D trigger in the on-time separator Sep.

The pulse generator in the embodiment of the present application can be implemented by various circuits, and an implementation manner of the pulse generator OS provided in the embodiment of the present application is described below with reference to the drawings.

Referring to fig. 12, a circuit diagram of a pulse generator according to an embodiment of the present application is shown.

As shown in fig. 12, an input terminal of the pulse generator according to the embodiment of the present invention is connected to an error signal EAO output by an error amplifier EA, and outputs an enable signal TON _ ST to the on-time generator TON according to the error signal EAO. The pulse generator OS is configured to generate an enable signal TON _ ST according to the error signal EAO, and enable the on-time generator TON.

The on-time separator in the embodiment of the present application will be described below.

Referring to fig. 13, a circuit diagram of a conduction time separator according to an embodiment of the present application is shown.

As shown in fig. 13, the on-time separator provided in the embodiment of the present application includes: d flip-flop 600. A first output terminal of the D flip-flop 600 outputs a first switching signal QD to the charging current control circuit ADJ, and a second output terminal of the D flip-flop 600 outputs a second switching signal QDs to the charging current control circuit ADJ. The first switching signal QD is complementary to the second switching signal. That is, when the first switching signal QD is at a high level, the second switching signal QDs is at a low level; when the first switching signal QD is at a low level, the second switching signal QDs is at a high level.

The on-time separator provided in the embodiment of the present application further separates the first on-time signal D and the second on-time signal DS according to the on-time signal TON output by the on-time generator TON. The first on-time signal D is used to control the on/off of the first switch group M1, and the second on-time signal DS is used to control the on/off of the second switch group M2. The period of the on-time signal is T, the waveform of the on-time signal TON in the first period T1 is the same as the waveform of the first on-time signal D in the first period T1, and the waveform of the on-time signal TON in the second period T2 is the same as the waveform of the second on-time signal DS in the second period T2. The first on time plus the second on time equals the on time.

For example, as shown in the waveform in the on-time separation Sep in fig. 11, the waveform of the on-time signal TON in the first period T1 is TON1, and the waveform of the on-time signal TON in the second period T2 is TON 2. The waveform of the first on-time signal D in the first period T1 is Ton1, which is the same as the waveform of the on-time signal Ton in the first period T1, and the waveform of the second on-time signal DS in the second period T2 is Ton2, which is the same as the waveform of the on-time signal Ton in the second period T2.

It should be noted that the period of the on-time signal TON, the period of the first on-time signal D, and the period of the second on-time signal DS may be T, and as another possible implementation, the period of the on-time signal TON, the period of the first on-time signal D, and the period of the second on-time signal DS may also be 2T. When the period of the on-time signal TON, the period of the first on-time signal D, and the period of the second on-time signal DS are 2T, to avoid the overlapping of the waveforms of the on-time signal TON, the duty ratios of the first on-time signal D and the second on-time signal DS are less than 50%.

The charging current control circuit in the embodiment of the present application will be described below.

Referring to fig. 14, the schematic diagram of a charging current control circuit according to an embodiment of the present disclosure is shown.

As shown in fig. 14, the first charging current IQD and the second charging current IQDs are respectively combined into a charging current IC under the control of the first current switch QD and the second current switch QDs, and the charging current IC is output to the on-time generator TON. The first current switch QD is controlled by a first switching signal QD output by the on-time separator Sep, and the second current switch QD is controlled by a second switching signal QDs output by the on-time separator Sep. Therefore, the charging current IC is equal to the first charging current IQD during the first period T1 and equal to the second charging current IQDs during the second period T2.

The first current switch QD and the second current switch QDs have opposite switching states, i.e. are complementary, and when QD is on, QDs is off, whereas when QD is off, QDs is on.

After the charging current IC is synthesized by the first charging current IQD and the second charging current IQDs provided in the embodiment of the present application, the charging current IC is output to the on-time generator TON, the on-time generator TON generates the on-time signal TON according to the charging current IC, and the on-time separator Sep separates the on-time signal TON into the first on-time signal D and the second on-time signal DS.

It should be understood that the process of combining the first charging current IQD and the second charging current IQDs into the charging current IC and the process of separating the first on-time signal D and the second on-time signal DS from the on-time signal TON are two processes corresponding to the processes provided in the embodiments of the present application. That is, in the embodiment of the present application, when the on-time signal TON is generated according to the charging current IC, it is equivalent to generate the first on-time signal D according to the first charging current IQD in the first period T1, and generate the second on-time signal DS according to the second charging current IQDs in the second period T2. That is, the first charging current IQD corresponds to the first on-time signal D, and the second charging current IQDs corresponds to the second on-time signal DS.

The current 2 × Ich in the charging current control circuit provided in the embodiment of the present application is the sum of the first charging current IQD and the second charging current IQDs, and 2 × Ich remains fixed. The first charging current IQD in the first branch of the charging current control circuit is Ich + Δ I, and the second charging current IQDs in the second branch of the charging current control circuit is Ich- Δ I. That is, in the charging current control circuit provided in the embodiment of the present application, the increase Δ I of the first charging current IQD is equal to the decrease Δ I of the second charging current IQDs, and the sum of the first charging current IQD and the second charging current IQDs is equal to the constant current 2 × Ich, so that the sum of the first on-time and the second on-time is substantially constant, and the influence on the output voltage Vout when the voltage VCF on the flying capacitor is adjusted in the embodiment of the present application is small. As a possible implementation manner, the sum of the first on-time and the second on-time in the embodiment of the present application is substantially constant, and specifically includes: the on-time of the first switch group is changed by a first time, and the on-time of the second switch group is changed to the opposite direction to approximate the first time. The two current branches in fig. 14 are alternately conducting, and only the current of one branch is output to the IC at the same time.

Fig. 14 is a schematic diagram of a charging current control circuit corresponding to a single on-time generator, and in order to better understand the charging current control circuit provided in the embodiment of the present application, a possible implementation of the charging current control circuit provided in the present application is described below with reference to the accompanying drawings, it should be understood that a circuit implementing the operation principle of fig. 14 may include a variety of specific topologies, and only one specific implementation of which is described below with reference to fig. 15.

Referring to fig. 15, there is shown a circuit diagram of a charge current control circuit corresponding to the schematic diagram of fig. 14.

As shown in fig. 15, the charging current control circuit provided in the embodiment of the present application includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a first switch transistor N1 and a second switch transistor N2. In this embodiment, the first switch tube and the second switch tube are both NMOS tubes for example. In addition, the first switch tube and the second switch tube may also be PMOS tubes, and when the first switch tube and the second switch tube are both PMOS tubes, the control signals are slightly different from those of the NMOS tubes, which is not described in detail in this embodiment.

The source electrode of the third PMOS transistor P3 and the source electrode of the fourth PMOS transistor P4 are both connected to the second constant current source 2 × Ich, the gate electrode of the third PMOS transistor P3 is connected to half of the power supply voltage VIN, and the gate electrode of the fourth PMOS transistor P4 is connected to the voltage VCF on the flying capacitor CF.

The drain of the third PMOS transistor P3 is connected to the first end of the first switch transistor N1, the drain of the fourth PMOS transistor P4 is connected to the first end of the second switch transistor N2, and the second end of the first switch transistor N1 and the second end of the second switch transistor N2 are connected together to output the charging current IC. A first output terminal of the D flip-flop 600 is connected to the control terminal of the first switch transistor N1, and a second output terminal of the D flip-flop 600 is connected to the control terminal of the second switch transistor.

When the first switching tube and the second switching tube are both NMOS tubes, the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the first switching tube N1, the drain electrode of the fourth PMOS tube P4 is connected with the drain electrode of the second switching tube N2, and the source electrode of the first switching tube N1 and the source electrode of the second switching tube N2 are connected together to output a charging current IC; a first output terminal of the D flip-flop 600 is connected to the gate of the first switching transistor N1, and a second output terminal of the D flip-flop 600 is connected to the gate of the second switching transistor.

In order to enable the circuit to operate more stably, as shown in fig. 15, as a possible implementation manner, the charging current control circuit provided in the embodiment of the present application may further include: a third switch tube N3 and a fourth switch tube N4. The first end of the third switch tube N3 is connected to the first end of the first switch tube N1, and the first end of the fourth switch tube N4 is connected to the first end of the second switch tube N2. The control end of the third switch tube N3 is connected with QDS. The control end of the fourth switching tube N4 is connected with the QD. The second terminal of the third switch transistor N3 is grounded, and the second terminal of the fourth switch transistor N4 is grounded.

Since QDS and QD are two complementary control signals, when the third switch N3 is turned on, the first switch N1 is turned off; when the first switch tube N1 is turned on, the third switch tube N3 is turned off. Similarly, when the fourth switch tube N4 is turned on, the second switch tube N2 is turned off; when the second switch tube N2 is turned on, the fourth switch tube N4 is turned off. In order to better understand the scheme provided by the embodiment of the present application, the control circuit of the embodiment of the present application is described below with reference to a signal waveform diagram of the control circuit provided by the embodiment of the present application.

Referring to fig. 16, a signal waveform diagram of a control circuit according to an embodiment of the present application is shown.

As can also be seen from the timing diagram shown in fig. 16, the driving signals controlling the two switches QD and QDs in fig. 14 are complementary, and thus, the switching states of the two switches QD and QDs can be made complementary.

At time t1, the output voltage Vout of the dc converter changes from higher than the preset voltage Vref to lower than the preset voltage Vref, the error signal EAO output by the error amplifier changes from low level to high level, the enable signal TON _ ST output by the pulse generator OS generates a pulse, the on-time signal TON output by the on-time generator TON changes from low level to high level, the first switching signal QD received by the charging current control circuit changes from low level to high level, and the first on-time signal D output by the on-time separator Sep changes from low level to high level.

At time t2, the on-time signal TON output by the on-time generator TON changes from high level to low level, and the first on-time signal D output by the on-time separator Sep changes from high level to low level.

At time t3, the output voltage of the dc converter changes from higher than the preset voltage Vref to lower than the preset voltage Vref again, the error signal EAO output by the error amplifier changes from low level to high level, the enable signal TON _ ST output by the pulse generator OS generates a pulse, the on-time signal TON output by the on-time generator TON changes from low level to high level, the first switching signal QD received by the charging current control circuit changes from high level to low level, the second switching signal QDs received by the charging current control circuit changes from low level to high level, and the second on-time signal DS output by the on-time separator Sep changes from low level to high level.

At time t4, the on-time signal TON output by the on-time generator TON changes from high level to low level, and the first on-time signal D output by the on-time separator Sep changes from high level to low level.

Comparing fig. 16 and 8, it can be seen that the duty cycle of D and DS in fig. 16 is less than 50%, and the duty cycle of D and DS in fig. 8 is greater than 50%, which also confirms the difference between the scheme of the dual on-time generator and the scheme of the single on-time generator.

To sum up, the conduction time generator of the dc converter provided in the embodiment of the present application is connected to the error amplifier through the pulse generator, the conduction time generator directly generates a comprehensive conduction time according to a signal output by the pulse generator, and outputs the comprehensive conduction time to the conduction time separator, and the conduction time separator separates the first conduction time and the second conduction time according to the comprehensive conduction time to control the four switch sets, so as to maintain the voltage on the flying capacitor at half of the power supply voltage. Therefore, the voltage of the switching point of the direct current converter provided by the embodiment of the application is stable, the ripple current of the inductor is reduced, and the extra loss caused by the ripple current is reduced.

According to the dc converter provided in the above embodiments, a power supply system is further provided in the embodiments of the present application, and the power supply system provided in the embodiments of the present application will be described below with reference to the accompanying drawings.

Referring to fig. 17, the figure is a schematic diagram of a power supply system according to an embodiment of the present application.

As shown in fig. 17, the power supply system provided in the embodiment of the present application includes: the dc converter 900, the rectifier 700 and the buck converter 800 are as described in the previous embodiments.

Wherein, the input end of the rectifier 700 is used for connecting an ac power supply, such as a 220V ac mains; the output of the rectifier 700 is connected to the input of the buck converter 800; the output end of the buck converter 800 is connected with the input end of the dc converter 900; the output of the dc converter 900 is used to connect a load. The buck converter 800 in this embodiment serves as a first stage buck converter, and the dc converter 900 serves as a second stage buck converter.

In addition, the buck converter 800 in the present embodiment can also be implemented by using the dc converter 900 described in the above embodiments.

The power supply system provided by the embodiment of the application comprises the direct current converter provided by the embodiment, and because the voltage on the flying capacitor of the direct current converter is maintained at half of the power supply voltage, the voltage of the switching point of the direct current converter is relatively stable, the ripple current of the inductor in the power supply system is relatively small, and thus the extra loss in the power supply system is relatively small.

Further, since the sum of the first on-time and the second on-time in the dc converter is a substantially fixed value, the solution of the embodiment of the present application has less influence on the output voltage of the dc converter when adjusting the voltage on the flying capacitor. The output voltage of the power supply system provided by the embodiment of the application is equivalent to the output voltage of the direct current converter, so that the influence on the output voltage of the power supply system is small when the ripple current on the inductor is reduced by the scheme provided by the embodiment of the application.

The buck converter 800 provided in the embodiment of the present application is configured to receive the output voltage of the rectifier 700, and output the output voltage to the dc converter 900 after being stepped down, which may be implemented by an open-loop buck converter. The dc converter 900 is configured to receive the output voltage of the buck converter 800, and output the output voltage to a load such as a chip after being stepped down, and may be implemented by a closed-loop control buck converter. The voltage output by the dc converter 900 is used to power a load. Because the dc converter 900 can implement closed-loop control, the dc converter 900 has both the voltage-reducing function and the voltage-stabilizing function, and the output voltage is stable and controllable.

As a possible implementation manner, the rectifier 700 provided in this embodiment of the present application is used to convert 220V ac power into 48V dc power, the buck converter 800 is used to convert 48V dc power into 12V dc power, and the dc converter 900 is used to further buck 12V dc power, for example, the dc power can be stepped down to 5V, 3.3V, or 1.2V to supply power to a load such as a chip.

It should be understood that the buck converter 800 provided by the embodiment of the present application is only used to reduce the input voltage of 48V to 12V, and the output voltage thereof is not directly supplied to the chip or other loads, but is further stepped down and stabilized by the dc converter 900. The voltage output by the dc converter 900 is more stable and accurate, so that the power supply requirements of loads such as chips can be met.

The 12V output by the buck converter 800 provided by the embodiment of the present application can be controlled in an open loop manner, and the output voltage is allowed to fluctuate within a certain range as long as the input voltage range of the dc converter 900 is satisfied. Thus, the buck converter 800 for the first stage buck can be designed as an open loop buck converter.

Accordingly, the output voltage of the dc converter 900 provided by the embodiment of the present application must meet the power supply requirement of the chip or other loads, provide a more accurate and stable output voltage, and for the output voltage to be more stable and accurate, the voltage at the output end thereof can be detected and fed back to the input end thereof for negative feedback closed-loop control. That is, the dc converter 900 provided in the embodiment of the present application can perform closed-loop control, so that the voltage at the output terminal thereof is more stable. Therefore, the dc converter 900 with the second step down can be designed as a closed loop converter.

According to the direct current converter and the power supply system provided by the above embodiments, embodiments of the present application further provide a driving chip, and the driving chip provided by the embodiments of the present application will be described below with reference to the accompanying drawings.

Referring to fig. 18, the figure is a schematic diagram of a driving chip provided in an embodiment of the present application.

As shown in fig. 18, the driving chip provided in the embodiment of the present application includes: a driving circuit 400 and a control circuit 500 for driving a three-level dc converter, the three-level dc converter including a flying capacitor and a plurality of switch groups; the control circuit 500 includes at least an on-time generator 501; an on-time generator 501 for adjusting an output on-time signal by changing a charging current of a capacitor of the on-time generator 501 when a voltage on the flying capacitor deviates from a half of a power supply voltage, the on-time signal being output to the driving circuit 400; and a driving circuit 400 configured to generate a driving pulse signal according to the on-time signal to drive the switching states of the plurality of switch groups to adjust the charging and discharging time of the flying capacitor, so that the voltage on the flying capacitor is equal to half of the power supply voltage.

As a possible embodiment, the plurality of switch groups includes: a first switch group, a second switch group, a third switch group and a fourth switch group; the conduction time generator is used for outputting a first conduction time signal to the first switch group and outputting a second conduction time signal to the second switch group; the switch state of the fourth switch group is complementary to the switch state of the first switch group; the switch state of the third switch set is complementary to the switch state of the second switch set; the sum of the first conducting time and the second conducting time in each switching period of the four switching groups is within a preset time range.

As a possible implementation, the control circuit further includes: an error amplifier, a conduction time separator and a charging current control circuit; the conduction time generator control circuit comprises a first conduction time generator and a second conduction time generator; the two input ends of the error amplifier are respectively connected with the output voltage of the direct current converter and a preset voltage and used for outputting an error signal according to the difference value of the output voltage of the direct current converter and the preset voltage; a turn-on time separator for outputting a first enable signal of the first turn-on time generator and a second enable signal of the second turn-on time generator according to the error signal; the charging current control circuit is used for comparing the voltage on the flying capacitor with a half of the power supply voltage and generating a first charging current of the first conduction time generator and a second charging current of the second conduction time generator according to a comparison result; the sum of the first charging current and the second charging current is within a preset current range.

As a possible implementation, the control circuit further includes: an on-time separator; the conduction time separator is used for separating a first conduction time signal and a second conduction time signal according to the conduction time signal output by the conduction time generator and sending the first conduction time signal and the second conduction time signal to the driving circuit, the first conduction time signal corresponds to the first switch group, and the second conduction time signal corresponds to the second switch group; in the continuous conduction mode, the switch state of the fourth switch group is complementary with the switch state of the first switch group, and the switch state of the third switch group is complementary with the switch state of the second switch group; the sum of the conducting time of the first switch group and the conducting time of the second switch group in each switching period of the four switch groups is within a preset time range.

As a possible implementation, the control circuit further includes: an error amplifier and a charging current control circuit; two input ends of the error amplifier are respectively connected with the output voltage of the direct current converter and a preset voltage and used for outputting an error signal according to the difference value of the voltage on the flying capacitor and the preset voltage; and the charging current control circuit is used for comparing the voltage on the flying capacitor with a half of the power supply voltage and generating the charging current of the conduction time generator according to the comparison result and two complementary signals output by the D trigger in the conduction time separator.

Therefore, the driving chip provided by the embodiment of the application can adjust the magnitude of the charging current in the on-time generator according to the voltage on the flying capacitor and half of the power supply voltage, so as to adjust the on-time output by the on-time generator. And controlling the on-time of the four switch groups, namely controlling the on-off time of the four switch groups, namely controlling the charging time of the flying capacitor and the discharging time of the flying capacitor, according to the on-time output by the on-time generator, so as to influence the voltage on the flying capacitor, and further maintain the voltage on the flying capacitor at half of the power supply voltage. Therefore, the voltage of the switching point of the direct current converter provided by the embodiment of the application is stable, the ripple current of the inductor is reduced, and the extra loss caused by the ripple current is reduced.

It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.

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Three-level direct current converter, power supply system and chip

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