阅读说明：本技术 一种模数转换器及其校准方法 (Analog-to-digital converter and calibration method thereof ) 是由 许�鹏 于 2020-06-03 设计创作，主要内容包括：本发明公开了一种模数转换器及其校准方法,该校准方法通过第一校准过程得到第一校准值,通过第二校准过程得到第二校准值,然后根据第一校准值和第二校准值确定校准电容阵列的校准参数,第一校准过程和第二校准过程都需要在电荷采样阶段和电荷保持阶段切换高位电容阵列的最低位电容和低位电容阵列的全部电容所接的电位,区别在于第一校准过程和第二校准过程的电位切换方向是相反的,通过相反的电位切换,使得到的校准参数不受比较器的输入失调电压的影响,从而可以在校准过程中有效消除校准过程中比较器的输入失调电压的影响,提高校准的准确度。(The invention discloses an analog-digital converter and a calibration method thereof, the calibration method obtains a first calibration value through a first calibration process, obtains a second calibration value through a second calibration process, and then determines a calibration parameter of a calibration capacitor array according to the first calibration value and the second calibration value, the first calibration process and the second calibration process both need to switch the lowest level capacitor of a high level capacitor array and the potential connected with all capacitors of the low level capacitor array in a charge sampling stage and a charge holding stage, the difference lies in that the potential switching directions of the first calibration process and the second calibration process are opposite, and the obtained calibration parameter is not influenced by the input offset voltage of a comparator through opposite potential switching, so that the influence of the input offset voltage of the comparator in the calibration process can be effectively eliminated in the calibration process, and the calibration accuracy is improved.)

1. A calibration method of an analog-to-digital converter, the analog-to-digital converter comprising a low-order capacitor array composed of 1 st to m-th capacitors and auxiliary capacitors, a high-order capacitor array composed of m +1 st to n-th capacitors, a bridge capacitor, a calibration capacitor array, and a comparator, a first end of the calibration capacitor array, a first end of each capacitor in the low-order capacitor array, and a first end of the bridge capacitor are connected, a first end of each capacitor in the high-order capacitor array is connected with a second end of the bridge capacitor, m and n are integers greater than or equal to 1, and the comparator is configured to compare a holding voltage at the second end of the bridge capacitor with a preset common mode voltage, wherein the calibration method comprises:

providing an initial digital signal to the calibration capacitor array, the equivalent output capacitance of the calibration capacitor array being controlled by the digital signal;

changing the digital signal to change the equivalent output capacitance of the calibration capacitor array, executing a first voltage switching so that the comparator outputs a change, and determining a first calibration value of the digital signal based on the change of the comparator output;

changing the digital signal such that an equivalent output capacitance of the calibration capacitance array changes, performing a second voltage inversion such that the comparator output changes, and determining a second calibration value for the digital signal based on the change in the comparator output;

determining calibration parameters to provide to the calibration capacitive array for calibration based on the first calibration value and the second calibration value of the digital signal,

wherein the first voltage switching comprises: connecting the second terminal of the (m + 1) th capacitor to a ground reference voltage in a charge sampling phase, connecting the second terminals of the (1) th to (m) th capacitors and the auxiliary capacitor to a reference voltage, connecting the second terminal of the (m + 1) th capacitor to a reference voltage in a charge holding phase, and connecting the second terminals of the (1) th to (m) th capacitors and the auxiliary capacitor to a ground reference voltage,

the second voltage switching comprises: and in the charge sampling stage, connecting the second end of the (m + 1) th capacitor with a reference voltage, connecting the second ends of the (1) th to (m) th capacitors and the auxiliary capacitor with a reference ground voltage, and in the charge holding stage, connecting the second ends of the (m + 1) th capacitors with the reference ground voltage, and connecting the second ends of the (1) th to (m) th capacitors and the auxiliary capacitor with the reference voltage.

2. The calibration method according to claim 1, wherein the calibration capacitor array is composed of 1 st to q th calibration capacitors, a first terminal of each calibration capacitor is connected to a first terminal of the calibration capacitor array, a second terminal of each calibration capacitor receives the reference ground voltage or floats according to the digital signal, the digital signal includes a binary number of q bits corresponding to the 1 st to q th calibration capacitors in a one-to-one manner, and q is an integer greater than or equal to 1.

3. The calibration method according to claim 2, wherein in a case where an ith bit of the digital signal is 1, a second terminal of an ith calibration capacitor of the calibration capacitor array is connected to a reference ground voltage,

and under the condition that the ith bit of the digital signal is 0, suspending a second end of the ith calibration capacitor of the calibration capacitor array, wherein i is an integer which is more than or equal to 1 and less than or equal to q.

4. The calibration method according to claim 3, wherein the capacitance values of the 1 st to the qth calibration capacitors in the calibration capacitor array are sequentially increased in a twofold relationship, and the 1 st to the qth bits of the initial digital signal are 0.

5. The calibration method of claim 4, wherein the changing the digital signal such that the equivalent output capacitance of the calibration capacitance array changes, performing a first voltage switch such that the comparator output changes, and determining a first calibration value for the digital signal based on the change in the comparator output comprises:

selecting the most significant bit of the unselected data bits in the digital signal to become 1;

executing the first voltage switching;

obtaining the output of the comparator, and changing the selected highest bit to 0 if the output of the comparator represents that the holding voltage at the second end of the bridging capacitor is greater than or equal to the common-mode voltage;

and jumping to a step of selecting the highest bit of the unselected data bits in the digital signal to be 1 until the unselected data bits do not exist in the digital signal, and outputting the digital signal at the moment as the first calibration value.

6. The calibration method of claim 4, wherein the altering the digital signal such that the equivalent output capacitance of the calibration capacitance array changes, performing a second voltage switch such that the comparator output changes, and determining a second calibration value for the digital signal based on the change in the comparator output comprises:

selecting the most significant bit of the unselected data bits in the digital signal to become 1;

executing the second voltage switching;

obtaining the output of the comparator, and changing the selected highest bit to 0 if the output of the comparator represents that the holding voltage at the second end of the bridging capacitor is less than or equal to the common-mode voltage;

skipping to the step of selecting the most significant bit of the unselected data bit in the digital signal to be 1 until there is no unselected data bit in the digital signal, and outputting the digital signal at this time as the second calibration value.

7. The calibration method according to claim 5 or 6, wherein the holding voltage at the second terminal of the bridge capacitor is equal to or approximately equal to the preset common mode voltage in case there are no unselected data bits in the digital signal.

8. The calibration method according to claim 3, wherein the capacitance values of the 1 st to the qth calibration capacitors in the calibration capacitor array are equal, and the 1 st to the qth bits of the initial digital signal are 0.

9. The calibration method of claim 7, wherein the changing the digital signal such that the equivalent output capacitance of the calibration capacitor array changes, performing a first voltage switch such that the comparator output changes, and determining a first calibration value for the digital signal based on the change in the comparator output comprises:

selecting one unselected data bit from the digital signal to become 1; executing the first voltage switching; obtaining the output of the comparator, and if the output of the comparator indicates that the holding voltage at the second end of the bridge capacitor is smaller than the common-mode voltage, repeating the step until the output of the comparator indicates that the holding voltage at the second end of the bridge capacitor is larger than or equal to the common-mode voltage;

outputting the digital signal with the hold voltage at the second end of the bridge capacitance being greater than or equal to the common mode voltage as the first calibration value.

10. The calibration method of claim 7, wherein the altering the digital signal such that the equivalent output capacitance of the calibration capacitance array changes, performing a second voltage switch such that the comparator output changes, and determining a second calibration value for the digital signal based on the change in the comparator output comprises:

selecting one unselected data bit from the digital signal to become 1; executing the second voltage switching; obtaining the output of the comparator, and if the output of the comparator indicates that the holding voltage at the second end of the bridge capacitor is greater than the common-mode voltage, repeating the step until the output of the comparator indicates that the holding voltage at the second end of the bridge capacitor is less than or equal to the common-mode voltage;

outputting a digital signal with a holding voltage at a second end of the bridge capacitance equal to or less than the common mode voltage as the second calibration value.

11. The calibration method of claim 1, wherein the first voltage switch and the second voltage switch each further comprise:

connecting the second end of the bridging capacitor with the preset common mode voltage for charge sampling, and disconnecting the second end of the bridging capacitor from the preset common mode voltage for charge holding.

12. The calibration method of claim 1, wherein determining calibration parameters to provide to the calibration capacitive array for calibration based on the first calibration value and the second calibration value of the digital signal comprises:

the determining of the calibration parameter provided to the calibration capacitive array is based on an average of the first calibration value and the second calibration value of the digital signal.

13. An analog-to-digital converter, comprising:

a low-order capacitor array including 1 st to mth capacitors and an auxiliary capacitor, first ends of the 1 st to mth capacitors and the auxiliary capacitor being connected to each other;

the high-order capacitor array comprises m +1 th to nth capacitors, and first ends of the m +1 th to nth capacitors are connected with each other;

a bridge capacitor, a first end of which is connected with the first ends of the 1 st to mth capacitors, a second end of which is connected with the first ends of the m +1 th to nth capacitors, and m and n are integers more than or equal to 1;

the calibration capacitor array comprises 1 st to q th calibration capacitors, and first ends of the 1 st to q th calibration capacitors are connected with a first end of each capacitor in the low-order capacitor array and a first end of the bridging capacitor;

a first input end of the comparator is connected with a second end of the bridging capacitor, and a second input end of the comparator is used for receiving a preset common mode voltage; and

the control circuit is used for determining the equivalent output capacitance of the calibration capacitor array in the analog-to-digital conversion process according to the calibration parameters of the calibration capacitor array in the analog-to-digital conversion process and controlling the connection potential of the second end switches of the high-order capacitor array and the low-order capacitor array in the analog-to-digital conversion process,

wherein the control circuit performs the calibration method of any one of claims 1-12 in a calibration process prior to the analog-to-digital conversion process to determine the calibration parameter.

Technical Field

The present invention relates to the field of semiconductor integrated circuit technology, and more particularly, to an analog-to-digital converter and a calibration method thereof.

Background

Analog-to-Digital Converter (ADC) is a device capable of converting continuous Analog signals into discrete Digital signals that can be processed by a computer, is a key component of an interface between an Analog system and a Digital system, and has been widely used in the fields of radar, communication, measurement and control, medical treatment, instruments, images, audio, and the like for a long time. The rapid development of digital signal processing technology and communication industry has pushed the development of ADCs gradually towards high speed, high precision and low power consumption.

A Successive Approximation Analog-to-Digital Converter (SAR ADC) is an ADC that uses a binary search method to continuously generate a new Analog voltage to approximate to an originally input Analog signal through an internally integrated Digital-to-Analog Converter (DAC) array, and finally uses a Digital input corresponding to a DAC as an output of the ADC. Compared with other types of ADCs, the SAR ADC has the advantages of medium speed, medium precision, low power consumption, low cost and the like, so that the SAR ADC has a wide application field.

The SAR ADC is mainly composed of a DAC array, a successive approximation control logic and a latching comparator. According to different structures of DAC arrays inside the SAR ADC, the SAR ADC can be divided into a resistance voltage division type, a current superposition type, a charge redistribution type and the like. Among them, the most common structure is a charge redistribution ADC, which does not need to design an additional holding circuit since charges can be directly stored in a capacitor array. In addition, the capacitor array DAC has no static power consumption, and compared with a resistor voltage division type DAC and a current superposition type DAC, the power consumption is saved. Meanwhile, in the modern CMOS process, the matching precision of the metal capacitor is much higher than that of a resistor and a transistor, and higher precision can be achieved easily.

However, the capacitor array SAR ADC has the problem that the performance of the ADC is reduced due to capacitor mismatch caused by the production process.

Disclosure of Invention

In view of the above, an object of the present invention is to provide an analog-to-digital converter and a calibration method thereof, which can improve the calibration accuracy of the analog-to-digital converter.

According to an aspect of the embodiments of the present invention, there is provided a calibration method of an analog-to-digital converter, the analog-to-digital converter including a lower capacitor array including 1 st to m-th capacitors and auxiliary capacitors, an upper capacitor array including m +1 st to n-th capacitors, a bridge capacitor, a calibration capacitor array, and a comparator, a first end of the calibration capacitor array, a first end of each capacitor in the lower capacitor array, and a first end of the bridge capacitor are connected, a first end of each capacitor in the upper capacitor array is connected to a second end of the bridge capacitor, m and n are integers greater than or equal to 1, and the comparator is configured to compare a holding voltage at the second end of the bridge capacitor with a preset common mode voltage, wherein the calibration method includes: providing an initial digital signal to the calibration capacitor array, the equivalent output capacitance of the calibration capacitor array being controlled by the digital signal; changing the digital signal to change the equivalent output capacitance of the calibration capacitor array, executing a first voltage switching so that the comparator outputs a change, and determining a first calibration value of the digital signal based on the change of the comparator output; changing the digital signal such that an equivalent output capacitance of the calibration capacitance array changes, performing a second voltage inversion such that the comparator output changes, and determining a second calibration value for the digital signal based on the change in the comparator output; determining a calibration parameter to provide to the calibration capacitive array for calibration based on a first calibration value and a second calibration value of the digital signal, wherein the first voltage switching comprises: in a charge sampling phase, connecting a second terminal of an m +1 th capacitor to a reference ground voltage, connecting second terminals of the 1 st to m th capacitors and the auxiliary capacitor to the reference voltage, and in a charge holding phase, connecting a second terminal of the m +1 th capacitor to the reference voltage, and connecting second terminals of the 1 st to m th capacitors and the auxiliary capacitor to the reference ground voltage, wherein the second voltage switching comprises: and in the charge sampling stage, connecting the second end of the (m + 1) th capacitor with a reference voltage, connecting the second ends of the (1) th to (m) th capacitors and the auxiliary capacitor with a reference ground voltage, and in the charge holding stage, connecting the second ends of the (m + 1) th capacitors with the reference ground voltage, and connecting the second ends of the (1) th to (m) th capacitors and the auxiliary capacitor with the reference voltage.

Preferably, the calibration capacitor array is composed of 1 st to q th calibration capacitors, a first end of each calibration capacitor is connected to the first end of the calibration capacitor array, a second end of each calibration capacitor receives the reference ground voltage or is suspended according to the digital signal, the digital signal includes q-bit binary numbers corresponding to the 1 st to q th calibration capacitors one to one, and q is an integer greater than or equal to 1.

Preferably, when the ith bit of the digital signal is 1, the second terminal of the ith calibration capacitor of the calibration capacitor array is connected to a reference ground voltage, and when the ith bit of the digital signal is 0, the second terminal of the ith calibration capacitor of the calibration capacitor array is suspended, where i is an integer greater than or equal to 1 and less than or equal to q.

Preferably, the capacitance values of the 1 st to the qth calibration capacitors in the calibration capacitor array are sequentially increased in a twofold relationship, and the 1 st to the qth bits of the initial digital signal are 0.

Preferably, the changing the digital signal such that the equivalent output capacitance of the calibration capacitance array changes, performing a first voltage switch such that the comparator output changes, and based on the change in the comparator output, determining a first calibration value for the digital signal comprises: selecting the most significant bit of the unselected data bits in the digital signal to become 1; executing the first voltage switching; obtaining the output of the comparator, and changing the selected highest bit to 0 if the output of the comparator represents that the holding voltage at the second end of the bridging capacitor is greater than or equal to the common-mode voltage; and jumping to a step of selecting the highest bit of the unselected data bits in the digital signal to be 1 until the unselected data bits do not exist in the digital signal, and outputting the digital signal at the moment as the first calibration value.

Preferably, the changing the digital signal such that the equivalent output capacitance of the calibration capacitance array changes, performing a second voltage switch such that the comparator output changes, and determining a second calibration value of the digital signal based on the change in the comparator output comprises: selecting the most significant bit of the unselected data bits in the digital signal to become 1; executing the second voltage switching; obtaining the output of the comparator, and changing the selected highest bit to 0 if the output of the comparator represents that the holding voltage at the second end of the bridging capacitor is less than or equal to the common-mode voltage; skipping to the step of selecting the most significant bit of the unselected data bit in the digital signal to be 1 until there is no unselected data bit in the digital signal, and outputting the digital signal at this time as the second calibration value.

Preferably, the holding voltage at the second end of the bridge capacitor is equal to or approximately equal to the predetermined common mode voltage in the absence of unselected data bits in the digital signal.

Preferably, the capacitance values of the 1 st to q th calibration capacitors in the calibration capacitor array are equal, and the 1 st to q th bits of the initial digital signal are 0.

Preferably, the changing the digital signal such that the equivalent output capacitance of the calibration capacitance array changes, performing a first voltage switch such that the comparator output changes, and based on the change in the comparator output, determining a first calibration value for the digital signal comprises: selecting one unselected data bit from the digital signal to become 1; executing the first voltage switching; obtaining the output of the comparator, and if the output of the comparator indicates that the holding voltage at the second end of the bridge capacitor is smaller than the common-mode voltage, repeating the step until the output of the comparator indicates that the holding voltage at the second end of the bridge capacitor is larger than or equal to the common-mode voltage; outputting the digital signal with the hold voltage at the second end of the bridge capacitance being greater than or equal to the common mode voltage as the first calibration value.

Preferably, the changing the digital signal such that the equivalent output capacitance of the calibration capacitance array changes, performing a second voltage switch such that the comparator output changes, and determining a second calibration value of the digital signal based on the change in the comparator output comprises: selecting one unselected data bit from the digital signal to become 1; executing the second voltage switching; obtaining the output of the comparator, and if the output of the comparator indicates that the holding voltage at the second end of the bridge capacitor is greater than the common-mode voltage, repeating the step until the output of the comparator indicates that the holding voltage at the second end of the bridge capacitor is less than or equal to the common-mode voltage; outputting a digital signal with a holding voltage at a second end of the bridge capacitance equal to or less than the common mode voltage as the second calibration value.

Preferably, the first voltage switching and the second voltage switching both further include: connecting the second end of the bridging capacitor with the preset common mode voltage for charge sampling, and disconnecting the second end of the bridging capacitor from the preset common mode voltage for charge holding.

Preferably, the determining, based on the first calibration value and the second calibration value of the digital signal, the calibration parameter provided to the calibration capacitive array for calibration includes: the determining of the calibration parameter provided to the calibration capacitive array is based on an average of the first calibration value and the second calibration value of the digital signal.

According to another aspect of the embodiments of the present invention, there is provided an analog-to-digital converter including: a low-order capacitor array including 1 st to mth capacitors and an auxiliary capacitor, first ends of the 1 st to mth capacitors and the auxiliary capacitor being connected to each other; the high-order capacitor array comprises m +1 th to nth capacitors, and first ends of the m +1 th to nth capacitors are connected with each other; a bridge capacitor, a first end of which is connected with the first ends of the 1 st to mth capacitors, a second end of which is connected with the first ends of the m +1 th to nth capacitors, and m and n are integers more than or equal to 1; the calibration capacitor array comprises 1 st to q th calibration capacitors, and first ends of the 1 st to q th calibration capacitors are connected with a first end of each capacitor in the low-order capacitor array and a first end of the bridging capacitor; a first input end of the comparator is connected with a second end of the bridging capacitor, and a second input end of the comparator is used for receiving a preset common mode voltage; and the control circuit is used for determining the equivalent output capacitance of the calibration capacitor array in the analog-to-digital conversion process according to the calibration parameter of the calibration capacitor array in the analog-to-digital conversion process and controlling the connection potential of the second end switches of the high-order capacitor array and the low-order capacitor array in the analog-to-digital conversion process, wherein the control circuit executes the calibration method in the calibration process before the analog-to-digital conversion process so as to determine the calibration parameter.

The analog-to-digital converter and the calibration method thereof provided by the embodiment of the invention have the following beneficial effects.

The calibration method comprises the steps of obtaining a first calibration value through a first calibration process, obtaining a second calibration value through a second calibration process, and then determining a calibration parameter of a calibration capacitor array according to the first calibration value and the second calibration value, wherein the first calibration process and the second calibration process both need to switch the potentials connected with the lowest bit capacitor of a high-bit capacitor array and all capacitors of the low-bit capacitor array in a charge sampling stage and a charge holding stage, the difference is that the potential change directions of the first calibration process and the second calibration process are opposite, and the obtained calibration parameter is not affected by the input offset voltage of a comparator through opposite potential switching, so that the influence of the input offset voltage of the comparator in the calibration process can be effectively eliminated in the calibration process, and the calibration accuracy is improved.

In addition, the weight ratio between the high-order capacitor array and the low-order capacitor array of the analog-to-digital converter after calibration meets the requirement of binary system, and the signal-to-noise ratio and the linearity of the analog-to-digital converter are not limited on the basis of ensuring the internal weight ratio of the capacitor array.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 is a schematic diagram illustrating a conventional successive approximation type analog-to-digital converter;

FIG. 2 is a schematic diagram of a capacitive DAC for a digital CMOS process;

FIG. 3 is a schematic diagram of a capacitive DAC with a bridge capacitor structure;

FIG. 4 is a schematic diagram of a 12-bit successive approximation type analog-to-digital converter according to an embodiment of the present invention;

FIG. 5 is a flow chart of a method of calibrating a successive approximation analog to digital converter according to an embodiment of the invention;

FIG. 6 is a specific flow chart illustrating the determination of the first calibration value of the digital signal in the calibration method of FIG. 5;

FIG. 7 is a schematic flow chart of a specific method for determining a second calibration value of the digital signal in the calibration method of FIG. 5;

FIG. 8 illustrates another specific flow chart for determining the first calibration value of the digital signal in the calibration method of FIG. 5;

fig. 9 shows another specific flowchart for determining a second calibration value of the digital signal in the calibration method of fig. 5.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected" or "coupled" to another element, or being "connected" or "coupled" between two nodes, it may be directly coupled or connected to the other element or intervening elements may also be present, and the connection or coupling between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Fig. 1 shows a schematic structure of a conventional successive approximation type analog-to-digital converter. As shown in fig. 1, SAR ADC100 includes a sample-and-hold circuit 110, a comparator 120, a logic control circuit 130, and a digital-to-analog converter 140. The sample hold circuit 110 samples the analog input signal according to the sampling clock and provides the sampled analog input signal to the comparator 120, the comparator 120 compares the analog input signal with the analog voltage generated by the digital-to-analog converter 140, the logic control circuit 130 generates a logic control signal according to the comparison result of the comparator 120, and the feedback control digital-to-analog converter 140 generates a new analog voltage to approximate the analog input signal until the analog voltage is approximately equal to the analog input signal, and the digital output corresponding to the analog voltage is the output of the SAR ADC 100.

Fig. 2 shows a schematic structure diagram of a capacitive digital-to-analog converter in a digital CMOS process. As shown in fig. 2, the capacitive digital-to-analog converter 200 is composed of a group of capacitor arrays and bottom plate switches corresponding to each capacitor, and the capacitance value ratio between capacitors in a typical capacitor array satisfies binary weights, i.e. the lowest-order capacitor 210 is a unit capacitance value 1C, the second lowest-order capacitor 220 is a capacitance value 2C twice as large, and so on, for an ADC with n-bit design accuracy, the highest-order capacitor 230 of the capacitive digital-to-analog converter is 2^n-1C. The capacitive digital-to-analog converter is specifically realized by controlling the conducting direction of a bottom plate switch of a capacitor corresponding to the weight according to digital input, so that analog output corresponding to the digital input is generated on a top plate of a capacitor array.

The resolution of the analog-digital converter depends on the matching precision between the capacitances of the capacitance type digital-analog converter and parasitic factors existing in actual manufacturing. With the improvement of the resolution requirement of the analog-to-digital converter, the capacitance type digital-to-analog converter with the binary weight proportion exponentially increases the size, the area and the number of bits of the input load of a front-stage circuit, and the application of the analog-to-digital converter is limited.

In order to solve the above problems, some conventional successive approximation type analog-to-digital converters with high precision generally employ a capacitance type digital-to-analog converter with a bridge capacitance structure, so as to further reduce the total capacitance number and size of the capacitance type digital-to-analog converter.

Fig. 3 shows a schematic diagram of a capacitive digital-to-analog converter with a bridge capacitor structure. Fig. 3 shows an 8-bit capacitive digital-to-analog converter 300, which includes capacitor sub-arrays 310 and 320 and a bridge capacitor Cb. The bridge capacitor Cb is connected between the capacitor sub-array 310 and the capacitor sub-array 320. The capacitor subarray 310 corresponds to a quantization bit with a higher weight and is a high-order capacitor array, and the capacitor subarray 320 corresponds to a quantization bit with a lower weight and is a low-order capacitor array. The bridge capacitor Cb is connected in series between the upper capacitor array 310 and the lower capacitor array 320 to ensure that the weights of the upper capacitor array 310 and the lower capacitor array 320 still satisfy the binary ratio, i.e. in the capacitive adc 300, the total capacitance of the lower capacitor array 320 and the lowest capacitor in the upper capacitor array 310 are the same in magnitude. In the conventional capacitive digital-to-analog converter 300, a bottom plate sampling technology and a switching time sequence are adopted, and the bridging capacitor Cb between the sub-capacitor sub-arrays is introduced, so that the number of capacitors and the switching power consumption are greatly reduced. However, in order to ensure that the weights of the upper capacitor array 310 and the lower capacitor array 320 still satisfy the binary ratio, the capacitance of the bridging capacitor Cb has a parasitic capacitance, and the parasitic capacitance of the lower capacitor array also affects the weight of the lower capacitor array, which introduces a serious mismatch problem, increases the matching difficulty, and may cause a conversion error.

A first embodiment of the present invention provides a single-ended successive approximation analog-to-digital converter (SAR ADC) including a low-side capacitor array, a high-side capacitor array, a bridge capacitor, a calibration capacitor array, and a comparator. The low-order capacitor array is composed of 1 st to mth capacitors, an auxiliary capacitor, and a plurality of first switches corresponding to the 1 st to mth capacitors and the auxiliary capacitor, and the 1 st to mth capacitors and the auxiliary capacitor are controlled to be connected to a reference voltage Vref or a reference ground voltage GND by the first switches. The capacitance values of the 1 st to the m th capacitors are sequentially increased in a twofold relationship (the capacitance values of the 1 st to the m th capacitors can be 1C to 2)^m-1C, C is the size of the unit capacitor), and the capacitance value of the auxiliary capacitor is the unit capacitor. The high-order capacitor array is composed of m +1 th to nth capacitors and a plurality of second switches corresponding to the m +1 th to nth capacitors, and the m +1 th to nth capacitors are controlled to be connected with a reference voltage Vref or a reference ground voltage GND by the second switches. The capacitance values of the m +1 th to the n th capacitors are sequentially increased in a twofold relationship (the capacitance values of the m +1 th to the n th capacitors can be 1C to 2)^n-m-1C, C is the unit capacitance size). Calibrating a capacitor arrayThe reference ground voltage GND is controlled to be connected or disconnected from the 1 st to the qth calibration capacitors by controlling the third switches. In addition, the capacitance values of the 1 st to q th calibration capacitors may be sequentially increased in a twofold relationship or may be equal to each other (for example, the capacitance values of the 1 st to q th calibration capacitors are all equal to the unit capacitor C). The first ends of the 1 st to mth capacitors and the first end of the calibration capacitor array are connected with the first end of the bridging capacitor, the first ends of the m +1 th to nth capacitors are connected with the second end of the bridging capacitor, and m, n and q are integers greater than or equal to 1.

Fig. 4 is a schematic structural diagram of a 12-bit successive approximation type analog-to-digital converter according to an embodiment of the invention. As shown in fig. 4, SAR ADC400 includes a 6-bit low-side capacitor array 410, a 6-bit high-side capacitor array 420, a bridge capacitor Cb, a 6-bit calibration capacitor array 430 (i.e., m and q equal to 6, and n equal to 12), a comparator 440, and a control circuit 450.

Specifically, the lower capacitor array 410 includes capacitors C101 to C106 (i.e., m — 6 in the present embodiment) and switches K11 to K16. The capacitances of the capacitors C101 to C106 are sequentially increased in a twofold relationship, first terminals of the capacitors C101 to C106 are connected to each other and to a first terminal of the bridge capacitor Cb, second terminals of the capacitors C101 to C106 are connected to the switches K11 to K16, respectively, and the switches K11 to K16 are, for example, single-pole, three-throw switches for connecting the capacitors C101 to C106 to the reference voltage Vref, the ground reference voltage GND or the analog input signal Vin. The low-side capacitor array 410 further includes an auxiliary capacitor Cd having a first terminal connected to the first terminals of the capacitors C101 to C106, a second terminal connected to the switch K17, and a switch K17 for connecting the auxiliary capacitor Cd to the reference voltage Vref or the ground reference voltage GND, and a switch K17. The capacitance of the auxiliary capacitor Cd is, for example, a unit capacitor, so that the equivalent output capacitance of the low-order capacitor array 410 is equal to the capacitance of the lowest-order capacitor in the high-order capacitor array 420.

The high-side capacitor array 420 includes capacitors C107 to C112 (i.e., n-12 in the present embodiment) and switches K21 to K26. The capacitances of the capacitors C107 to C112 increase in a twofold relationship, first terminals of the capacitors C107 to C112 are connected to each other and to a second terminal of the bridge capacitor Cb, second terminals of the capacitors C107 to C112 are connected to the switches K21 to K26, respectively, and the switches K21 to K26 are, for example, single-pole three-throw switches for connecting the capacitors C107 to C112 to the reference voltage Vref, the ground reference voltage GND or the analog input signal Vin.

Further, in SAR ADC400, node VQ is the capacitance common node of lower capacitor array 410, node VP is the capacitance common node of upper capacitor array 420, equivalent capacitance Cp1 is the equivalent parasitic capacitance of node VQ to ground, and equivalent capacitance Cp2 is the equivalent parasitic capacitance of node VP to ground.

The calibration capacitor array 430 includes calibration capacitors C201 to C206 (i.e., q ═ 6 in the present embodiment) and switches K31 to K36. The capacitances of the calibration capacitors C201 to C206 increase in sequence by two times, first terminals of the calibration capacitors C201 to C206 are connected to each other and to the capacitors C101 to C106 in the low-order capacitor array and the first terminal of the auxiliary capacitor Cd, second terminals of the calibration capacitors C201 to C206 are connected to switches K31 to K36, respectively, and the switches K31 to K36 are, for example, single-pole switches for connecting or disconnecting the second terminals of the calibration capacitors C201 to C206 to the reference ground voltage GND.

The positive input terminal of the comparator 440 is connected to the second terminal of the bridge capacitor Cb, the negative input terminal is configured to receive the common mode voltage Vcm, and the comparator 440 is configured to compare the holding voltage Vsump at the second terminal of the bridge capacitor Cb with the common mode voltage Vcm and output a result signal according to the comparison result.

The control circuit 450 is configured to measure a calibration parameter according to the circuit mismatch information during the calibration process, and change an equivalent output capacitance of the calibration capacitor array according to the calibration parameter during the analog-to-digital conversion process, so that the calibration capacitor array calibrates the mismatch between the low-order capacitor array and the high-order capacitor array and the offset of the comparator.

Further, the SAR ADC400 further includes sampling switches K41 and K42, the sampling switch K41 is connected between the first terminals of the capacitors C107 to C112 and the common mode voltage Vcm, and the sampling switch K42 is connected between the inverting input terminal of the comparator 440 and the common mode voltage Vcm. The control circuit 450 is also operable to turn on the sampling switches K41 and K42 during the charge sampling phase and turn off the sampling switches K41 and K42 during the charge holding phase.

In this embodiment, the capacitances C101-C112 and the capacitances C201-C206 may comprise a composite capacitor, which may comprise or have a combination of capacitors or sub-capacitors with different temperature coefficients, such as a composite capacitor in which the temperature coefficients may cancel each other to provide a more stable capacitance value, or a more temperature stable resistor-capacitor product.

Fig. 5 shows a flow chart of a method of calibrating a successive approximation analog-to-digital converter according to an embodiment of the invention. The calibration method is performed, for example, by the control circuit 450 of fig. 4 to determine calibration parameters for calibrating the capacitive array during a calibration process. As shown in fig. 5, the calibration method includes steps S101-S104.

In step S101, an initial digital signal is provided to the calibration capacitor array. The digital signal is, for example, a q-bit binary number, and the digital signal changes an equivalent output capacitance of the calibration capacitor array by turning on at least one third switch in the calibration capacitor array. In one embodiment, bits 1 to q of the initial digital signal are all 0.

In step S102, the digital signal is changed, a first voltage switching is performed, so that the comparator output changes, and a first calibration value of the digital signal is determined based on the change of the comparator output.

Wherein the first voltage switching comprises: connecting a second end of a bridging capacitor to a preset common mode voltage for charge sampling, disconnecting the second end of the bridging capacitor from the preset common mode voltage for charge holding, connecting a second end of an m +1 th capacitor to a reference ground voltage in a charge sampling stage, connecting second ends of the 1 st to m th capacitors and the auxiliary capacitor to a reference voltage, connecting a second end of the m +1 th capacitor to the reference voltage in a charge holding stage, and connecting second ends of the 1 st to m th capacitors and the auxiliary capacitor to the reference ground voltage.

In step S103, the digital signal is changed, a second voltage switching is performed such that the comparator output varies, and a second calibration value of the digital signal is determined based on the variation of the comparator output.

Wherein the second voltage switching comprises: connecting a second end of a bridging capacitor to a preset common mode voltage for charge sampling, disconnecting the second end of the bridging capacitor from the preset common mode voltage for charge holding, connecting a second end of an m +1 th capacitor to a reference voltage in a charge sampling stage, connecting second ends of the 1 st to m th capacitors and the auxiliary capacitor to a reference ground voltage, connecting a second end of the m +1 th capacitor to the reference ground voltage in a charge holding stage, and connecting second ends of the 1 st to m th capacitors and the auxiliary capacitor to the reference voltage.

In step S104, calibration parameters for calibrating the capacitive array are determined based on the first calibration value and the second calibration value. In one embodiment, the calibration parameter is derived based on an average of the first calibration value and the second calibration value. It is easily understood that the calibration parameter may be a q-bit binary number or a switch driving signal, and the calibration parameter is used to change the equivalent output capacitance of the calibration capacitor array by changing the on and off of a plurality of third switches in the calibration capacitor array during a normal operating state, so that the circuit mismatch information between the high-order capacitor array and the low-order capacitor array can be matched.

Fig. 6 shows a specific flowchart for determining the first calibration value of the digital signal in the calibration method of fig. 5.

As shown in fig. 6, for the calibration capacitor array in which the capacitance values of the 1 st to q th calibration capacitors sequentially increase in a twofold relationship, the determining the first calibration value of the digital signal in the calibration method according to the embodiment of the present invention includes steps S211 to S219.

In step S211, the initialization digital signal code _ a is 000000 and i is 6. Specifically, an initial digital signal comprising a 6-bit binary number is provided to the calibration capacitance array 430. It is to be readily understood that the number of bits of the digital signal is set to 6 bits only for convenience of explanation, and the digital signal may be a binary number of an arbitrary number of bits.

In step S212, code _ a _ i is set to 1. In this step, the highest bit of the unselected data bits in the digital signal is selected to become 1, that is, the data bit of the 6 th bit (i ═ 6) of the digital signal is set to 1, that is, the code _ a at this time is 100000. Specifically, referring to fig. 4, in the calibration capacitor array 430, when the ith bit of the digital signal is 1, the third switch corresponding to the ith calibration capacitor of the calibration capacitor array is turned on (i.e., the switch K36 corresponding to the capacitor C206 is turned on), so as to connect the second terminal of the capacitor to the reference ground voltage, and when the ith bit of the digital signal is 0, the third switch corresponding to the ith calibration capacitor of the calibration capacitor array is turned off, so as to suspend the second terminal of the capacitor, where i is an integer greater than or equal to 1 and less than or equal to 6.

In step S213, the second terminal of the lowest capacitor of the high capacitor array is connected to the ground reference voltage, and the second terminals of all capacitors of the low capacitor array are connected to the reference voltage in the charge sampling phase. Specifically, in this step, the sampling switches K41 and K42 are turned on to perform charge sampling, the second terminal of the lowest capacitance (i.e., the capacitance C107) in the high-order capacitance array 420 is connected to the ground reference voltage GND, and the second terminals of all capacitances (i.e., the capacitances C101 to C106 and the auxiliary capacitance Cd) in the low-order capacitance array 410 are connected to the reference voltage Vref.

In step S214, in the charge holding stage, the second terminal of the lowest capacitor of the high capacitor array is connected to the reference voltage, and the second terminals of all capacitors of the low capacitor array are connected to the reference ground voltage. Specifically, in this step, the sampling switches K41 and K42 are turned off to hold the charges, and then the second terminal of the lowest capacitor (i.e., the capacitor C107) in the high-order capacitor array 420 is connected to the reference voltage Vref, and the second terminals of all the capacitors (i.e., the capacitors C101 to C106 and the auxiliary capacitor Cd) in the low-order capacitor array 410 are connected to the ground reference voltage GND.

Further, the calibration method of the present embodiment further includes connecting the second terminals of the other capacitors (i.e., capacitors C108 to C112) in the high-order capacitor array 420 to the reference voltage Vref or the ground reference voltage GND during the charge sampling phase and the charge holding phase, as long as they are not changed during the whole calibration process.

The switching of the lowest capacitor of the high-side capacitor array generates a positive voltage change at the second terminal of the bridge capacitor Cb:

where Cmsb1 represents the capacitance of the lowest order capacitor C107 of the high order capacitor array, Ceq represents the total equivalent capacitance at node VP:

where Cmsbt represents the equivalent output capacitance of the upper capacitor array, Clsbt represents the equivalent output capacitance of the lower capacitor array, Ctrim represents the equivalent output capacitance of the calibration capacitor array, and Cp1 and Cp2 represent the equivalent parasitic capacitances of nodes VQ and VP to ground.

Further, the equivalent output capacitance Cmsbt of the high-order capacitor array is obtained by the following formula:

wherein, Cmsb_iAnd the capacitance value of the ith capacitor of the high-order capacitor array is shown, wherein i is an integer which is more than or equal to 1 and less than or equal to 6.

Further, the equivalent output capacitance Clsbt of the low-order capacitor array is obtained by the following formula:

wherein, Clsb_iAnd a capacitance value of an ith capacitor of the low-order capacitor array, wherein i is an integer of more than or equal to 1 and less than or equal to 6. Cd denotes a capacitance value of the auxiliary capacitance in the low-order capacitance array.

Further, the equivalent output capacitance Ctrim of the calibration capacitor array is determined by the sum of capacitances corresponding to switch-on in the calibration capacitor array, that is:

b_ipresentation schoolConducting state of ith switch in quasi-capacitor array, b_i1 denotes switch on, b_iAnd 0 indicates that the switch is open. Ctric (Ctric) rim_iAnd a capacitance value representing the ith bit capacitance of the calibration capacitor array, wherein i is an integer greater than or equal to 1 and less than or equal to 6.

When Cb < Clsbt + Cp1+ Ctrim:

Ceq≈Cmsbt+Cp2+Cb

the switching of the switches in the low-side capacitor array will produce a negative voltage change on node VP:

the holding voltage Vsump _ a at the second terminal of the bridge capacitor Cb after the charge holding period is:

Vsump_a＝Vcm+ΔVcmsb1+ΔVlsbt

in step S215, it is determined whether or not the holding voltage Vsump _ a is equal to or higher than the common mode voltage Vcm. If Vsump _ a is not less than Vcm, continuing to step S216 and step S217 in sequence; if Vsump _ a < Vcm, the process proceeds to step S217.

In step S216, code _ a _ i is set to 0. In this step, if Vsump _ a is greater than or equal to Vcm, it indicates that Δ Vcmsb1+ Δ Vlsbt is greater than or equal to 0, that is, the weight of the lower capacitor array is less than or equal to the weight of the lowest capacitor in the upper capacitor array, which indicates that the equivalent output capacitance of the calibration capacitor array is greater than the capacitance to be compensated, and therefore, the binary number of the ith bit needs to be reset to 0, and the corresponding switch is turned off. If Vsump _ a < Vcm, it indicates that Δ Vcmsb1+ Δ Vlsbt < 0, i.e. the weight of the lower capacitor array is greater than the weight of the lowest capacitor in the upper capacitor array, indicating that the equivalent output capacitance of the calibration capacitor array is smaller than the capacitance to be compensated, and therefore, the binary number of the ith bit needs to be kept to 1.

In step S217, i-1 is set.

In step S218, it is determined whether i is smaller than 1. If i is less than 1, continue to step S219; if i is 1 or more, the process returns to step S212.

In step S219, the current digital signal code _ a is output as the first calibration value.

Specifically, after the value of one data bit is determined, the step of selecting the highest bit of the unselected data bits in the digital signal to become 1 is continued until there is no unselected data bit in the digital signal, and the digital signal at this time is output as the first calibration value.

Fig. 7 shows a specific flowchart for determining the second calibration value of the digital signal in the calibration method of fig. 5.

As shown in fig. 7, for the calibration capacitor array in which the capacitance values of the 1 st to q-th calibration capacitors sequentially increase in a twofold relationship, the determining the second calibration value of the data signal in the calibration method according to the embodiment of the present invention includes steps S221 to S229.

In step S221, the initialization digital signal code _ b is 000000 and i is 6. Specifically, an initial digital signal comprising a 6-bit binary number is provided to the calibration capacitance array 430 at this step. It is to be readily understood that the number of bits of the digital signal is set to 6 bits only for convenience of explanation, and the digital signal may be a binary number of an arbitrary number of bits.

In step S222, code _ b _ i is set to 1. In this step, the highest bit of the unselected data bits in the digital signal is selected to become 1, that is, the data bit of the 6 th bit (i ═ 6) of the digital signal is set to 1, that is, the code _ b at this time is 100000. Specifically, referring to fig. 4, in the calibration capacitor array 430, when the ith bit of the digital signal is 1, the third switch corresponding to the ith calibration capacitor of the calibration capacitor array is turned on (i.e., the switch K36 corresponding to the capacitor C206 is turned on), so as to connect the second terminal of the capacitor to the reference ground voltage, and when the ith bit of the digital signal is 0, the third switch corresponding to the ith calibration capacitor of the calibration capacitor array is turned off, so as to suspend the second terminal of the capacitor, where i is an integer greater than or equal to 1 and less than or equal to 6.

In step S223, the second terminal of the lowest capacitor of the high capacitor array is connected to the reference voltage, and the second terminals of all capacitors of the low capacitor array are connected to the reference ground voltage in the charge sampling phase. Specifically, in this step, the sampling switches K41 and K42 are turned on to perform charge sampling, the second terminal of the lowest capacitance (i.e., the capacitor C107) in the high-order capacitance array 420 is connected to the reference voltage Vref, and the second terminals of all capacitances (i.e., the capacitors C101 to C106 and the auxiliary capacitor Cd) in the low-order capacitance array 410 are connected to the ground reference voltage GND.

In step S224, in the charge holding stage, the second terminal of the lowest capacitor of the high capacitor array is connected to the ground reference voltage, and the second terminals of all capacitors of the low capacitor array are connected to the reference voltage. Specifically, in this step, the sampling switches K41 and K42 are turned off first to hold the charges, and then the second terminal of the lowest capacitor (i.e., the capacitor C107) in the high-side capacitor array 420 is connected to the ground reference voltage GND, and the second terminals of all the capacitors (i.e., the capacitors C101 to C106 and the auxiliary capacitor Cd) in the low-side capacitor array 410 are connected to the reference voltage Vref.

Further, the calibration method of the present embodiment further includes connecting the second terminals of the other capacitors (i.e., capacitors C108 to C112) in the high-order capacitor array 420 to the reference voltage Vref or the ground reference voltage GND during the charge sampling phase and the charge holding phase, as long as they are not changed during the whole calibration process.

The switching of the lowest capacitor of the high-side capacitor array generates a negative voltage change at the second terminal of the bridge capacitor Cb:

the switching of the low-side capacitor array generates a positive voltage change at the second terminal of the bridge capacitor Cb:

the holding voltage Vsump _ b at the second terminal of the bridge capacitor Cb after the charge holding phase is:

Vsump_b＝Vcm+ΔVcmsb1+ΔVlsbt

in step S225, it is determined whether or not the holding voltage Vsump _ b is equal to or less than Vcm. If Vsump _ b is less than or equal to Vcm, continue with step S226 and step S227; if Vsump _ b > Vcm, the process continues to step S227.

In step S226, code _ b _ i is set to 0. In this step, if Vsump _ b is less than or equal to Vcm, it indicates that Δ Vcmsb1+ Δ Vlsbt is less than or equal to 0, i.e. the weight of the lower capacitor array is less than or equal to the weight of the lowest capacitor in the upper capacitor array, which indicates that the equivalent output capacitance of the calibration capacitor array is greater than the capacitance to be compensated, and therefore, it is necessary to reset the binary number of the ith bit to 0 and turn off the corresponding switch. If Vsump _ b > Vcm, it indicates that Δ Vcmsb1+ Δ Vlsbt >0, i.e. the weight of the lower capacitor array is greater than the weight of the lowest capacitor in the upper capacitor array, indicating that the equivalent output capacitance of the calibration capacitor array is now smaller than the capacitance to be compensated, and therefore, the binary number of the ith bit needs to be kept to 1.

In step S227, i-1 is set.

In step S228, it is determined whether i is smaller than 1. If i is less than 1, continue to step S229; if i is 1 or more, the process returns to step S222.

In step S229, the current digital signal code _ b is output as the second calibration value.

Specifically, after the value of one data bit is determined, the step of selecting the highest bit of the unselected data bits in the digital signal to be 1 is continued until there is no unselected data bit in the digital signal, and the digital signal at this time is output as the second calibration value.

In the analog-to-digital converter according to the embodiment of the present invention, when the input offset voltage Vos of the comparator is equal to 0, the first calibration value and the second calibration value are equal to each other without considering noise, and the obtained calibration parameter can compensate for the mismatch error caused by the bridge capacitor Cb. When the input offset voltage Vos of the comparator is large, the comparator result in the calibration process is affected, so that the calibration capacitors corresponding to the first calibration value and the second calibration value cannot accurately compensate the mismatch error caused by the bridge capacitor Cb.

The first calibration process and the second calibration process are both used for switching the lowest bit capacitance of the high-bit capacitor array and the potential connected with all the capacitances of the low-bit capacitor array in the charge sampling stage and the charge holding stage, the difference is that the potential change directions of the first calibration process and the second calibration process are opposite, and when the input offset voltage Vos of the comparator is considered, at the end of the first calibration process:

at the end of the second calibration procedure:

the following can be derived from the above equation:

wherein Ctrima and Ctrima are equivalent output capacitances of the calibration capacitor array corresponding to the first calibration value and the second calibration value, respectively. From the above derivation, the calibration method of the present embodiment can effectively eliminate the influence of the input offset voltage of the comparator during the calibration process, so that the weight of the lowest-order capacitor of the high-order capacitor array is equal to the weight of the low-order capacitor array.

Fig. 8 shows another specific flowchart for determining the first calibration value of the digital signal in the calibration method of fig. 5.

As shown in fig. 8, for calibration capacitor arrays with the capacitance values of the 1 st to q th calibration capacitors being equal, determining the first calibration value of the digital signal in the calibration method of the embodiment of the present invention includes steps S311 to S317.

In step S311, the initialization digital signal code _ a is 000000 and i is 6. Specifically, an initial digital signal comprising a 6-bit binary number is provided to the calibration capacitance array 430. It is to be readily understood that the number of bits of the digital signal is set to 6 bits only for convenience of explanation, and the digital signal may be a binary number of an arbitrary number of bits.

In step S312, code _ a _ i is set to 1. In this step, the unselected data bits in the digital signal are selected to become 1. For example, a data bit of the 6 th bit (i ═ 6) of the digital signal is set to 1, that is, code _ a at this time is 100000.

In step S313, in the charge sampling phase, the second terminal of the lowest capacitor of the high capacitor array is connected to the ground reference voltage, and the second terminals of all capacitors of the low capacitor array are connected to the reference voltage. Specifically, in this step, the sampling switches K41 and K42 are turned on to perform charge sampling, the second terminal of the lowest capacitance (i.e., the capacitance C107) in the high-order capacitance array 420 is connected to the ground reference voltage GND, and the second terminals of all capacitances (i.e., the capacitances C101 to C106 and the auxiliary capacitance Cd) in the low-order capacitance array 410 are connected to the reference voltage Vref.

In step S314, the second terminal of the lowest capacitance of the high-order capacitance array is connected to the reference voltage, and the second terminals of all the capacitances of the low-order capacitance array are connected to the reference ground voltage in the charge holding stage. Specifically, in this step, the sampling switches K41 and K42 are turned off to hold the charges, and then the second terminal of the lowest capacitor (i.e., the capacitor C107) in the high-order capacitor array 420 is connected to the reference voltage Vref, and the second terminals of all the capacitors (i.e., the capacitors C101 to C106 and the auxiliary capacitor Cd) in the low-order capacitor array 410 are connected to the ground reference voltage GND.

Further, the calibration method of the present embodiment further includes connecting the second terminals of the other capacitors (i.e., capacitors C108 to C112) in the high-order capacitor array 420 to the reference voltage Vref or the ground reference voltage GND during the charge sampling phase and the charge holding phase, as long as they are not changed during the whole calibration process.

In step S315, it is determined whether or not the holding voltage Vsump _ a is equal to or higher than the common mode voltage Vcm. If Vsump _ a < Vcm, continue with step S316; if Vsump _ a is not less than Vcm, the process continues to step S317.

In step S316, i-1 is set, and the process returns to step S312. In this step, if Vsump _ a < Vcm, it indicates Δ Vcmsb1+ Δ Vlsbt < 0, i.e. the weight of the lower capacitor array is greater than the weight of the lowest capacitor in the upper capacitor array, which indicates that the equivalent output capacitance of the calibration capacitor array is smaller than the capacitance to be compensated, so the data bit of the i-1 th bit needs to be set to 1, and the above steps are repeated until Vsump _ a ≧ Vcm.

In step S317, the current digital signal code _ a is output as the first calibration value. In this step, if Vsump _ a is greater than or equal to Vcm, it indicates that Δ Vcmsb1+ Δ Vlsbt is greater than or equal to 0, that is, the weight of the lower capacitor array is less than or equal to the weight of the lowest capacitor in the upper capacitor array, which indicates that the equivalent output capacitance of the calibration capacitor array is greater than or equal to the capacitance that needs to be compensated, and the digital signal at this time is output as the first calibration value.

Fig. 9 shows another specific flowchart for determining a second calibration value of the digital signal in the calibration method of fig. 5.

As shown in fig. 9, for calibration capacitor arrays with the capacitance values of the 1 st to q-th calibration capacitors being equal, the determining the second calibration value of the digital signal in the calibration method of the embodiment of the present invention includes steps S321 to S327.

In step S321, the initialization digital signal code _ b is 000000 and i is 6. Specifically, an initial digital signal comprising a 6-bit binary number is provided to the calibration capacitance array 430. It is to be readily understood that the number of bits of the digital signal is set to 6 bits only for convenience of explanation, and the digital signal may be a binary number of an arbitrary number of bits.

In step S322, code _ b _ i is set to 1. In this step, the unselected data bits in the digital signal are selected to become 1. For example, a data bit of the 6 th bit (i ═ 6) of the digital signal is set to 1, that is, code _ b at this time is 100000.

In step S323, in the charge sampling phase, the second terminal of the lowest capacitor of the high-order capacitor array is connected to the reference voltage, and the second terminals of all capacitors of the low-order capacitor array are connected to the reference ground voltage. Specifically, in this step, the sampling switches K41 and K42 are turned on to perform charge sampling, the second terminal of the lowest capacitance (i.e., the capacitor C107) in the high-order capacitance array 420 is connected to the reference voltage Vref, and the second terminals of all capacitances (i.e., the capacitors C101 to C106 and the auxiliary capacitor Cd) in the low-order capacitance array 410 are connected to the ground reference voltage GND.

In step S324, the second terminals of the lowest capacitors of the high-order capacitor array are connected to the ground voltage reference, and the second terminals of all the capacitors of the low-order capacitors are connected to the reference voltage. Specifically, in this step, the sampling switches K41 and K42 are turned off first to hold the charges, and then the second terminal of the lowest capacitor (i.e., the capacitor C107) in the high-side capacitor array 420 is connected to the ground reference voltage GND, and the second terminals of all the capacitors (i.e., the capacitors C101 to C106 and the auxiliary capacitor Cd) in the low-side capacitor array 410 are connected to the reference voltage Vref.

Further, the calibration method of the present embodiment further includes connecting the second terminals of the other capacitors (i.e., capacitors C108 to C112) in the high-order capacitor array 420 to the reference voltage Vref or the ground reference voltage GND during the charge sampling phase and the charge holding phase, as long as they are not changed during the whole calibration process.

In step S325, it is determined whether or not the holding voltage Vsump _ b is equal to or less than the common mode voltage Vcm. If Vsump _ b > Vcm, continue with step S326; if Vsump _ b is less than or equal to Vcm, then continue with step S327.

In step S326, i-1 is set, and the process returns to step S322. In this step, if Vsump _ b > Vcm, it indicates that Δ Vcmsb1+ Δ Vlsbt >0, i.e. the weight of the lower capacitor array is greater than that of the lowest capacitor in the upper capacitor array, which indicates that the equivalent output capacitance of the calibration capacitor array is smaller than the capacitance to be compensated, and therefore it is necessary to set the data bit of the i-1 th bit to 1 and repeat the above steps until Vsump _ b ≦ Vcm.

In step S327, the current digital signal code _ b is output as a second calibration value. In this step, if Vsump _ b is smaller than or equal to Vcm, it indicates Δ Vcmsb1+ Δ Vlsbt is smaller than or equal to 0, i.e. the weight of the lower capacitor array is smaller than or equal to the weight of the lowest capacitor in the upper capacitor array, which indicates that the equivalent output capacitance of the calibration capacitor array at this time is greater than or equal to the capacitance to be compensated, and the digital signal at this time is output as the second calibration value.

It should be noted that the calibration method of the embodiment of the present invention is not only applicable to a single-ended successive approximation analog-to-digital converter, but also applicable to a differential analog-to-digital converter and different capacitor array segments, and the calibrated analog-to-digital converter not only satisfies the requirement of a binary system for the weight ratio between the high-order capacitor array and the low-order capacitor array, but also is not limited in the signal-to-noise ratio and the linearity on the basis of ensuring the internal weight ratio of the capacitor array.

In addition, the calibration method of the present embodiment is unidirectional to the calibration process of calibrating the capacitor array, so it is necessary to make the sum of the weights of the lower capacitor array greater than the weight of the lowest capacitor of the higher capacitor array during the design process (for example, by increasing the bridge capacitor Cb), and then decrease the sum of the weights of the lower capacitor array by increasing the equivalent output capacitance of the calibration capacitor array during the calibration process.

In summary, in the analog-to-digital converter and the calibration method thereof according to the embodiments of the invention, the calibration method obtains the first calibration value through the first calibration process, obtains the second calibration value through the second calibration process, then, a calibration parameter for calibrating the capacitor array is determined based on the first calibration value and the second calibration value, wherein the first calibration process and the second calibration process both require switching the lowest capacitance of the higher capacitor array and the entire capacitance of the lower capacitor array in the charge sampling stage and the charge holding stage, respectively, with the difference that the potential change directions of the first calibration process and the second calibration process are opposite, by means of the reverse potential switching, the obtained calibration parameters are not affected by the input offset voltage of the comparator, therefore, the influence of the input offset voltage of the comparator in the calibration process can be effectively eliminated in the calibration process, and the calibration accuracy is improved.

In addition, the weight ratio between the high-order capacitor array and the low-order capacitor array of the analog-to-digital converter after calibration meets the requirement of binary system, and the signal-to-noise ratio and the linearity of the analog-to-digital converter are not limited on the basis of ensuring the internal weight ratio of the capacitor array.

It will be understood by those of ordinary skill in the art that the words "during", "when" and "when … …" as used herein in relation to the operation of a circuit are not strict terms referring to actions occurring immediately upon initiation of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reactive action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.