阅读说明：本技术 一种多模融合乘法器 (Multimode fusion multiplier ) 是由 范团宝 蒋越星 时小山 杨朝 于 2020-04-01 设计创作，主要内容包括：本申请提供一种多模融合乘法器,涉及电子技术领域,用于降低乘法器的运算时间和功耗。该乘法器用于实现二进制的单乘法运算A[m-(1)-1:0]×B[m-(2)-1:0],或者2N个二进制乘法A0[m-(3)-1:0]×B0[m-(4)-1:0]的累加和运算,m-(1)≥2N×m-(3),m-(2)≥2N×m-(4),N为正整数,包括：P个预编码器、Q组融合编码器、以及压缩器；其中,P个预编码器和Q组融合编码器均用于对单乘法运算或者多乘法累加和运算中的第一数值和第二数值进行编码,并将多个部分积输出给压缩器,压缩器均可用于对单乘法运算或者多乘法累加和运算时对应的多个部分积进行压缩得到两个累加值；其中,在单乘法运算时,第一数值为A[m-(1)-1:0]、第二数值为B[m-(2)-1:0],在多乘法运算时,第一数值包括2N个A0[m-(3)-1:0],第二数值包括2N个B0[m-(4)-1:0]。(The application provides a multimode fusion multiplier, relates to the technical field of electronics, and is used for reducing the operation time and power consumption of the multiplier. The multiplier is used for realizing binary single multiplication A [ m ] 1 ‑1:0]×B[m 2 ‑1:0]Or 2N binary multiplications A0[ m ] 3 ‑1:0]×B0[m 4 ‑1:0]Sum of m 1 ≥2N×m 3 ，m 2 ≥2N×m 4 And N is a positive integer, including: p precoders, Q group fusion coders and compressors; the P precoders and the Q group fusion encoders are all used for encoding a first numerical value and a second numerical value in single multiplication operation or multiple multiplication accumulation sum operation and outputting a plurality of partial products to the compressor, and the compressor can be used for compressing a plurality of corresponding partial products in the single multiplication operation or multiple multiplication accumulation sum operation to obtain two accumulated values; wherein, in the case of a single multiplication, the first value is A [ m ] 1 ‑1:0]The second value is Bm 2 ‑1:0]In the case of multiple multiplication, the first value includes 2N A0[ m [ ] 3 ‑1:0]Second, secondThe values include 2N B0[ m ] 4 ‑1:0]。)

A multi-mode fusion multiplier, characterized by a single multiplication A [ m ] for implementing binary₁-1:0]×B[m ₂-1:0]Or 2N binary multiplications A0[ m ]₃-1:0]×B0[m ₄-1:0]Sum of m₁≥2N×m ₃，m ₂≥2N×m ₄And N is a positive integer, including: p precoders, Q group fusion encoder, and compressor, m₁、m ₂、m ₃、m ₄P and Q are integers greater than 1;

the P precoders are used for precoding a first numerical value according to the single multiplication indicating signal or the multiple multiplication indicating signals to obtain a precoding result; wherein the first value is the A [ m ] when the single multiplication indication signal indicates that the single multiplication operation is performed₁-1:0]Said first value comprising 2N of said A0[ m ] when said multiply indication signal indicates to perform said accumulate and sum operation₃-1:0]2N of said A0[ m ]₃-1:0]Arranged in order from the lower digit to the upper digit;

the Q group fusion encoder is used for encoding the pre-encoding result and the second numerical value to obtain a plurality of partial products; wherein the second value is the B [ m ] when the single multiplication indication signal indicates that the single multiplication operation is performed₂-1:0]Said second value comprising 2N of said B0[ m ] when said multiply indication signal indicates to perform said accumulate-and-sum operation₄-1:0]2N of said B0[ m ]₄-1:0]Arranged in order from the high order to the low order;

the compressor is configured to compress the plurality of partial products to obtain two accumulated values, where a sum of the two accumulated values is a result of the single multiplication operation or the accumulated sum operation.

The multiplier of claim 1, wherein when m is₁＞2N×m ₃The first value is middle to front (m)₁-2N×m ₃) Sign bits are filled in the high-order digits; and/or, when m₂＞2N×m ₄The second value is middle and last (m)₂-2N×m ₄) The lower digits are filled with invalid bits.

The multiplier of claim 1 or 2, wherein the P precoders comprise: an ith precoder to:

when i is more than or equal to 0 and less than or equal to Nxm₃-1, determining the ith group selection signal, the ith single multiplication group selection signal, the single multiplication control signal SCi and the first multiple multiplication control signal MCi in the encoded result according to the single multiplication indication signal, the multiple multiplication indication signal and at least two bits in the first numerical value, i is an even number;

when N × m₃≤i≤m ₁-1, determining an ith group selection signal, an ith single multiplication group selection signal, a single multiplication control signal SCi, a second multiple multiplication control signal MCNi and a control signal Si in the encoded result according to the single multiplication indication signal, the multiple multiplication indication signal and at least two bits in the first numerical value, i is an even number;

wherein the ith group selection signal includes a first selection signal M1Mi and a second selection signal M2Mi, and the ith single multiplication group selection signal includes a first single multiplication selection signal SM1Mi and a second single multiplication selection signal SM2 Mi.

The multiplier of claim 3, wherein when i equals 0, the at least two bits comprise a first bit a [0] and a second bit a [1] of the first value;

the 0 th precoder is used to perform the following encoding operations:

setting a first select signal M1M0 to the first bit a [0 ];

setting a second selection signal M2M0 to 1 when the first bit a [0] is 0 and the second bit a [1] is 1; setting a second selection signal M2M0 to 0 when the first bit a [0] is not 0 or the second bit a [1] is not 1;

when the single multiplication indicating signal is 1, setting a single multiplication control signal SC0 to the second bit a [1 ]; when the single multiplication instruction signal is 0, the single multiplication control signal SC0 is set to 0;

when the multiple multiplication indicating signal is 1, setting the first multiple multiplication control signal MC0 to the second bit a [1 ]; setting a first multiple multiplication control signal MC0 to 0 when the multiple multiplication indicating signal is 0;

when the single multiplication indicating signal is 1, setting the first single multiplication selecting signal SM1M0 as the first bit a [0], and setting the second single multiplication selecting signal SM2M0 as the second selecting signal M2M 0; when the single multiplication indicating signal is 0, both the first single multiplication selecting signal SM1M0 and the second single multiplication selecting signal SM2M0 are set to 0.

The multiplier of claim 3 or 4, wherein when 0 < i ≦ nxm₃-1, said at least two bits comprising a first bit a [ i-1] of said first value]A second bit a [ i ]]And a third bit a [ i +1]]；

The ith precoder is used to perform the following encoding operations:

setting the first selection signal M1Mi to 1 when the first bit a [ i-1] and the second bit a [ i ] are not equal; setting the first selection signal M1Mi to 0 when the first bit a [ i-1] and the second bit a [ i ] are equal;

setting the second selection signal M2Mi to 1 when the first bit a [ i-1] and the second bit a [ i ] are equal and the second bit a [ i ] and the third bit a [ i +1] are not equal; setting the second selection signal M2Mi to 0 when the first bit a [ i-1] and the second bit a [ i ] are not equal or the second bit a [ i ] and the third bit a [ i +1] are equal;

when the single multiplication indication signal is 1, setting the single multiplication control signal SCi as the third bit a [ i +1 ]; when the single multiplication indicating signal is 0, setting the single multiplication control signal SCi to 0;

when the multiple multiplication indicating signal is 1, taking the first multiple multiplication control signal MCi as the third bit a [ i +1 ]; setting the first multiple multiplication control signal MCi to 0 when the multiple multiplication indicating signal is 0;

when the single multiplication indicating signal is 1, setting the first single multiplication selecting signal SM1Mi as the first selecting signal M1Mi, and setting the second single multiplication selecting signal SM2Mi as the second selecting signal M2 Mi; when the single multiplication indicating signal is 0, both the first single multiplication select signal SM1Mi and the second single multiplication select signal SM2Mi are set to 0.

The multiplier according to any of claims 3 to 5, characterized in that when i is equal to Nxm₃When said at least two bits comprise a first bit a [ i-1] of said first value]A second bit a [ i ]]And a third bit a [ i +1]]；

N x m₃The precoder is used to perform the following encoding operations:

setting a fourth bit to the first bit a [ i-1] when the single multiplication indicating signal is 1; setting a fourth bit to 0 when the single multiplication indicating signal is 0;

setting the first selection signal M1Mi to 1 when the fourth bit and the second bit a [ i ] are not equal; setting the first selection signal M1Mi to 0 when the fourth bit and the second bit a [ i ] are equal;

setting the second selection signal M2Mi to 1 when the fourth bit and the second bit a [ i ] are equal and the second bit a [ i ] and the third bit a [ i +1] are not equal; setting the second selection signal M2Mi to 0 when the fourth bit and the second bit a [ i ] are not equal, or the second bit a [ i ] and the third bit a [ i +1] are equal;

setting the single multiplication control signal SCi to the third bit a [ i +1] when the single multiplication indication signal is 1; when the single multiplication indicating signal is 0, setting the single multiplication control signal SCi to 0;

setting the second multi-multiplication control signal MCNi to 0 when the multi-multiplication indicating signal is equal to the third bit a [ i +1], and setting the second multi-multiplication control signal MCNi to 1 when the multi-multiplication indicating signal is not equal to the third bit a [ i +1 ];

setting the control signal Si to the third bit a [ i +1 ];

when the single multiplication indicating signal is 1, setting the first single multiplication selecting signal SM1Mi as the first selecting signal M1Mi, and setting the second single multiplication selecting signal SM2Mi as the second selecting signal M2 Mi; when the single multiplication indicating signal is 0, both the first single multiplication select signal SM1Mi and the second single multiplication select signal SM2Mi are set to 0.

The multiplier of any of claims 3 to 6, characterised in that when nxm₃＜i≤m ₁1, the at least two bits include a first bit a [ i-1]A second bit a [ i ]]And a third bit a [ i +1]]；

The ith precoder is used to perform the following encoding operations:

setting the first selection signal M1Mi to 1 when the first bit a [ i-1] and the second bit a [ i ] are not equal; setting the first selection signal M1Mi to 0 when the first bit a [ i-1] and the second bit a [ i ] are equal;

setting the second selection signal M2Mi to 1 when the first bit a [ i-1] and the second bit a [ i ] are equal and the second bit a [ i ] and the third bit a [ i +1] are not equal; setting the second selection signal M2Mi to 0 when the first bit a [ i-1] and the second bit a [ i ] are not equal or the second bit a [ i ] and the third bit a [ i +1] are equal;

when the single multiplication indication signal is 1, setting the single multiplication control signal SCi to the third bit a [ i +1 ]; when the single multiplication indicating signal is 0, setting the single multiplication control signal SCi to 0;

setting the second multi-multiplication control signal MCNi to 0 when the multi-multiplication indicating signal is equal to the third bit a [ i +1], and setting the second multi-multiplication control signal MCNi to 1 when the multi-multiplication indicating signal is not equal to the third bit a [ i +1 ];

when the single multiplication indicating signal is 1, setting the first single multiplication selecting signal SM1Mi as the first selecting signal M1Mi, and setting the second single multiplication selecting signal SM2Mi as the second selecting signal M2 Mi; setting both the first single multiplication select signal SM1Mi and the second single multiplication select signal SM2Mi to 0 when the single multiplication indicating signal is 0;

setting the control signal Si to the third bit a [ i +1 ].

The multiplier according to any of claims 3 to 7, wherein the Q-bank fusion encoder comprises a first encoder for performing the following encoding operations:

setting the partial product p (i, k) to be the inverse of the single multiplication control signal SCi when the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are both 1 or the second single multiplication select signal SM2Mi and the second bit b [ k-1] in the second numerical value are both 1;

when the first single multiplication selecting signal SM1Mi and the first bit b [ k ] in the second numerical value are not simultaneously 1, and the second single multiplication selecting signal SM2Mi and the second bit b [ k-1] in the second numerical value are not simultaneously 1, the partial product p (i, k) is set as the single multiplication control signal SCi.

The multiplier of any of claims 3-8, wherein the Q-bank fused encoder further comprises: a second encoder for performing the following encoding operations:

setting a first intermediate term to 1 when both the first bit b [ k-1] in the multiple multiplication indicating signal and the second value are 1 or both the second bit b [ k ] in the single multiplication indicating signal and the second value are 1; setting a first intermediate term to 0 when a first bit b [ k-1] in the multiple multiplication indicating signal and the second value are not simultaneously 1 and a second bit b [ k ] in the single multiplication indicating signal and the second value are not simultaneously 1;

when the first intermediate term and the first selection signal M1Mi are both 1, or the second selection signal M2Mi and the first bit b [ k-1] are both 1, setting the second intermediate term to 1; setting a second middle term to 0 when the first middle term and the first selection signal M1Mi are not 1 at the same time and the second selection signal M2Mi and the first bit b [ k-1] are not 1 at the same time;

setting an inverse of the second multi-multiplication control signal MCNi to a partial product p (i, k) when the second intermediate term is 1; setting the second multi-multiplication control signal MCNi to a partial product p (i, k) when the second intermediate term is 0.

The multiplier of any of claims 3-9, wherein the Q-bank fused encoder further comprises: a third encoder for performing the following encoding operations:

setting the partial product p (i, k) to be the inverse of the single multiplication control signal SCi when the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second value are 1;

when the first single multiplication selecting signal SM1Mi and the first bit b [ k ] in the second value are not both 1, the partial product p (i, k) is set as the single multiplication control signal SCi.

The multiplier of any of claims 3-10, wherein the Q-bank fused encoder further comprises: a fourth encoder for performing the following encoding operations:

setting a first intermediate term to 1 when both the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second value are 1 or the second single multiplication select signal SM2Mi and the second bit b [ k-1] in the second value are 1; setting a first intermediate term to 0 when the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are not both 1 and the second single multiplication select signal SM2Mi and the second bit b [ k-1] in the second numerical value are not both 1;

setting a second intermediate term to be an inverse of the single multiplication control signal SCi when the first intermediate term is 1; setting a second intermediate term to the single multiplication control signal SCi when the first intermediate term is 0;

setting a partial product p (i, k) to 1 when the multiple multiplication indicating signal is 1; setting a partial product p (i, k) to the second intermediate term when the multiple multiplication indicating signal is 0.

The multiplier of any of claims 3-11, wherein the Q-bank fused encoder further comprises: a fifth encoder for performing the following encoding operations:

setting the partial product p (i, k) as the single multiplication control signal SCi when the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are both 1 or the second single multiplication select signal SM2Mi and the first bit b [ k ] in the second numerical value are both 1;

when the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are not both 1 and the second single multiplication select signal SM2Mi and the first bit b [ k ] in the second numerical value are not both 1, the partial product p (i, k) is set as the inverse of the single multiplication control signal SCi.

The multiplier of any of claims 3-12, wherein the Q-bank fused encoder further comprises: a sixth encoder for performing the following encoding operations:

setting the partial product p (i, k) to be the inverse of the control signal Si when the first selection signal M1Mi and the first bit b [ k ] in the second value are both 1 or the second selection signal M2Mi and the first bit b [ k ] in the second value are both 1;

when the first selection signal M1Mi and the first bit b [ k ] in the second value are not both 1 and the second selection signal M2Mi and the first bit b [ k ] in the second value are not both 1, the partial product p (i, k) is set as the control signal Si.

The multiplier of any of claims 3-13, wherein the Q-bank fused encoder further comprises: a seventh encoder for performing the following encoding operations:

setting a first intermediate term to 1 when both the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are 1, or both the second single multiplication select signal SM2Mi and the first bit b [ k ] in the second numerical value are 1; setting a first intermediate term to 0 when the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are not both 1 and the second single multiplication select signal SM2Mi and the first bit b [ k ] in the second numerical value are not both 1;

setting a second intermediate term to be an inverse of the single multiplication control signal SCi when the first intermediate term is 1; setting a second intermediate term to the single multiplication control signal SCi when the first intermediate term is 0;

setting partial product p (i, k) to the second intermediate term when the single multiplication indicating signal is 1; when the single multiplication instruction signal is 0, the partial product p (i, k) is set to 0.

The multiplier of any of claims 3-14, wherein the Q-bank fused encoder further comprises: an eighth encoder for performing the following encoding operations:

setting a first intermediate term to 1 when both the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are 1, or both the second single multiplication select signal SM2Mi and the first bit b [ k ] in the second numerical value are 1; setting a first intermediate term to 0 when the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are not both 1 and the second single multiplication select signal SM2Mi and the first bit b [ k ] in the second numerical value are not both 1;

setting a second intermediate term to be an inverse of the single multiplication control signal SCi when the first intermediate term is 1; setting a second intermediate term to the single multiplication control signal SCi when the first intermediate term is 0;

setting partial product p (i, k) to the second intermediate term when the single multiplication indicating signal is 1; setting the partial product p (i, k) to the inverse of the second intermediate term when the single multiplication indicating signal is 0.

The multiplier of any of claims 3-15, wherein the Q-bank fused encoder further comprises: a ninth encoder for performing the following encoding operations:

setting a first intermediate term to 1 when both the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second value are 1 or the second single multiplication select signal SM2Mi and the second bit b [ k-1] in the second value are 1; setting a first middle term to 0 when the first single multiplication select signal SM1Mi and the first bit b [ k ] in the second numerical value are not both 1 and the second single multiplication select signal SM2Mi and the second bit b [ k-1] in the second numerical value are not both 1;

setting a second intermediate term to be an inverse of the single multiplication control signal SCi when the first intermediate term is 1; setting a second intermediate term to the single multiplication control signal SCi when the first intermediate term is 0;

setting a partial product p (i, k) to 1 when the first multi-multiplication control signal MCi is 1; setting a partial product p (i, k) to the second intermediate term when the first multi-multiplication control signal MCi is 0.

The multiplier according to any of claims 3 to 16, wherein the Q-bank fusion encoder further comprises: a tenth encoder for performing the following encoding operations:

setting a first intermediate term to 1 when a first bit b [ k-1] in the multiple multiplication indicating signal and the second numerical value are both 1 or a second bit b [ k ] in the single multiplication indicating signal and the second numerical value are both 1; setting a first intermediate term to 0 when a first bit b [ k-1] in the multiple multiplication indicating signal and the second value are not simultaneously 1 and a second bit b [ k ] in the single multiplication indicating signal and the second value are not simultaneously 1;

setting a second intermediate term to 1 when the first intermediate term and the first select signal M1Mi are simultaneously 1, or the second select signal M2Mi and the first bit b [ k-1] are simultaneously 1; setting a second middle term to 0 when the first middle term and the first select signal M1Mi are not 1 at the same time and the second select signal M2Mi and the first bit b [ k-1] are not 1 at the same time;

setting a third intermediate term to be an inverse of the second multi-multiplication control signal MCNi when the second intermediate term is 1; when the second intermediate term is 0, setting a third intermediate term to the second multi-multiplication control signal MCNi;

setting a partial product p (i, k) to an inverse of the third intermediate term when the multiple multiplication indicating signal is 1; setting a partial product p (i, k) to the third intermediate term when the multiple multiplication indicating signal is 0.