阅读说明：本技术 一种无基准自启动的线性稳压器 (No-reference self-starting linear voltage stabilizer ) 是由 蔡胜凯 董渊 李响 张军 庄健 于 2021-09-14 设计创作，主要内容包括：本发明公开了一种无基准自启动的线性稳压器,涉及线性稳压器领域,该线性稳压器的工作电源上电时产生偏置电流,偏置电流将自启动电路的输出端VA的电压拉低,继而将P0的栅极的电压拉低而导通,当输出电压升高带动采样输出端的电压升高时,反馈调节电路在采样输出端的作用下驱动P9达到高于偏置电流的稳定电流,使得自启动电路的输出端被拉高使得自启动电路关闭,该线性稳压器可以在没有基准电压的基础上实现自启动并在稳定后关闭,由于无需额外的基准电压产生电路,因此可以简化电路结构,减小芯片面积,提高集成度。(The invention discloses a no-reference self-starting linear voltage stabilizer, which relates to the field of linear voltage stabilizers, wherein a working power supply of the linear voltage stabilizer generates a bias current when being electrified, the bias current pulls down the voltage of an output end VA of a self-starting circuit and then pulls down the voltage of a grid electrode of P0 to be conducted, when the output voltage is raised to drive the voltage of a sampling output end to be raised, a feedback regulating circuit drives P9 to reach a stable current higher than the bias current under the action of the sampling output end, so that the output end of the self-starting circuit is pulled up to close the self-starting circuit, the linear voltage stabilizer can realize self-starting on the basis of no reference voltage and close the self-starting circuit after being stabilized, and as no additional reference voltage generating circuit is needed, the circuit structure can be simplified, the chip area is reduced, and the integration level is improved.)

1. A reference-less self-starting linear regulator, comprising a voltage generation circuit in which: the source electrode of the PMOS pipe P0 is connected with a working power supply, the drain electrode of the PMOS pipe P0 is grounded through a sampling circuit, the drain electrode of the PMOS pipe P0 is also connected with the voltage output end of the linear voltage stabilizer, and the sampling output end of the sampling circuit is connected with a feedback regulation circuit;

the bias current IB is connected with a first pull-up branch consisting of t1 PMOS tubes in the self-starting circuit through a first current mirror and is connected to a working power supply, the common end of the first pull-up branch and the first current mirror is used as an output end VA of the self-starting circuit and is connected with the cathode of a diode D0, and the anode of the diode D0 is connected with the grid electrode of a PMOS tube P0; the source electrode of a PMOS tube P9 in the self-starting circuit is connected with the working power supply, the drain electrode of the PMOS tube P9 is connected with the output end VA of the self-starting circuit, and the grid electrode of the PMOS tube P9 is connected with the feedback regulating circuit;

the bias current IB is generated when the working power supply is electrified, the bias current IB pulls down the voltage of the output end VA of the self-starting circuit to VDD-t1 multiplied by VGS, and then the voltage of the grid electrode of the PMOS tube P0 is pulled to VDD-t1 multiplied by VGS + V_D0And is turned on, VGS is the gate-source voltage of each PMOS tube, V_D0Is the forward conduction voltage drop of diode D0, VDD is the voltage of the operating power supply;

the output voltage of the voltage output end of the linear voltage stabilizer is increased to drive the voltage of the sampling output end to be increased until the feedback adjusting circuit drives the PMOS tube P9 to reach a stable current higher than the bias current IB under the action of the sampling output end, and the output end VA of the self-starting circuit is pulled high to enable the self-starting circuit to be closed.

2. The linear regulator of claim 1, wherein in the feedback regulation circuit, a PMOS transistor P1 and a PMOS transistor P2 of the same size are connected to form a current mirror structure, a source of the PMOS transistor P1 is connected to a source of the PMOS transistor P2 and to the operating power supply, a gate of the PMOS transistor P1 is connected to a gate of the PMOS transistor P2 and to a drain of the PMOS transistor P1, a drain of the PMOS transistor P1 is connected to a collector of a transistor Q0, an emitter of a transistor Q0 is grounded, a base of the transistor Q0 is connected to a base of a transistor Q1, an emitter of the transistor Q1 is grounded through a resistor R3, and a collector of the transistor Q1 is connected to a drain of the PMOS transistor P2; the emitter of the triode Q2 is grounded, and the collector of the triode Q2 is connected with the base and is connected with the base of the triode Q0 and the sampling output end; the drain electrode of the PMOS tube P2 is connected with the anode of the diode D0 and the grid electrode of the PMOS tube P0, and the drain electrode of the PMOS tube P1 is connected with the grid electrode of the PMOS tube P9;

the size of the transistor Q0 is the same as that of the transistor Q2, and the size ratio of the transistor Q0 to the transistor Q1 is 1: when the voltage of the voltage output end is increased to drive the voltage of the sampling output end to be increased to exceed the starting voltage of the triode, the triodes Q0, Q1 and Q2 are all conducted, the PMOS tube P9 mirrors the current of the PMOS tube P1, and the stable current is I ═ Vt/lnN)/R3, wherein Vt is thermal voltage.

3. The linear regulator of claim 2, wherein the sampling circuit comprises a resistor R1 and a resistor R0, the drain of the PMOS transistor P0 is grounded via the resistor R1 and the resistor R0 in turn, and the common terminal of the resistor R1 and the resistor R0 serves as the sampling output terminal, so that the output voltage of the voltage output terminal of the linear regulator is V_outVt lnN (R1/R3) + Vbe2(1+ R1/R0), Vbe2 is the voltage across resistor R0, the output voltage of the linear regulator is related to resistors R0, R1 and R3, and the temperature coefficient of the output voltage is related to resistors R0, R1 and R3.

4. The linear regulator of claim 1, wherein in the self-starting circuit, the first pull-up branch comprises three PMOS transistors P6, P7 and P8, a source of the PMOS transistor P6 is connected to the operating power supply, a drain of the PMOS transistor P6 is connected to the gate and to the source of the PMOS transistor P7, a drain of the PMOS transistor P7 is connected to the gate and to the source of the PMOS transistor P8, and a drain of the PMOS transistor P8 is connected to the gate and to the output of the self-starting circuit;

the first current mirror comprises an NMOS tube N1 and an NMOS tube N3 which are the same in size, the grid electrode of the NMOS tube N1 is connected with the grid electrode of the NMOS tube N3 and is connected with the drain electrode of the NMOS tube N1 and a bias current IB, the source electrode of the NMOS tube N1 is grounded, the source electrode of the NMOS tube N3 is grounded, and the drain electrode of the NMOS tube N3 is connected to the first pull-up branch.

5. The linear regulator according to any one of claims 1-4, wherein the linear regulator further comprises a current limiting protection circuit, wherein the drain of the NMOS transistor N0 is connected to the operating power supply, the source is connected to the gate of the PMOS transistor P0, the output VB of the current limiting protection circuit is connected to the gate of the NMOS transistor N0, and the current limiting protection circuit further senses the output current of the PMOS transistor P0;

the bias current IB is connected with the current-limiting protection circuit through a second current mirror to provide a current threshold value, and the current-limiting protection circuit drives the NMOS transistor N0 to be conducted through an output end and pulls up the grid voltage of the PMOS transistor P0 when the output current is larger than the current threshold value, so that the output current is reduced until the output current is equal to the current threshold value.

6. The linear regulator of claim 5, wherein the bias current IB is connected to a second pull-up branch of the current-limiting protection circuit, which is composed of t2 PMOS transistors, through a second current mirror and is connected to the operating power supply, a source of the PMOS transistor P3 is connected to the operating power supply, a gate of the PMOS transistor P3 is connected to a gate of the PMOS transistor P0 and mirrors the output current, and a common terminal of the first pull-up branch and the second current mirror is connected to a drain of the PMOS transistor P3 and serves as an output terminal of the current-limiting protection circuit;

when the output current of the PMOS tube P0 is larger than the threshold current, the PMOS tube P3 pulls the voltage of the output end of the current-limiting protection circuit from VDD-t2 × VGS to VDD to drive the NMOS tube N0 to be conducted.

7. The linear regulator of claim 6, wherein the voltage regulator circuit comprises a voltage regulator circuit having a voltage regulator circuit with a voltage regulator circuit having a voltage regulator circuitA current threshold Iload of the output current_maxWhere IB is the current value of the bias current, m is the ratio of the sizes of the PMOS transistor P0 and the PMOS transistor P3, and n is the ratio of the output current to the input current in the second current mirror.

8. The linear regulator of claim 6, wherein in the current-limiting protection circuit, the second pull-up branch comprises two PMOS transistors P4 and P5, the source of the PMOS transistor P4 is connected to the operating power supply, the drain of the PMOS transistor P4 is connected to the gate and to the source of the PMOS transistor P5, and the drain of the PMOS transistor P5 is connected to the gate and to the output terminal of the current-limiting protection circuit;

the second current mirror comprises a current mirror with a size ratio of 1: n of an NMOS transistor N1 and an NMOS transistor N2, a gate of the NMOS transistor N1 is connected to a gate of the NMOS transistor N2 and connected to a drain of the NMOS transistor N1 and the bias current IB, a source of the NMOS transistor N1 is grounded, a source of the NMOS transistor N2 is grounded, and a drain of the NMOS transistor N2 is connected to the second pull-up branch.

9. The linear regulator according to claim 5, wherein the voltage generating circuit, the self-starting circuit and the current limiting protection circuit are respectively connected with high voltage tubes, and gates of the high voltage tubes are respectively controlled by a low voltage bias Vbias generated when the working power supply is powered on.

Technical Field

The invention relates to the field of linear voltage regulators, in particular to a non-reference self-starting linear voltage regulator.

Background

In practical integrated circuit applications, there are many times when it is necessary to convert a high voltage power supply to a stable low voltage power supply, and a common implementation is to use LDO (linear regulator), and the LDO generally uses PMOS as a power transistor to simplify the design of the circuit, as shown in fig. 1, which is a typical circuit structure of the LDO and uses the PMOS transistor MP0 as the power transistor. In the configuration of fig. 1, a reference voltage generating circuit is required to generate the reference voltage VREF, which increases the design difficulty and the chip area, resulting in an increase in cost.

Disclosure of Invention

The present invention provides a reference-free self-starting linear voltage regulator aiming at the above problems and technical requirements, and the technical scheme of the present invention is as follows:

a reference-less self-starting linear regulator, the linear regulator comprising a voltage generation circuit and a self-starting circuit, in the voltage generation circuit: the source electrode of the PMOS pipe P0 is connected with a working power supply, the drain electrode of the PMOS pipe P0 is grounded through a sampling circuit, the drain electrode of the PMOS pipe P0 is also connected with the voltage output end of the linear voltage stabilizer, and the sampling output end of the sampling circuit is connected with a feedback regulating circuit;

the bias current IB is connected with a first pull-up branch consisting of t1 PMOS tubes in the self-starting circuit through a first current mirror and is connected to a working power supply, the common end of the first pull-up branch and the first current mirror is used as the output end VA of the self-starting circuit and is connected with the cathode of a diode D0, and the anode of the diode D0 is connected with the grid electrode of a PMOS tube P0; the source electrode of a PMOS tube P9 in the self-starting circuit is connected with a working power supply, the drain electrode of the PMOS tube P9 in the self-starting circuit is connected with the output end VA of the self-starting circuit, and the grid electrode of the PMOS tube P9 is connected with the feedback regulating circuit;

when the working power supply is electrified, a bias current IB is generated, the bias current IB pulls the voltage of the output end VA of the self-starting circuit down to VDD-t1 multiplied by VGS, and then the voltage of the grid electrode of the PMOS tube P0 is pulled to VDD-t1 multiplied by VGS + V_D0And is turned on, VGS is the gate-source voltage of each PMOS tube, V_D0Is the forward conduction voltage drop of diode D0, VDD is the voltage of the operating power supply;

the output voltage of the voltage output end of the linear voltage stabilizer is increased to drive the voltage of the sampling output end to be increased until the feedback adjusting circuit drives the PMOS tube P9 to reach a stable current higher than the bias current IB under the action of the sampling output end, and the output end VA of the self-starting circuit is pulled high to enable the self-starting circuit to be closed.

In the feedback regulation circuit, a PMOS pipe P1 and a PMOS pipe P2 with the same size are connected to form a current mirror structure, the source electrode of the PMOS pipe P1 is connected with the source electrode of the PMOS pipe P2 and is connected with a working power supply, the grid electrode of the PMOS pipe P1 is connected with the grid electrode of the PMOS pipe P2 and is connected with the drain electrode of the PMOS pipe P1, the drain electrode of the PMOS pipe P1 is connected with the collector electrode of a triode Q0, the emitter electrode of the triode Q0 is grounded, the base electrode of the triode Q0 is connected with the base electrode of a triode Q1, the emitter electrode of the triode Q1 is grounded through a resistor R3, and the collector electrode of the triode Q1 is connected with the drain electrode of the PMOS pipe P2; the emitter of the triode Q2 is grounded, and the collector of the triode Q2 is connected with the base and is connected with the base of the triode Q0 and the sampling output end; the drain electrode of the PMOS tube P2 is connected with the anode of the diode D0 and the gate electrode of the PMOS tube P0, and the drain electrode of the PMOS tube P1 is connected with the gate electrode of the PMOS tube P9;

the size of the transistor Q0 is the same as that of the transistor Q2, and the size ratio of the transistor Q0 to the transistor Q1 is 1: when the voltage of the voltage output end is increased to drive the voltage of the sampling output end to be increased to exceed the starting voltage of the triode, the triodes Q0, Q1 and Q2 are all conducted, the PMOS tube P9 mirrors the current of the PMOS tube P1, and the stable current is I ═ Vt/lnN/R3, wherein Vt is thermal voltage.

The further technical scheme is that the sampling circuit comprises a resistor R1 and a resistor R0, the drain electrode of a PMOS tube P0 is grounded through the resistor R1 and the resistor R0 in sequence, the common end of the resistor R1 and the resistor R0 is used as a sampling output end, and the output voltage of the voltage output end of the linear voltage stabilizer is V_outVt × lnN (R1/R3) + Vbe2(1+ R1/R0), Vbe2 is the voltage across resistor R0, the output voltage of the linear regulator is related to resistors R0, R1 and R3, and the temperature coefficient of the output voltage is related to resistors R0, R1 and R3.

The further technical scheme is that in the self-starting circuit, the first pull-up branch comprises three PMOS tubes P6, P7 and P8, the source electrode of the PMOS tube P6 is connected with a working power supply, the drain electrode of the PMOS tube P6 is connected with the grid electrode and is connected with the source electrode of the PMOS tube P7, the drain electrode of the PMOS tube P7 is connected with the grid electrode and is connected with the source electrode of the PMOS tube P8, and the drain electrode of the PMOS tube P8 is connected with the grid electrode and is connected with the output end of the self-starting circuit;

the first current mirror comprises an NMOS tube N1 and an NMOS tube N3 which are the same in size, the grid electrode of the NMOS tube N1 is connected with the grid electrode of the NMOS tube N3 and connected with the drain electrode of the NMOS tube N1 and the bias current IB, the source electrode of the NMOS tube N1 is grounded, the source electrode of the NMOS tube N3 is grounded, and the drain electrode of the NMOS tube N3 is connected to the first pull-up branch.

The linear voltage stabilizer further comprises a current-limiting protection circuit, wherein the drain electrode of an NMOS tube N0 is connected with a working power supply, the source electrode of the NMOS tube N0 is connected with the grid electrode of a PMOS tube P0, the output end VB of the current-limiting protection circuit is connected with the grid electrode of an NMOS tube N0, and the current-limiting protection circuit also induces the output current on the PMOS tube P0;

the bias current IB is connected with the current-limiting protection circuit through the second current mirror to provide a current threshold value, and the current-limiting protection circuit drives the NMOS transistor N0 to be conducted through the output end when the output current is larger than the current threshold value, and pulls the grid voltage of the PMOS transistor P0 high, so that the output current is reduced until the output current is equal to the current threshold value.

The further technical scheme is that the bias current IB is connected with a second pull-up branch formed by t2 PMOS tubes in the current-limiting protection circuit through a second current mirror and is connected to a working power supply, the source electrode of the PMOS tube P3 is connected with the working power supply, the grid electrode of the PMOS tube P3 is connected with the grid electrode of the PMOS tube P0 and is subjected to image detection to output current, and the common end of the first pull-up branch and the second current mirror is connected with the drain electrode of the PMOS tube P3 and serves as the output end of the current-limiting protection circuit;

when the output current of the PMOS transistor P0 is larger than the threshold current, the PMOS transistor P3 pulls the voltage at the output end of the current-limiting protection circuit from VDD-t2 × VGS to VDD to drive the NMOS transistor N0 to be conducted.

The further technical scheme is that the current threshold value Iload of the output current_maxWhere IB is the current value of the bias current, m is the ratio of the sizes of the PMOS transistor P0 and the PMOS transistor P3, and n is the ratio of the output current to the input current in the second current mirror.

The current-limiting protection circuit comprises a first pull-up branch, a second pull-up branch, a third pull-up branch and a fourth pull-up branch, wherein the first pull-up branch comprises a PMOS tube P4 and a PMOS tube P5, the source electrode of the PMOS tube P4 is connected with a working power supply, the drain electrode of the PMOS tube P4 is connected with the grid electrode and connected with the source electrode of the PMOS tube P5, and the drain electrode of the PMOS tube P5 is connected with the grid electrode and connected with the output end of the current-limiting protection circuit;

the second current mirror comprises a current mirror with a size ratio of 1: n of an NMOS transistor N1 and an NMOS transistor N2, wherein the grid electrode of the NMOS transistor N1 is connected with the grid electrode of the NMOS transistor N2 and is connected with the drain electrode of the NMOS transistor N1 and the bias current IB, the source electrode of the NMOS transistor N1 is grounded, the source electrode of the NMOS transistor N2 is grounded, and the drain electrode of the NMOS transistor N2 is connected with the second pull-up branch.

The further technical scheme is that high-voltage tubes are respectively connected in the voltage generating circuit, the self-starting circuit and the current-limiting protection circuit, and grid electrodes of the high-voltage tubes are respectively controlled by low-voltage bias Vbias generated when the working power supply is electrified.

The beneficial technical effects of the invention are as follows:

the application discloses no benchmark is from linear voltage regulator who starts, and this linear voltage regulator built-in is from starting circuit can start on the basis that does not have reference voltage to close after stabilizing, owing to need not extra reference voltage and produce the circuit, consequently can simplify circuit structure, reduce chip area, improve the integrated level.

The linear voltage regulator is also internally provided with a current-limiting protection circuit, so that when the circuit is quickly electrified or short-circuited, the output current can be quickly limited within a current threshold, the maximum output current of the LDO can be accurately limited, and the safety of a chip is protected. And the current threshold can be set through the size of the device, so that the flexibility is higher. The high-voltage tube can be arranged to realize voltage resistance, so that the linear voltage stabilizer can be used in a high-voltage scene.

Drawings

Fig. 1 is a schematic diagram of a conventional linear regulator.

Fig. 2 is a schematic diagram of the structure of the reference-free self-starting linear regulator of the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses linear regulator of no benchmark self-starting, as shown in fig. 2, linear regulator includes voltage generation circuit and self-starting circuit, in voltage generation circuit: the source electrode of the PMOS pipe P0 is connected with the working power supply VDD, and the drain electrode is grounded through the sampling circuit. The drain of the PMOS transistor P0 is also connected to the voltage output terminal Vout of the linear regulator.

And the sampling output end VFB of the sampling circuit is connected with the feedback regulating circuit. Specifically, the sampling circuit comprises a resistor R1 and a resistor R0, the drain electrode of the PMOS transistor P0 is grounded through the resistor R1 and the resistor R0 in sequence, and the common end of the resistor R1 and the resistor R0 serves as a sampling output end.

The bias current IB is connected with a first pull-up branch consisting of t1 PMOS tubes in the self-starting circuit through a first current mirror and is connected to the working power supply VDD, the common end of the first pull-up branch and the first current mirror is used as the output end VA of the self-starting circuit and is connected with the cathode of a diode D0, and the anode of the diode D0 is connected with the grid electrode of the PMOS tube P0. The source electrode of the PMOS pipe P9 in the self-starting circuit is connected with the working power supply VDD, and the drain electrode is connected with the output end VA of the self-starting circuit. The gate of P9 is connected to the feedback regulation circuit.

When the working power supply VDD is electrified, a bias current IB is generated, the bias current IB pulls down the voltage of the output end VA of the self-starting circuit to VDD-t1 multiplied by VGS, and then the voltage of the grid electrode of the PMOS tube P0 is pulled to VDD-t1 multiplied by VGS + V_D0And is turned on, VGS is the gate-source voltage of each PMOS tube, V_D0Is the forward conduction voltage drop of diode D0 and VDD is the voltage of the operating power supply.

Specifically, in the self-starting circuit, the first pull-up branch comprises three PMOS transistors P6, P7 and P8, a source electrode of the PMOS transistor P6 is connected with a working power supply VDD, a drain electrode of the PMOS transistor P6 is connected with a gate electrode and is connected with a source electrode of the PMOS transistor P7, a drain electrode of the PMOS transistor P7 is connected with the gate electrode and is connected with a source electrode of the PMOS transistor P8, and a drain electrode of the PMOS transistor P8 is connected with the gate electrode and is connected with an output end VA of the self-starting circuit.

The first current mirror comprises an NMOS tube N1 and an NMOS tube N3 which are the same in size, the grid electrode of the NMOS tube N1 is connected with the grid electrode of the NMOS tube N3 and connected with the drain electrode of the NMOS tube N1 and the bias current IB, the source electrode of the NMOS tube N1 is grounded, the source electrode of the NMOS tube N3 is grounded, and the drain electrode of the NMOS tube N3 is connected to the first pull-up branch. When VDD is electrified and started, a bias current IB is generated, the bias current IB flows through an NMOS tube N1, an NMOS tube N3 mirrors the current of N1, the voltage of an output end VA of the self-starting circuit is pulled down to VDD-3VGS, and then the voltage of a grid electrode of a PMOS tube P0 is pulled downTo VDD-3VGS + V_D0And is turned on.

After the PMOS transistor P0 is turned on, the output voltage of the voltage output terminal Vout of the linear regulator starts to rise, and the rise of the output voltage of the voltage output terminal Vout drives the rise of the voltage of the sampling output terminal VFB until the feedback regulation circuit drives the PMOS transistor P9 to reach a stable current higher than the bias current IB under the action of the sampling output terminal VFB, and the output terminal VA of the self-starting circuit is pulled up to be close to VDD, so that the self-starting circuit is turned off.

In the feedback regulation circuit, PMOS tubes P1 and P2 with the same size are connected to form a current mirror structure, the source electrode of the PMOS tube P1 is connected with the source electrode of the PMOS tube P2 and connected with a working power supply VDD, and the grid electrode of the PMOS tube P1 is connected with the grid electrode of the PMOS tube P2 and connected with the drain electrode of the PMOS tube P1. The drain electrode of the PMOS pipe P1 is connected to the collector electrode of the triode Q0, the emitter electrode of the triode Q0 is grounded, the base electrode of the triode Q0 is connected with the base electrode of the triode Q1, the emitter electrode of the triode Q1 is grounded through a resistor R3, and the collector electrode of the triode Q1 is connected to the drain electrode of the PMOS pipe P2. The emitter of the triode Q2 is grounded, and the collector of the triode Q2 is connected with the base and is connected with the base of the triode Q0 and the sampling output end; the drain of the PMOS transistor P2 is connected to the anode of the diode D0 and the gate of the PMOS transistor P0, and the drain of the PMOS transistor P1 is connected to the gate of the PMOS transistor P9.

The size ratio of the transistor Q0 to the transistor Q1 is 1: n, the PMOS transistors P1 and P2 have the same size, so that the transistor Q0 has the same current as the transistor Q1, I ═ Vt × lnN)/R3, where Vt is the thermal voltage. Transistor Q0 is the same size as transistor Q2, so the current through Q2 is also I (Vt lnN)/R3. When the voltage of the voltage output end Vout rises to drive the voltage of the sampling output end VFB to rise to exceed the turn-on voltage Vbe of the triode, the triodes Q0, Q1 and Q2 are all turned on, and the PMOS transistor P9 mirrors the current of the PMOS transistor P1 and stabilizes the current as I ═ Vt × lnN)/R3. In the design, it is ensured that the stabilizing current I ═ Vt × lnN)/R3 of the PMOS transistor P9 is greater than the bias current IB, then VA is pulled up to near VDD, the start-up circuit is turned off, and finally the output voltage of the voltage output terminal Vout of the linear regulator is stabilized to V_outVt lnN (R1/R3) + Vbe2(1+ R1/R0), and Vbe2 is the voltage across resistor R0. Wherein Vt/lnN (R1/R3) is positive temperature coefficient voltageVbe2(1+ R1/R0) is a negative temperature coefficient voltage, and V can be adjusted by adjusting R0, R1 and R3_outSize and V of_outI.e., the output voltage of the linear regulator is associated with resistors R0, R1, and R3, and the temperature coefficient of the output voltage is associated with resistors R0, R1, and R3.

When the power supply is powered up rapidly or the output Iload is suddenly short-circuited, if the output current of the linear regulator is not limited, the PMOS transistor P0 generates a large current reaching the ampere level to generate a great amount of heat, which may burn out the P0, and even the output voltage Vout may cause an overshoot phenomenon to burn out electronic components downstream. Therefore, the linear voltage regulator of the present application further includes a current limiting protection circuit. The drain electrode of the NMOS tube N0 is connected with a working power supply VDD, the source electrode is connected with the grid electrode of the PMOS tube P0, the output end VB of the current-limiting protection circuit is connected with the grid electrode of the NMOS tube N0, and the current-limiting protection circuit also senses the output current Iload on the PMOS tube P0.

The bias current IB is connected with the current-limiting protection circuit through the second current mirror to provide a current threshold value, and the current-limiting protection circuit drives the NMOS tube N0 to be conducted through the output end and pulls high the grid voltage of the PMOS tube P0 when the output current Iload is larger than the current threshold value, so that the output current Iload is reduced until the output current Iload is equal to the current threshold value.

The bias current IB is connected with a second pull-up branch consisting of t2 PMOS tubes in the current-limiting protection circuit through a second current mirror and is connected to the working power supply VDD, and the source electrode of the PMOS tube P3 is connected with the working power supply VDD. The grid electrode of the PMOS pipe P3 is connected with the grid electrode of the PMOS pipe P0 and mirrors the detected output current Iload. The common end of the first pull-up branch and the second current mirror is connected with the drain electrode of the PMOS pipe P3 and is used as the output end VB of the current-limiting protection circuit. When the output current Iload of the PMOS tube P0 is larger than the threshold current, the PMOS tube P3 pulls up the voltage of the output end VB of the current-limiting protection circuit from VDD-t2 × VGS to VDD to drive the NMOS tube N0 to be conducted, the NMOS tube N0 pulls up the voltage of the gate VG of the PMOS tube P0, and therefore VGS of P0 is reduced, and the output current Iload is limited.

In the current-limiting protection circuit, the second pull-up branch comprises two PMOS tubes P4 and P5, the source electrode of the PMOS tube P4 is connected with the working power supply VDD, the drain electrode of the PMOS tube P4 is connected with the grid electrode and the source electrode of the PMOS tube P5, and the drain electrode of the PMOS tube P5 is connected with the grid electrode and the output end VB of the current-limiting protection circuit. The second current mirror comprises a current mirror with a size ratio of 1: n of an NMOS transistor N1 and an NMOS transistor N2, wherein the grid electrode of the NMOS transistor N1 is connected with the grid electrode of the NMOS transistor N2 and is connected with the drain electrode of the NMOS transistor N1 and the bias current IB, the source electrode of the NMOS transistor N1 is grounded, the source electrode of the NMOS transistor N2 is grounded, and the drain electrode of the NMOS transistor N2 is connected with the second pull-up branch.

The addition of the PMOS tubes P4 and P5 can make the voltage of the output end VB of the current limiting protection circuit be VDD-t2 × VGS ═ VDD-2 × VGS under the normal working condition of the circuit, which is close to the voltage of VDD, so when the current of the PMOS tube P3 is larger than that of N2 when rapid power-on or short-circuit occurs, the voltage of the node VB can be pulled to VDD more rapidly, and the response speed of current limiting is increased.

And from this, a current threshold value Iload of the output current Iload can be obtained_maxWhere IB is the current value of the bias current IB, m is the ratio of the sizes of the PMOS transistor P0 and the PMOS transistor P3, and n is the ratio of the output current to the input current in the second current mirror, the current threshold of the output current can be flexibly changed by changing the size of m, n or IB.

In addition, the voltage generation circuit, the self-starting circuit and the current-limiting protection circuit are respectively connected with a high-voltage tube, and the grid electrode of each high-voltage tube is respectively controlled by a low-voltage bias Vbias generated when the working power supply is electrified, so that the linear voltage regulator can be used in a high-voltage scene. Specifically, as shown in fig. 2, in the voltage generating circuit, a high-voltage tube N is connected between a PMOS transistor P1 and a transistor Q0_HV3A high-voltage tube N is connected between the PMOS tube P2 and the triode Q1_HV4. In the self-starting circuit, a high-voltage tube N is connected between the first pull-up branch and the first current mirror_HV2Specifically, a high-voltage tube N is connected between the PMOS tube P8 and the NMOS tube N3_HV2. In the current-limiting protection circuit, a high-voltage tube N is connected between the second pull-up branch and the second current mirror_HV1Specifically, a high-voltage tube N is connected between the PMOS tube P5 and the NMOS tube N2_HV1。

The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.