阅读说明：本技术 带隙基准电压产生电路、集成电路及电子设备 (Bandgap reference voltage generating circuit, integrated circuit, and electronic device ) 是由 韩书光 范明浩 于 2021-10-27 设计创作，主要内容包括：本公开涉及一种带隙基准电压产生电路、集成电路及电子设备,所述电路包括：电压产生单元,用于产生正温度系数电压及负温度系数电压,根据所述正温度系数电压及负温度系数电压产生带隙基准电压；放大器,用于对所述带隙基准电路进行电压钳位,其中,所述放大器的失调电压与温度成正比。本公开实施例通过设置放大器的失调电压与温度成正比,大大降低了电路复杂度,由于不再需要很大的密勒补偿电容,进一步降低了电路复杂度,并且避免了chopping噪声,提高了基准电压的精度。(The present disclosure relates to a bandgap reference voltage generating circuit, an integrated circuit and an electronic device, the circuit including: the voltage generating unit is used for generating positive temperature coefficient voltage and negative temperature coefficient voltage and generating band gap reference voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage; and the amplifier is used for clamping the voltage of the band gap reference circuit, wherein the offset voltage of the amplifier is in direct proportion to the temperature. The embodiment of the disclosure greatly reduces the circuit complexity by setting the offset voltage of the amplifier to be in direct proportion to the temperature, further reduces the circuit complexity because a large Miller compensation capacitor is not needed any more, avoids chopping noise, and improves the precision of the reference voltage.)

1. A bandgap reference voltage generating circuit, the circuit comprising:

the voltage generating unit is used for generating positive temperature coefficient voltage and negative temperature coefficient voltage and generating band gap reference voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage;

and the amplifier is connected with the voltage generation unit and used for clamping the voltage of the voltage generation unit, wherein the offset voltage of the amplifier is in direct proportion to the temperature.

2. The circuit of claim 1, wherein the voltage generating unit comprises a zeroth BJT transistor, a first BJT transistor, a second BJT transistor, a first branch resistor, a second resistor, and a third resistor, wherein,

the emitter of the zero BJT transistor is used for receiving a power supply voltage, the base of the zero BJT transistor is connected with the output end of the amplifier, and the collector of the zero BJT transistor is connected with the first end of the third resistor and used for outputting the band-gap reference voltage;

a second end of the third resistor is connected to a first end of the first branch resistor and a first end of the second branch resistor, a second end of the first branch resistor is connected to a collector of the first BJT transistor, a base of the first BJT transistor and a first input end of the amplifier, a second end of the second branch resistor is connected to a first end of the second resistor and a second input end of the amplifier,

the second end of the second resistor is connected with the collector of the second BJT transistor and the base of the second BJT transistor,

an emitter of the first BJT transistor and an emitter of the second BJT transistor are grounded.

3. The circuit of claim 2, wherein the first BJT transistor and the second BJT transistor are NPN type, and the zeroth BJT transistor is PNP type.

4. The circuit of any of claim 2, wherein the amplifier comprises a third BJT transistor, a fourth BJT transistor, a fifth BJT transistor, a sixth BJT transistor, a seventh BJT transistor, a first NMOS transistor, wherein,

a base of the third BJT transistor is used as a first input terminal of the amplifier, a base of the fourth BJT transistor is used as a second input terminal of the amplifier, an emitter of the third BJT transistor is connected with an emitter of the fourth BJT transistor,

an emitter of the fifth BJT transistor, an emitter of the sixth BJT transistor, and an emitter of the seventh BJT transistor are connected to receive a power supply voltage,

the base of the fifth BJT transistor, the base of the sixth BJT transistor and the base of the seventh BJT transistor are connected with each other,

the base of the sixth BJT transistor is further connected to the collector of the sixth BJT transistor and the source of the first NMOS transistor,

a collector of the fifth BJT transistor is connected to a collector of the third BJT transistor and a gate of the first NMOS transistor, a drain of the first NMOS transistor is grounded,

and the collector of the seventh BJT transistor is connected with the collector of the fourth BJT transistor and used as the output end of the amplifier.

5. The circuit of claim 4, wherein the amplifier further comprises a second NMOS transistor and an eighth BJT transistor,

an emitter of the eighth BJT transistor is connected to an emitter of the fifth BJT transistor, an emitter of the sixth BJT transistor, and an emitter of the seventh BJT transistor, for receiving the power supply voltage,

the collector of the eighth BJT transistor, the base of the eighth BJT transistor and the source of the second NMOS transistor are connected as the output end of the amplifier,

and the grid electrode of the second NMOS transistor is connected with the collector electrode of the seventh BJT transistor and the collector electrode of the fourth BJT transistor, and the drain electrode of the second NMOS transistor is grounded.

6. The circuit of claim 4 or 5, wherein the amplifier further comprises a fourth resistor, and a first end of the fourth resistor is connected to the collector of the third BJT transistor and the collector of the fourth BJT transistor.

7. The circuit of claim 6, wherein a ratio of an area of the first BJT transistor to a sum of areas of a third BJT transistor and a fourth BJT transistor is 1: n and N are integers, wherein the resistance values of the fourth resistor and the second resistor satisfy the following relation:

r4 ═ N/2 · R2, where R4 represents the resistance value of the fourth resistor, and R2 represents the resistance value of the second resistor.

8. An integrated circuit comprising the bandgap reference voltage generating circuit as claimed in any one of claims 1 to 7.

9. An electronic device, characterized in that the electronic device comprises an integrated circuit as claimed in claim 8.

Technical Field

The present disclosure relates to the field of technology, and in particular, to a bandgap reference voltage generating circuit, an integrated circuit, and an electronic device.

Background

The function of a Bandgap Reference (BGR) is to generate a Reference voltage. It is called a bandgap reference because its reference voltage is not much different from the bandgap voltage of silicon. The band gap reference is a key component in an analog circuit and is widely applied to the fields of analog-to-digital converters, sensors, the Internet of things, wearable equipment and the like.

The reference voltage generated by the bandgap reference is affected by process variations. For example, transistor mismatches, process corners, all affect the absolute value and temperature coefficient of the reference voltage. In order to ensure the accuracy of the reference voltage, it is usually necessary to regulate (trim) the reference voltage. Conventional trim methods include multi-point trim and single-point trim (single-trim). The advantage of multi-point trim is that it is possible to achieve very accurate reference voltages, with the disadvantage that the trim process is very cumbersome and requires trim to be performed at multiple temperatures. In contrast, a single trim has the advantage that the trim process is very simple and convenient, and can be completed at room temperature, but has the disadvantage that the circuit needs to be designed very carefully to ensure that a single trim can be achieved.

However, the bandgap reference circuit in the related art has low accuracy due to the influence of the offset voltage, and it is difficult to implement single trim.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a bandgap reference voltage generating circuit, the circuit including:

the voltage generating unit is used for generating positive temperature coefficient voltage and negative temperature coefficient voltage and generating band gap reference voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage;

and the amplifier is connected with the voltage generation unit and used for clamping the voltage of the voltage generation unit, wherein the offset voltage of the amplifier is in direct proportion to the temperature.

In one possible embodiment, the voltage generating unit includes a zeroth BJT transistor, a first BJT transistor, a second BJT transistor, a first branch resistor, a second resistor, and a third resistor, wherein,

the emitter of the zero BJT transistor is used for receiving a power supply voltage, the base of the zero BJT transistor is connected with the output end of the amplifier, and the collector of the zero BJT transistor is connected with the first end of the third resistor and used for outputting the band-gap reference voltage;

a second end of the third resistor is connected to a first end of the first branch resistor and a first end of the second branch resistor, a second end of the first branch resistor is connected to a collector of the first BJT transistor, a base of the first BJT transistor and a first input end of the amplifier, a second end of the second branch resistor is connected to a first end of the second resistor and a second input end of the amplifier,

the second end of the second resistor is connected with the collector of the second BJT transistor and the base of the second BJT transistor,

an emitter of the first BJT transistor and an emitter of the second BJT transistor are grounded.

In one possible embodiment, the first BJT transistor and the second BJT transistor are NPN type, and the zeroth BJT transistor is PNP type.

In one possible embodiment, the amplifier includes a third BJT transistor, a fourth BJT transistor, a fifth BJT transistor, a sixth BJT transistor, a seventh BJT transistor, and a first NMOS transistor, wherein,

a base of the third BJT transistor is used as a first input terminal of the amplifier, a base of the fourth BJT transistor is used as a second input terminal of the amplifier, an emitter of the third BJT transistor is connected with an emitter of the fourth BJT transistor,

an emitter of the fifth BJT transistor, an emitter of the sixth BJT transistor, and an emitter of the seventh BJT transistor are connected to receive a power supply voltage,

the base of the fifth BJT transistor, the base of the sixth BJT transistor and the base of the seventh BJT transistor are connected with each other,

the base of the sixth BJT transistor is further connected to the collector of the sixth BJT transistor and the source of the first NMOS transistor,

a collector of the fifth BJT transistor is connected to a collector of the third BJT transistor and a gate of the first NMOS transistor, a drain of the first NMOS transistor is grounded,

and the collector of the seventh BJT transistor is connected with the collector of the fourth BJT transistor and used as the output end of the amplifier.

In one possible embodiment, the amplifier further comprises a second NMOS transistor and an eighth BJT transistor,

an emitter of the eighth BJT transistor is connected to an emitter of the fifth BJT transistor, an emitter of the sixth BJT transistor, and an emitter of the seventh BJT transistor, for receiving the power supply voltage,

the collector of the eighth BJT transistor, the base of the eighth BJT transistor and the source of the second NMOS transistor are connected as the output end of the amplifier,

and the grid electrode of the second NMOS transistor is connected with the collector electrode of the seventh BJT transistor and the collector electrode of the fourth BJT transistor, and the drain electrode of the second NMOS transistor is grounded.

In one possible embodiment, the amplifier further includes a fourth resistor, and a first end of the fourth resistor is connected to the collector of the third BJT transistor and the collector of the fourth BJT transistor.

In one possible embodiment, the ratio of the area of the first BJT transistor to the sum of the areas of the third BJT transistor and the fourth BJT transistor is 1: n and N are integers, wherein the resistance values of the fourth resistor and the second resistor satisfy the following relation:

r4 ═ N/2 · R2, where R4 represents the resistance value of the fourth resistor, and R2 represents the resistance value of the second resistor.

According to an aspect of the present disclosure, there is provided an integrated circuit including the bandgap reference voltage generating circuit.

According to an aspect of the present disclosure, there is provided an electronic device including the integrated circuit.

The band-gap reference voltage generating circuit of the embodiment of the disclosure does not need to correct the amplifier offset independently, and does not need to use an extra chopping circuit and notch filter for correcting the amplifier offset, thereby greatly reducing the circuit complexity.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a block diagram of a bandgap reference voltage generating circuit according to an embodiment of the present disclosure.

Fig. 2a shows a schematic diagram of a voltage generation unit according to an embodiment of the present disclosure.

Fig. 2b shows a schematic diagram of an amplifier according to an embodiment of the present disclosure.

FIG. 3 shows a block diagram of an electronic device in accordance with an embodiment of the present disclosure.

FIG. 4 shows a block diagram of an electronic device in accordance with an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

In the description of the present disclosure, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, indicate orientations or positional relationships that are based on the orientations or positional relationships illustrated in the drawings, are used for convenience in describing the present disclosure and to simplify the description, and do not indicate or imply that the circuits or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

The bandgap reference circuit uses an amplifier for voltage clamping, generally, the amplifier has an input offset voltage due to the introduction of the amplifier, and the offset voltage is random in magnitude, completely depends on process deviation, seriously affects the precision of the reference voltage, and causes difficulty in realizing a single trim function. In order to realize the single trim function, the related art proposes a chop-based technique to eliminate the amplifier offset voltage, for example, chop the amplifier first, and then Filter the chop-processed voltage by using a Notch Filter (Notch Filter), which has a good effect, but its disadvantages are also obvious. Furthermore, the bias voltage of the amplifier needs to be generated by an additional bias circuit, which further increases the circuit complexity. In addition, chopping circuits introduce high frequency noise that, while filtered out by notch filters, potential parasitic capacitances can still couple this high frequency noise to the reference voltage, ultimately affecting the accuracy of the reference voltage. Furthermore, the introduction of notch filter causes the loop phase margin to deteriorate, which requires the addition of a very large miller compensation capacitance (15pF), which wastes a large chip area.

The disclosed embodiment provides a bandgap reference voltage generating circuit, which includes: the voltage generating unit is used for generating positive temperature coefficient voltage and negative temperature coefficient voltage and generating band gap reference voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage; the amplifier is connected with the voltage generating unit and used for clamping the voltage of the voltage generating unit, wherein the offset voltage of the amplifier is in direct proportion to the temperature, the fact that the amplifier offset only generates a PTAT (Proportional to Absolute temperature) error at the bandgap reference voltage is ensured, the single trim function of the bandgap reference can eliminate the PTAT error at the bandgap reference voltage, therefore, the single trim can eliminate the error of the bandgap reference voltage caused by the amplifier offset together, the bandgap reference voltage generating circuit of the embodiment of the disclosure does not need to correct the amplifier offset independently, does not need to use an additional chopping circuit and notch filter for correcting the amplifier offset, greatly reduces the circuit complexity, and does not need a large Miller compensation capacitor, the circuit complexity is further reduced, the chopping noise is avoided, and the precision of the reference voltage is improved.

Fig. 1 shows a block diagram of a bandgap reference voltage generating circuit according to an embodiment of the present disclosure.

In some possible implementations, the bandgap reference voltage generating circuit may be applied to an integrated circuit and configured as a processing component. In one example, a processing component includes, but is not limited to, a single processor, or discrete components, or a combination of a processor and discrete components. The processor may comprise a controller having functionality to execute instructions in an electronic device, which may be implemented in any suitable manner, e.g., by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, Application Specific Integrated Circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

In some possible implementations, the bandgap reference voltage generating circuit may be applied to a terminal device or a server or other processing device. The terminal device may be a User Equipment (UE), a mobile device, a User terminal, a handheld device, a computing device, or a vehicle-mounted device, and some examples of the terminal device are as follows: a Mobile Phone (Mobile Phone), a tablet computer, a notebook computer, a palm computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in Industrial Control (Industrial Control), a wireless terminal in unmanned driving (self driving), a wireless terminal in Remote Surgery (Remote medical Surgery), a wireless terminal in Smart Grid, a wireless terminal in Transportation Safety, a wireless terminal in Smart City (Smart City), a wireless terminal in Smart Home (Smart Home), a wireless terminal in car networking, and the like. For example, the server may be a local server or a cloud server.

As shown in fig. 1, the bandgap reference voltage generating circuit 1 includes:

a voltage generating unit 10 for generating a positive temperature coefficient voltage and a negative temperature coefficient voltage and generating a bandgap reference voltage V according to the positive temperature coefficient voltage and the negative temperature coefficient voltage_BG；

And an amplifier 20 connected to the voltage generating unit 10 for clamping the voltage of the voltage generating unit 10, wherein an offset voltage of the amplifier 20 is proportional to the temperature.

The specific implementation manner of the voltage generation unit and the amplifier is not limited in the embodiments of the present disclosure, and those skilled in the art may configure the voltage generation unit and the amplifier as long as the voltage generation unit is configured to generate a positive temperature coefficient voltage and a negative temperature coefficient voltage, generate a bandgap reference voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage, and the amplifier is configured to perform a voltage clamping function on the voltage generation unit and ensure that an offset voltage of the amplifier is in direct proportion to a temperature.

The positive temperature coefficient voltage of the disclosed embodiment is that the voltage increases with the temperature rise, the negative temperature coefficient voltage is that the voltage decreases with the temperature rise, and the zero temperature coefficient voltage is that the voltage does not change with the temperature.

A possible implementation of the voltage generating unit 10, and the amplifier 20 is exemplarily described below.

The working principle of the band gap reference is as follows: the voltage with the positive temperature coefficient and the voltage with the negative temperature coefficient are generated firstly, and then the two are added, so that the voltage with the zero temperature coefficient is realized. The voltage generating unit 10 is exemplarily described below based on the operating principle of the bandgap reference.

Referring to fig. 2a, fig. 2a is a schematic diagram illustrating a voltage generation unit according to an embodiment of the disclosure.

In one possible embodiment, as shown in fig. 2a, the voltage generating unit 10 may include a first BJT (Bipolar Junction Transistor) Transistor Q₁A second BJT transistor Q₂The zeroth BJT transistor Q₀A first branch resistor R_1AA second branch resistor R_1BA second resistor R₂A third resistor R₃Wherein, in the step (A),

the zeroth BJT transistor Q₀Emitter for receiving a supply voltage V_DDSaid zeroth BJT transistor Q₀Is connected to the output of said amplifier 20, said zeroth BJT transistor Q₀Is connected to the third resistor R₃For outputting said bandgap reference voltage V_BG；

The third resistor R₃Is connected to the first branch resistor R_1AFirst terminal and the second branch resistance R_1BThe first branch resistance R_1AIs connected to the first BJT transistor Q₁The collector of (1), the first BJT transistor Q₁And a first input terminal of the amplifier 20, the second branch resistor R_1BIs connected to the second resistor R₂And a second input of said amplifier 20,

the second resistor R₂Is connected to the second BJT transistor Q₂Collector of said second BJT transistor Q₂The base electrode of (a) is formed,

the first BJT transistor Q₁And said second BJT transistor Q₂The emitter of (2) is grounded.

Positive temperature coefficient and negative temperature coefficient voltage usable first BJT transistor Q of the disclosed embodiments₁A second BJT transistor Q₂Generating, a first BJT transistor Q₁A second BJT transistor Q₂The current density of (1: N, N being a positive integer) is in a fixed ratio, and the positive temperature coefficient voltage can be the first BJT transistor Q₁A second BJT transistor Q₂The negative temperature coefficient voltage of the base-emitter voltage drop difference can be the first BJT transistor Q₁A second BJT transistor Q₂The base-emitter voltage drop of any BJT transistor in the series.

Through the voltage generating unit 10, the embodiment of the disclosure can conveniently generate zero temperature coefficient voltage, and has small circuit area and low cost.

It should be noted that when the amplifier 20 has an input offset voltage V_OSA reference voltage V generated by a bandgap reference_BGCan be expressed as:

wherein, V_TIs a thermal voltage, N is a first BJT transistor Q₁A second BJT transistor Q₂Area ratio of (a). From the above formula, it can be seen that if the offset voltage V of the amplifier 20 is larger_OSFor a PTAT voltage, then it is at V_BGThe error generated in (f) is also a PTAT error. This PTAT error can be easily removed by a single trim, for example, by applying a third resistor R to the resistor at room temperature₃Performing trim and letting the reference voltage V_BGAnd (5) restoring to an ideal value. Due to the third resistor R₃The current in is a PTAT current, so that the trim can generate a PTAT voltage to cancel out V_BGIn order to increase the bandgap reference voltage V_BGThe accuracy of (2).

In one possible embodiment, the first BJT transistor Q₁And the second BJT transistor Q₂Being of NPN type, the zero BJT transistor Q₀Is PNP type.

Referring to fig. 2b, fig. 2b shows a schematic diagram of an amplifier according to an embodiment of the disclosure.

In one possible embodiment, as shown in fig. 2b, the amplifier 20 may include a third BJT transistor Q₃Fourth BJT transistor Q₄The fifth BJT transistor Q₅Sixth BJT transistor Q₆Seventh BJT transistor Q₇A first NMOS transistor M₁Wherein, in the step (A),

the third BJT transistor Q₃As a first input of said amplifier 20, said fourth BJT transistor Q₄As a second input of said amplifier 20, said third BJT transistor Q₃Is connected to said fourth BJT transistor Q₄The emitter of (a) is provided,

the fifth BJT transistor Q₅Said sixth BJT transistor Q₆Said seventh BJT transistor Q₇Is connected to the emitter for receiving a supply voltage V_DD，

The fifth BJT transistor Q₅Base of (3), said sixth BJT transistor Q₆Said seventh BJT transistor Q₇The base electrodes of the first and second electrodes are connected with each other,

the sixth BJT transistor Q₆Is further connected to said sixth BJT transistor Q₆And the first NMOS transistor M₁The source of (a) is provided,

the fifth BJT transistor Q₅Is connected to the third BJT transistor Q₃And the first NMOS transistor M₁The first NMOS transistor M₁The drain of (a) is grounded,

the seventh BJT transistor Q₇Is connected to the fourth BJT transistor Q₄As an output of said amplifier 20.

The amplifier 20 provided by the embodiment of the present disclosure has a PTAT characteristic, and can be used in cooperation with the voltage generation unit 10 to enable the bandgap voltage generation circuit to implement single-point adjustment, thereby improving the precision of the reference voltage.

The principle of amplifier 20 having the offset voltage of PTAT above is exemplified below.

As can be seen from FIG. 2b, the input offset voltage of the amplifier 20 is only dependent on the third BJT transistor Q₃Fourth BJT transistor Q₄And a fifth BJT transistor Q₅And seventh BJT transistor Q₇Of the first and second sub-arrays. Here, the I-V relationship of the BJT transistor can be expressed as:

wherein, V_GRepresents the bandgap voltage of silicon, T represents the temperature, T_rDenotes an arbitrary reference temperature, eta denotes a process-related parameter, I_CRepresenting the collector current.

Due to the fifth BJT transistor Q₅And seventh BJT transistor Q₇Having the same voltage V_BEThus the fifth BJT transistor Q₅And seventh BJT transistor Q₇Only a different I will result from a mismatch between_C(T) and I_C(T_r) And the other parameters in the above formula (2) are the same. In this case, the following formula is obtained:

similarly, in equation (2), the third BJT transistor Q₃Fourth BJT transistor Q₄Can lead to different V_BE(T)、V_BE(T_r)、I_C(T)、I_C(T_r) And the other parameters in the formula (2) are the same. In addition, transistor Q is connected to the third BJT₃Fourth BJT transistor Q₄Are respectively equal to the fifth BJT transistor Q₅And seventh BJT transistor Q₇The current (the relationship of the upper and lower series), therefore, the following can be obtained:

combining formula (2) and formula (4), one can obtain:

the above equation (5) shows that the input offset voltage of the proposed amplifier 20 is a PTAT voltage.

In addition, it should be noted that in order to generate the fifth BJT transistor Q₅And seventh BJT transistor Q₇So that the fifth BJT transistor Q cannot be turned on₅Direct diode connection, which causes base current to flow into collector, thus destroying the current mirror fifth BJT transistor Q₅And seventh BJT transistor Q₇The current matching of (1) is such that the offset voltage of the amplifier 20 is no longer the PTAT voltage, because the current gain β of the BJT transistor has a large nonlinearity, which may cause a large nonlinearity in the base current, and thus, the PTAT characteristic of the offset voltage of the amplifier 20 is seriously damaged.

In contrast, in fig. 2b, the disclosed embodiment introduces an additional first NMOS transistor M₁And a sixth BJT transistor Q₆To generate a fifth BJT transistor Q₅And seventh BJT transistor Q₇The base voltage of (1). Since the first NMOS transistor M₁The gate of the transistor (Q) has no leakage, so that the current mirror of the fifth BJT transistor (Q) can be well ensured₅And seventh BJT transistor Q₇Current matching of (2).

In a possible implementation, the amplifier 20 may further include a second NMOS transistor M₂And eighth BJT transistor Q₈，

The eighth BJT transistor Q₈Is connected to the fifth BJT transistor Q₅Said sixth BJT transistor Q₆Said seventh BJT transistor Q₇For receiving said supply voltage V_DD，

The eighth BJT transistor Q₈Collector of, the eighth BJT transistor Q₈And the second NMOS transistor M₂Is connected as an output of said amplifier 20,

the second NMOS transistor M₂Is connected to the seventh BJT transistor Q₇And said fourth BJT transistor Q₄The second NMOS transistor M₂Is grounded.

The embodiment of the disclosure arranges a second NMOS transistor M₂And eighth BJT transistor Q₈The current mirror, i.e. the fifth BJT transistor Q, can be ensured₅And seventh BJT transistor Q₇Having similar collector voltage to further improve the current mirror fifth BJT transistor Q₅And seventh BJT transistor Q₇Current matching of (2).

As shown in fig. 2a and 2b, since the sixth BJT transistor Q₆Is equal to the fifth BJT transistor Q₅And seventh BJT transistor Q₇While the eighth BJT transistor Q₈Is equal to the zeroth BJT transistor Q₀Thus, the sixth BJT transistor Q₆And eighth BJT transistor Q₈The current of the same is accurately controlled.

In one possible embodiment, the third BJT transistor Q₃Fourth BJT transistor Q₄Being of NPN type, the fifth BJT transistor Q₅Sixth BJT transistor Q₆Seventh BJT transistor Q₇The eighth BJT transistor Q₈Is PNP type.

In a possible embodiment, the amplifier 20 further comprises a fourth resistor R₄Said fourth resistor R₄Is connected to said third BJT transistor Q₃And said fourth BJT transistor Q₄The collector electrode of (1).

The embodiment of the disclosure sets the fourth resistor R₄And a bias circuit is replaced, so that the circuit area and the cost are further saved.

The embodiment of the present disclosure can ensure that the current of the amplifier 20 is exactly equal to the current of the bandgap reference main branch as long as the tail resistance of the amplifier 20 is in a certain proportion to the resistance of the bandgap reference main branch, and the exact equality relationship can be established at any temperature. In this case, the amplifier 20 does not require an additional bias circuit, thereby further reducing circuit complexity.

The disclosed embodiment employs a tail resistor, i.e., a fourth resistor R₄Instead of a complicated biasing circuit, a fourth resistor R₄Similar to the second resistor R in FIG. 2a₂. In FIG. 2a, transistor Q is due to the first BJT₁A second BJT transistor Q₂So that the second resistance R is 1: N₂The current at is (V)_TlnN)/R₂. Similarly, in fig. 2a and 2b, assume a first BJT transistor Q₁Area and third BJT transistor Q₃Fourth BJT transistor Q₄The ratio of the total areas is also 1: N, and assuming that R4 ═ R2, then the fourth resistor R is₄The current at will also be (V)_TlnN)/R₂. In one example, the first BJT transistor Q may be configured for design convenience₁Area and third BJT transistor Q₃Fourth BJT transistor Q₄The ratio of the total area is set to 1:2 instead of 1: N. At this time, the fourth resistor R may be connected₄The fourth resistor R is secured by setting R4 to (N/2) · R2₄The current at is (2/N) · (V)_TlnN)/R₂. This is achieved by using the tail resistor, i.e. the fourth resistor R₄The method of replacing the bias circuit easily achieves precise control of the amplifier 20 tail current so that the amplifier 20 tail current is exactly proportional to the bandgap reference main branch current.

Since the disclosed embodiment does not use a complicated bias circuit, the circuit complexity is significantly reduced. The voltage generating unit 10 of the embodiment of the present disclosure is provided with the zeroth BJT transistor Q₀A first BJT transistor Q₁A second BJT transistor Q₂For BJT transistors, the input offset voltage of the amplifier 20 can be guaranteed to be PTAT voltage, and the amplifier 20 can be made to have no need for additional bias circuit.

The disclosed embodiment proposes a scheme by making the amplifier 2BJT transistors are adopted for the 0 input tube and the current mirror, and the input offset voltage of the amplifier 20 is PTAT voltage. The significance of this feature is that it ensures that the amplifier 20 is detuned only at V_BGA PTAT error is generated. The single trim function due to the bandgap reference can eliminate V_BGA PTAT error, so that a single trim can detune amplifier 20 by a resulting V_BGThe error is eliminated. That is, the disclosed embodiments do not require separate correction for amplifier 20 detuning, nor do they require additional chopping circuitry and notch filter to correct amplifier 20 detuning. This also greatly reduces circuit complexity, avoids chopping noise, and eliminates the need for large miller compensation capacitors.

The amplifier 20 proposed by the embodiment of the present disclosure has another advantage in that it does not require an additional bias circuit. Instead, its bias current can be precisely controlled by the tail resistor. Since the amplifier 20 has a special relationship with the main bandgap reference branch, as long as the tail resistance of the amplifier 20 is in a certain proportion to the resistance of the main bandgap reference branch, it can be ensured that the current of the amplifier 20 is exactly equal to the current of the main bandgap reference branch, and this exact equality relationship can be established at any temperature. In this case, the circuit complexity is further reduced since the amplifier 20 does not require an additional bias circuit.

According to an aspect of the present disclosure, there is provided an integrated circuit including the bandgap reference voltage generating circuit.

According to an aspect of the present disclosure, there is provided an electronic device including the integrated circuit.

The electronic device may be provided as a terminal, server, or other form of device.

Referring to fig. 3, fig. 3 is a block diagram of an electronic device according to an embodiment of the disclosure.

For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like terminal.

Referring to fig. 3, electronic device 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input/output (I/O) interface 812, sensor component 814, and communication component 816.

The processing component 802 generally controls overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components 802 may include one or more processors 820 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

The memory 804 is configured to store various types of data to support operations at the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

The power supply component 806 provides power to the various components of the electronic device 800. The power components 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.

The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the electronic device 800 is in an operation mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.

The sensor assembly 814 includes one or more sensors for providing various aspects of state assessment for the electronic device 800. For example, the sensor assembly 814 may detect an open/closed state of the electronic device 800, the relative positioning of components, such as a display and keypad of the electronic device 800, the sensor assembly 814 may also detect a change in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, orientation or acceleration/deceleration of the electronic device 800, and a change in the temperature of the electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include a light sensor, such as a Complementary Metal Oxide Semiconductor (CMOS) or Charge Coupled Device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 may access a wireless network based on a communication standard, such as a wireless network (WiFi), a second generation mobile communication technology (2G) or a third generation mobile communication technology (3G), or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.

In an exemplary embodiment, a non-transitory computer-readable storage medium, such as the memory 804, is also provided that includes computer program instructions executable by the processor 820 of the electronic device 800 to perform the above-described methods.

Referring to fig. 4, fig. 4 is a block diagram of an electronic device according to an embodiment of the disclosure.

For example, the electronic device 1900 may be provided as a server. Referring to fig. 4, electronic device 1900 includes a processing component 1922 further including one or more processors and memory resources, represented by memory 1932, for storing instructions, e.g., applications, executable by processing component 1922. The application programs stored in memory 1932 may include one or more modules that each correspond to a set of instructions.

The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output (I/O) interface 1958. The electronic device 1900 may operate based on an operating system, such as the Microsoft Server operating system (Windows Server), stored in the memory 1932^TM) Apple Inc. of the present application based on the graphic user interface operating System (Mac OS X)^TM) Multi-user, multi-process computer operating system (Unix)^TM) Free and open native code Unix-like operating System (Linux)^TM) Open native code Unix-like operating System (FreeBSD)^TM) Or the like.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.