阅读说明：本技术 片上系统装置、扩频时钟生成器及其方法 (System-on-chip apparatus, spread spectrum clock generator and method thereof ) 是由 大卫·史塔薛尔斯基 于 2021-08-09 设计创作，主要内容包括：本申请提供了一种片上系统装置、扩频时钟生成器及其方法。在一个实施例中,一种扩频时钟生成器包括耦接到N分频锁相环(PLL)的数字deltasigma调制器,其中,所述PLL包括离散时间电容倍增器环路滤波器。(A system-on-chip apparatus, a spread spectrum clock generator and a method thereof are provided. In one embodiment, a spread spectrum clock generator includes a digital deltasigma modulator coupled to a frequency-division-N phase-locked loop (PLL), wherein the PLL includes a discrete-time capacitance multiplier loop filter.)

1. A spread spectrum clock generator comprising a digital delta sigma modulator coupled to a divide-by-N phase locked loop, a divide-by-N PLL, wherein the PLL comprises a discrete time capacitance multiplier loop filter.

2. The spread spectrum clock generator of claim 1, wherein the discrete-time capacitance multiplier loop filter is implemented using a plurality of switched capacitance resistors.

3. The spread spectrum clock generator of claim 2, wherein each of the plurality of switched capacitance resistors comprises one capacitor and at least two switches driven by non-overlapping clocks.

4. The spread spectrum clock generator of claim 2, wherein at least one of the plurality of switched capacitance resistors comprises a dual linear switched capacitance resistor.

5. The spread spectrum clock generator of claim 1, wherein the discrete time capacitance multiplier loop filter is process independent.

6. The spread spectrum clock generator of claim 1, wherein the PLL further comprises a Voltage Controlled Oscillator (VCO) configured to be calibrated, and a switched capacitor charge pump current reference generator reference configured to be dynamically adjusted based on a gain of the VCO, wherein the resulting gain factor is process independent.

7. A system-on-chip (SoC) device comprising:

a spread spectrum clock generator comprising a digital delta sigma modulator coupled to a divide-by-N phase locked loop, a divide-by-N PLL, the PLL comprising a discrete time capacitance multiplier loop filter; and

a plurality of PLLs coupled to the spread spectrum clock generator, the plurality of PLLs each configured to service different logic on the SoC device.

8. The SoC device of claim 7, wherein the discrete-time capacitance multiplier loop filter is implemented using a plurality of switched capacitance resistors.

9. The SoC device of claim 8, wherein each of the plurality of switched capacitance resistors comprises one capacitor and at least two switches driven by non-overlapping clocks.

10. The SoC device of claim 8, wherein at least one of the plurality of switched capacitance resistors comprises a dual linear switched capacitance resistor.

11. The SoC device of claim 7, wherein the discrete-time capacitance multiplier loop filter is process-independent.

12. The SoC apparatus of claim 7, wherein the fractional-N PLL further comprises a Voltage Controlled Oscillator (VCO) configured to be calibrated, and a switched capacitor charge pump current reference generator reference configured to be dynamically adjusted based on a gain of the VCO, wherein the resulting gain factor is process independent.

13. The SoC device of claim 7, wherein at least one of the plurality of PLLs is configured to drive a plurality of processor cores on the SoC device based on an output of the spread-spectrum clock generator.

14. The SoC device of claim 7, wherein at least one of the plurality of PLLs is configured to generate a Double Data Rate (DDR) reference clock based on an output of the spread spectrum clock generator.

15. A method of discrete-time loop filtering implemented in a spread spectrum clock generator, the method comprising:

receiving a signal from a charge pump; and

the signal is filtered using a discrete time capacitance multiplier loop filter.

16. The method of claim 15, wherein the discrete-time capacitance multiplier loop filter is implemented using a plurality of switched capacitance resistors.

17. The method of claim 16, wherein each of the plurality of switched capacitor resistors comprises one capacitor and at least two switches driven by non-overlapping clocks.

18. The method of claim 16, wherein at least one of the plurality of switched capacitor resistors comprises a dual linear switched capacitor resistor.

19. The method of claim 15, wherein the discrete-time capacitance multiplier loop filter is process independent.

20. The method of claim 15, further comprising calibrating a Voltage Controlled Oscillator (VCO) and scaling a current reference to maintain a process independent gain factor.

Technical Field

The present invention relates generally to spread spectrum clock generators, and in particular to spread spectrum clock generators for use in a system on a chip (SoC).

Background

Spread Spectrum Clock Generators (SSCG) are ubiquitous in modern system on a chip (SoC) devices and microprocessors. SSCG is needed to reduce electromagnetic interference (EMI) that may cause systems to interfere with each other. SSCG is typically implemented as a fractional-N Phase Locked Loop (PLL) using a digital delta sigma (delta sigma) modulator (DDSM), which requires a low PLL bandwidth to filter quantization noise. The low loop bandwidth requires a large volume of on-chip capacitors, which may result in excessive area consumption. In addition to capacitors, loop filters are typically implemented using resistors. The resistor and the capacitor together form the poles and zeros necessary to stabilize the control loop of the PLL. Since the die resistor and capacitor cannot be matched in process, the control loop of the PLL may degrade, resulting in reduced EMI suppression and increased jitter.

Disclosure of Invention

In one embodiment, a spread spectrum clock generator includes a digital delta sigma modulator coupled to a frequency-division-N phase-locked loop (PLL) that includes a discrete-time capacitance multiplier loop filter.

Other systems, methods, features and advantages of the invention will be, or will become, apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

Drawings

Various aspects of the invention may be better understood with reference to the following drawings. The components in the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1A is a block diagram illustrating an example environment in which an embodiment of a process independent Spread Spectrum Clock Generator (SSCG) may be used.

Fig. 1B is a schematic diagram illustrating an exemplary process independent SSCG embodiment.

Fig. 2A-2C are schematic diagrams illustrating continuous-time to discrete-time transitions of a process-independent SSCG capacitance multiplier loop filter.

Figure 2D is a schematic diagram illustrating example non-overlapping clocks used in the switched capacitor resistors of the discrete-time capacitance multiplier loop filter of an embodiment of the process-independent SSCG.

Fig. 3 is a schematic diagram illustrating a small-signal phase-domain model of a phase-locked loop from which the open-loop transfer function of an embodiment of the process-independent SSCG is derived.

Fig. 4 is a flow diagram illustrating an embodiment of an example discrete-time loop filtering method.

Detailed Description

Certain embodiments of a process independent Spread Spectrum Clock Generator (SSCG) and associated methods are disclosed having a discrete time capacitance multiplier loop filter that uses a combination of switched capacitance resistors for the capacitance multiplier loop filter and uses a calibrated Voltage Controlled Oscillator (VCO) combined with a scaled current reference to provide the process independent SSCG.

In addition, SSCG is typically implemented as a fractional-N Phase Locked Loop (PLL) using a digital delta sigma modulator. The fabrication of SSCG involves different processes for the resistor and capacitor, and thus one process does not fit well into the other, which may result in reduced performance of the PLL. In contrast, certain embodiments of process independent SSCG use a discrete-time capacitance multiplier filter in combination with a switched capacitor (programmable) charge pump current reference that is dynamically selected (i.e., dynamically adjusted) based on VCO gain, which keeps the PLL control loop gain constant, enabling process independent operation that improves the performance of the PLL and thus the SSCG performance (e.g., less area consumption, improved EMI suppression, and/or reduced jitter).

Having summarized certain features of the process independent SSCG of the present invention, reference will now be made in detail to a description of the process independent SSCG as illustrated in the accompanying drawings. While process-independent SSCG will be described in connection with these figures, it is not intended to be limited to one or more embodiments disclosed herein. That is, while the invention is susceptible to modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail as sufficient to enable those skilled in the art to understand the invention. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words "include", "including", and "includes" mean including, but not limited to.

Referring now to FIG. 1A, an example environment 10 is shown in which an embodiment of a process independent Spread Spectrum Clock Generator (SSCG) may be used in the example environment 10. The environment includes a crystal oscillator 12 that provides a reference clock to a system on chip (SoC) 14. The SoC 14 includes a process independent SSCG 16 configured to control a plurality of Phase Locked Loops (PLLs) 18. Each of the PLLs 18 is configured to provide an output to a different functional area or logic on the SoC 14 (depicted in fig. 1A as SoC F (x), where x equals 1, 2,. N). For example, the PLL 018 may be configured to drive multiple processor cores of a multi-core processor on the SoC 14 (e.g., clock the cores) based on the output of the SSCG 16. As another example, the PLL118 may be configured to generate a Double Data Rate (DDR) reference clock based on the output of the SSCG. As will be appreciated by those of ordinary skill in the art, additional and/or other logic may be present as a receiver of the output of the PLL 18, and thus further discussion thereof is omitted herein for the sake of brevity, as this is not germane to the present invention.

Fig. 1B is a schematic diagram illustrating an exemplary process independent SSCG embodiment. Specifically, fig. 1B illustrates the SSCG 16 of fig. 1A in greater detail. It is well known that a frequency reference, such as crystal oscillator 12, may be a major source (in addition to other sources of electromagnetic interference (EMI) on a SoC. Spread spectrum clock generators implement a technique in which the clock frequency is slightly modulated to reduce the peak energy generated by the clock. Spread spectrum clocking reduces the EMI generated by clocks from both the fundamental frequency and subsequent harmonics, thereby reducing the overall system EMI. In other words, the spread spectrum clock generator is configured to spread energy over a larger portion of a given frequency spectrum. As noted above, the SSCG 16 comprises a divide-by-N PLL that, in addition to the innovations noted herein, also uses a Digital Delta Sigma Modulator (DDSM) as a commonly used configuration in the industry. The crystal oscillator 12 provides a reference frequency to the PLL of the SSCG 16, which in turn functions as a frequency synthesizer that provides spread spectrum clocks to a plurality of PLLs 18. The SSCG 16 includes a Phase Frequency Detector (PFD)20, a charge pump current reference generator 22A Charge Pump (CP)24, a discrete-time capacitive loop filter 26, a Voltage Controlled Oscillator (VCO)28, a 1/M frequency divider 30, a multi-modulus divider (N/N + P)32, a DDSM34, and a ramp generator 36. The functions of the assemblies 20, 22, 24, 28, 30, 32, 34, and 36 are well known in the industry and, therefore, a discussion thereof is omitted herein for the sake of brevity. Additional information about SSCG can be found in published literature (such as Texas Instruments, Inc.)^TM) Technical introduction SWRA029, "Fractional/integral-N PLL Foundation (Fractional/integral-N PLL bases)"). Instead, for purposes of the present invention, emphasis is placed on the configurable operation between the loop filter 26 (described further below in conjunction with fig. 2A-2D) and the charge pump current reference generator 22 and VCO 28 and its effect on the corresponding gain factor to ensure process independence (described further below in conjunction with fig. 3).

Attention is first drawn to fig. 2A-2C, which show schematic diagrams illustrating continuous-time to discrete-time conversion of a capacitance multiplier loop filter. Fig. 2A specifically illustrates a continuous-time capacitance multiplier loop filter 38 that receives a current Ip from the charge pump 24 (e.g., as generated by the charge pump current reference generator 22). The continuous-time capacitance multiplier loop filter 38 includes a continuous-time capacitance multiplier 40, a capacitor C242 in the circuit other than the capacitance multiplier 40, a resistor R344, and another capacitor C346. The continuous-time capacitance multiplier 40 includes an amplifier 48, the amplifier 48 having an output connected to the inverting input (-); a resistor Rx50 and a capacitor C152 arranged in series at the non-inverting input (+); and another resistor Ry 54 at the output of amplifier 48. Certain embodiments of the SCCG that are process independent use an equivalent switched capacitor loop filter to effectively implement the function of the continuous-time capacitance multiplier loop filter 38, which reduces chip area, among other benefits. To illustrate this implementation, a description of the conversion from continuous time to discrete time is provided below.

FIG. 2B shows a version 38A of the continuous-time capacitance multiplier loop filter 38, in which the capacitance multiplier 40 is shown as being replaced by a capacitance multiplier 40A, the capacitance multiplier 40A having an effective impedance, i.e., C and C_1effR arranged in series_1eff. The following equations 1-5 can be derived from examination of FIGS. 2A-2B as follows:

C_1eff＝C₁(1+n_r) (equation 2)

n_r＝R_x/R_y(equation 3)

ix＝I_p/(1+n_r) (equation 4)

R_y＝R_x/n_r(equation 5)

Fig. 2C shows the discrete-time capacitance multiplier filter 26 resulting from the above conversion. Specifically, the resistors Rx50, Ry 54, and R344 of fig. 2A have been replaced by switched capacitance resistors 56, 58, and 60, while the amplifier 48 and capacitors C152, C242, and C346 remain. Thus, the discrete-time capacitance multiplier filter 26 includes a parallel arrangement of a switched capacitance resistor Rx 56 and a capacitor C152 at the non-inverting input of the amplifier 48, and within the loop at the output of the amplifier 48 is a switched capacitance resistor Ry 58, the output of which is fed back to the input of the switched capacitance resistor Rx 56, the switched capacitance resistor Rx 56 also receiving the charge pump current Ip. Outside the loop, there is a parallel arrangement of a capacitor C242, a switched capacitance resistor R360 and a capacitor C346 at the output (Vc) of the loop filter 26.

With specific reference to switched capacitance resistors 56, 58, and 60, switched capacitance resistors Rx 56 and R360 are similarly configured, while switched capacitance resistor Ry 58 comprises a dual linear switched capacitance resistor. Referring to the switched capacitance resistor Rx 56, the switched capacitance resistor Rx 56 includes a second clock Φ at each side of the Cx branch node (including the capacitor Cx (in the branch))₁First switch driven by second clock phi₂A second switch that is actuated. First clock phi₁And a second clock phi₂Including non-overlapping clocks 62 and 64, as shown in fig. 2D, which is forThe switched capacitor circuit is generated using known clock generation techniques and, therefore, a discussion thereof is omitted here for the sake of brevity. Note that these switches may be implemented according to any known transistor and/or switching logic consistent with a fabrication method for the SSCG 16. Similarly, the switched capacitor resistor R360 is comprised of a first clock Φ on each side of the CR3 branch node (including the capacitor CR3 (in that branch))₁First switch driven and controlled by second clock phi₂A second switch that is actuated.

As indicated above, switched capacitor resistor Ry 58 comprises a dual linear switched capacitor resistor. Switched capacitor resistor Ry 58 includes a set of switches on each side of the opposite side node of the branch (including capacitor Cy). For example, at the top node depicted in FIG. 2C, on each side of the node is a first clock Φ₁First switch driven and controlled by second clock phi₂A second switch that is actuated. On the bottom node depicted in FIG. 2C, on each side of the node is clocked by a second clock Φ₂Third switch driven by the first clock phi₁A fourth switch that is actuated. Explained further, since the amplifier 48 is used to drive the load Cy with a single set of switches, one of the clock states (e.g., Φ) is targeted₂) The amplifier 48 becomes unloaded, which may cause the amplifier 48 (e.g., buffer) to become unstable. By using a dual linear switched capacitor configuration, no load is avoided because the amplifier 48 is always exposed to the same load.

2A-2C, the continuous-time capacitance multiplier filter 38 uses actual resistors Rx50, Ry 54, and R344, which are converted to discrete time by being implemented as switched capacitance resistors Rx 56, Ry 58, and R360, respectively, as shown in FIG. 2C. Thus, the following equations 6-8 can be described:

rx 1/fCx (Eq. 6)

Ry T/4Cy 1/4Cy (equation 7)

R3 ═ T/CR3 ═ 1/fCR3 (equation 8)

In equations 6 to 8T is clock phi₁、Φ₂And f is the clock Φ₁、Φ₂Of (c) is detected. Note that in the portion of the continuous-time capacitance multiplier loop filter 38 that performs capacitance multiplication (e.g., the continuous-time capacitance multiplier), the effective capacitance C is_1effGiven by equation 2, and Ry by equation 5. Examining equations 2 and 5, when increasing n_rTo increase the effective capacitance, Ry decreases. Thus, n_rDoubling of (a) reduces Ry by a factor of 2. Since Cy is T/Ry for a standard switched capacitor resistor, reducing Ry by a factor of 2 will double Cy. As shown in equation 7 above, the use of a bilinear switched capacitor resistor Ry 58 increases n_rThe area loss of (a) is reduced by a factor of 4. Furthermore, since the poles and zeros of the PLL control loop in fig. 2C are a function of the ratio of the capacitors (the resistors replaced by the capacitors), and further since the switched capacitor resistors are based on the reference frequency of the current reference (which depends on the off-chip crystal oscillator 12), independence of the discrete time multiplier loop filter 26 from the manufacturing process is achieved.

The analysis of the SSCG transfer function, particularly with respect to process independence, is discussed below, which can be evaluated by looking at the gain factor of the open-loop transfer function (and similarly, the closed-loop transfer function with the same parameters). Fig. 3 is a schematic diagram illustrating a small-signal phase-domain model 66 of a phase-locked loop from which the open-loop transfer function of an embodiment of the process-independent SSCG is derived. Examination of the small-signal phase-domain model 66 reveals the following equations 9-15 (wherea is 1, and R_1e＝R_1effAnd C_1e＝C_1eff)：

The open loop gain (or loop gain) lg(s) is given by the following equations 16-17:

substituting z(s) yields equation 18 below:

the grouping of the first dividend and divisor of equation 18 into one term, denoted as equation 19 below, may be implemented:

specifically, lg(s) may be rewritten as follows:

for omega_p1、ω_p2And the equations for b and c are shown in equations 12-15 (a still equals 1). Examination of LG(s) shows that in conventional systems, K, ω_z、ω_p1、ω_p2Is a resistor, a capacitor, I_pAnd K_VCOAs a function of the absolute value of (a). Therefore, lg(s) is not independent with respect to processing. However, as shown in fig. 2C, independence from the process may be achieved by implementing the resistors in the capacitance multiplier filter 38 (of fig. 2A) as switched capacitance resistors. In converting the filter from a continuous-time version to a discrete-time version, note that R is T/C for Rx and R3, and T/4C for Ry, as described above. As long as the PLL bandwidth of the SSCG 16 is much less than the reference clock frequency (e.g., BW)<<Fref), these approximations are valid. Recall lg(s), refer to equation 20 and note that if K, ω_z、ω_p1、ω_p2Is process independent, LG(s) is process independent. By simple algebraic operation of the above equation, the following equation 23 can be shown:

in other words, ω_zIs a stable ratio of frequency f to capacitor (and has a similar effect between the increase or decrease in capacitance due to being fabricated by the same processAnd thus process independent). For omega_p1、ω_p2Note from equations 12 and 13 that if b and c are process independent (and reference a is 1), then ω is_p1And ω_p2Is process independent. Through simple algebraic operations on the equations described herein, the following equations 24 and 25 can be shown:

i.e. b is a function of the sum of the stable reference clock frequency f and the ratio of the capacitors. N is a radical of_rEqual to 4Cy/Cx and is therefore the ratio of the capacitors. c is also a function of the ratio of the stable reference frequency f and the capacitor. Since a, b and c are process independent, ω_p1And ω_p2Is process independent.

Attention is now directed to the gain factor K, and equation 21, I is remembered_pIs generated by switched capacitor current reference generator 22 (fig. 1B). For I_pIs as follows (equation 26):

wherein T is¹2Tref, where Tref is the reference clock period, and f¹Fref/2, where fref is the reference clock frequency as described above. Note that C_ICorresponding to the main capacitor used to generate the charge pump current reference. That is, the charge pump current reference includes generating I_pAnd the capacitors within the block are used to generate equation 26 above. Using algebraic operations on the above equations, equation 27 can be shown:

in other words, I is calibrated_pAnd K_VCOThe product of (d) remains constant. In addition, the VCO supplies a control voltage, and generates a clock based on the control voltage. When the control voltage is varied, the frequency is varied. The VCO is comprised of a programmable switching circuit or device (e.g., a programmable transistor) that converts a voltage to a current, where the current drives a current controlled oscillator. In the calibration process, the control voltage is kept constant and the transistors are switched to multiples of the current used to control the current controlled oscillator. By keeping the control voltage constant, the frequency can be fine-tuned to a desired value. Furthermore, a gain may be measured, wherein adjusting the control voltage results in a gain determined by a frequency change caused by a change in the control voltage. Once K is determined_VCOThen the charge pump current value is determined. Typically, the goal of calibration is to determine the gain (K) of the VCO_VCO) Such that once determined, the charge pump current can be varied to keep K (e.g., the open loop transfer function K) constant and thus obtain independence from the process. Thus, the gain K is measured_VCOThen to I_pScaling is performed (note K in equation 18_VCOAnd I_pThe inverse relationship between them and can therefore be kept constant). I is_pThe process through C1 may be biased. However, for K, in the case where Vref is process independent, the second dividend and divisor in equation 27 will cause the variation to disappear, making K process independent. Vref is derived from the bandgap voltage (which is process independent). In effect, implementing a switched capacitor programmable charge pump current reference generator based on VCO gain dynamic selection (i.e., dynamic adjustment) keeps the PLL control loop gain constant.

Although the above description is directed to an open-loop path transfer function, since the closed-loop function uses the same parameters, a similar derivation of independence from process can be shown, but is omitted here for brevity and clarity.

Having described certain embodiments of process-independent SSCG, it should be appreciated that one embodiment of an example discrete-time loop filtering method (represented as method 68 in fig. 4) implemented in SSCG includes receiving a signal from a charge pump (70); and filtering (72) the signal using a discrete-time capacitance multiplier loop filter.

Any process descriptions or blocks in flow charts should be understood as representing modules, segments, logic, or portions of code which include one or more executable instructions for implementing specific logical functions or steps in the process, and alternate implementations are included within the scope of the embodiments in which functions may be executed out of order from that shown or discussed (including substantially concurrently or in a different order), depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Note that different combinations of the disclosed embodiments can be used, and thus reference to an embodiment or one embodiment is not meant to exclude features from that embodiment from being used with features from other embodiments. In the claims, the word "comprising" does not exclude other elements or steps.