阅读说明：本技术 显示面板及显示装置 (Display panel and display device ) 是由 熊娜娜 符鞠建 于 2021-08-20 设计创作，主要内容包括：本申请实施例提供了一种显示面板及显示装置,显示面板包括像素驱动电路组和呈阵列排布的多个发光元件,像素驱动电路组包括第一像素驱动电路和第二像素驱动电路；在第一排布方向上,第一像素驱动电路和第二像素驱动电路分别与不同的发光元件电连接；在发光阶段,第一像素驱动电路与第二像素驱动电路中的第一节点和第二节点的电压值之间的关系包括：(V12-V11)*(V22-V21)＜0,其中,V12表示第一像素驱动电路中的第二节点的电压值,V11表示第一像素驱动电路中的第一节点的电压值,V22表示第二像素驱动电路中的第二节点的电压值,V21表示第二像素驱动电路中的第一节点的电压值。本申请实施例能够改善甚至消除显示面板的闪烁现象。(The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a pixel driving circuit group and a plurality of light-emitting elements which are arranged in an array manner, and the pixel driving circuit group comprises a first pixel driving circuit and a second pixel driving circuit; in the first arrangement direction, the first pixel drive circuit and the second pixel drive circuit are electrically connected to different light emitting elements, respectively; in the light emitting stage, the relationship between the voltage values of the first node and the second node in the first pixel driving circuit and the second pixel driving circuit includes: (V12-V11) (V22-V21) < 0, where V12 represents a voltage value of the second node in the first pixel driving circuit, V11 represents a voltage value of the first node in the first pixel driving circuit, V22 represents a voltage value of the second node in the second pixel driving circuit, and V21 represents a voltage value of the first node in the second pixel driving circuit. The embodiment of the application can improve and even eliminate the flicker phenomenon of the display panel.)

1. A display panel is characterized by comprising a pixel array, wherein the pixel array comprises a pixel driving circuit group and a plurality of light-emitting elements arranged in an array, the pixel driving circuit group comprises a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, and each light-emitting element is electrically connected to one of the first pixel driving circuits and the second pixel driving circuits;

the first pixel drive circuit and the second pixel drive circuit are electrically connected to different ones of the light emitting elements, respectively, in a first arrangement direction of the plurality of light emitting elements;

the first pixel driving circuit and the second pixel driving circuit each include:

the control end of the driving module is electrically connected with a first node and used for driving the light-emitting element to emit light under the control of the first node;

a first switch module, which includes at least two first switch elements, the at least two first switch elements are arranged in series, control ends of the at least two first switch elements are electrically connected with a scanning signal line, a first end of one of the at least two first switch elements is electrically connected with the first node, and a connection node between different first switch elements in the at least two first switch elements is a second node;

in the light emitting phase, the relationship between the voltage values of the first and second nodes in the first pixel driving circuit and the voltage values of the first and second nodes in the second pixel driving circuit includes:

(V12-V11)*(V22-V21)＜0，

wherein V12 represents a voltage value of the second node in the first pixel driving circuit, V11 represents a voltage value of the first node in the first pixel driving circuit, V22 represents a voltage value of the second node in the second pixel driving circuit, and V21 represents a voltage value of the first node in the second pixel driving circuit.

2. The display panel according to claim 1, wherein the plurality of light emitting elements includes M1 × M2 light emitting elements, M1 light emitting elements are arranged in order in the first arrangement direction, and M1 light emitting elements include Q first light emitting element groups, each of the first light emitting element groups including at least one of the light emitting elements;

in the Q first light-emitting element groups, the light-emitting elements in Q1 first light-emitting element groups are electrically connected to the first pixel driving circuit, the light-emitting elements in Q2 first light-emitting element groups are electrically connected to the second pixel driving circuit, Q1+ Q2 is Q, and M1, M2, Q, Q1, and Q2 are all positive integers.

3. The display panel of claim 2, wherein the ratio of q1 to q2 is 1: X1, and X1 is a positive number.

4. The display panel according to claim 2, wherein when a ratio of q1 to q2 is 1:1, the light emitting element in one of the first light emitting element groups in two adjacent first light emitting element groups is electrically connected to the first pixel driving circuit, and the light emitting element in the other first light emitting element group is electrically connected to the second pixel driving circuit.

5. The display panel according to claim 1, wherein the plurality of light-emitting elements includes M1 × M2 light-emitting elements, M2 light-emitting elements are arranged in this order in a second arrangement direction, the second arrangement direction is perpendicular to the first arrangement direction, and M1 and M2 are both positive integers;

in the M1 columns of the light emitting elements, M2 light emitting elements in one part of columns are all connected with the first pixel driving circuit, and M2 light emitting elements in the other part of columns are all connected with the second pixel driving circuit; alternatively, the first and second electrodes may be,

in the M1 rows of the light emitting elements, M2 light emitting elements in one part of the rows are all connected with the first pixel driving circuit, and M2 light emitting elements in the other part of the rows are all connected with the second pixel driving circuit; alternatively, the first and second electrodes may be,

in each of the M1 columns of the light emitting elements or each of the M1 rows of the light emitting elements, a part of the M2 light emitting elements are electrically connected to the first pixel driving circuit, and another part of the light emitting elements are electrically connected to the second pixel driving circuit.

6. The display panel according to claim 5, wherein the M2 light-emitting elements include K second light-emitting element groups each including at least one of the light-emitting elements;

in the K second light emitting element groups, light emitting elements in K1 second light emitting element groups are electrically connected to the first pixel driving circuit, light emitting elements in K2 second light emitting element groups are electrically connected to the second pixel driving circuit, and K1+ K2 ═ K, K, K1 and K2 are positive integers.

7. The display panel according to claim 6, wherein the ratio between k1 and k2 is 1: X2, and X2 is a positive number.

8. The display panel according to claim 6, wherein in the case where the ratio between k1 and k2 is 1:1, the light emitting element in one of the second light emitting element groups in two adjacent second light emitting element groups is electrically connected to the first pixel driving circuit, and the light emitting element in the other second light emitting element group is electrically connected to the second pixel driving circuit.

9. The display panel according to claim 2, wherein the display panel further comprises a plurality of gate lines extending in a row direction and a plurality of data lines extending in a column direction, the first arrangement direction including the row direction;

in the odd-numbered rows of the light emitting elements, the first pixel driving circuit is electrically connected to the light emitting elements in the first light emitting element group whose arrangement number is odd, and the second pixel driving circuit is electrically connected to the light emitting elements in the first light emitting element group whose arrangement number is even;

in the light emitting elements in the even-numbered rows, the first pixel driving circuit is electrically connected to the light emitting elements in the first light emitting element group whose arrangement number is even, and the second pixel driving circuit is electrically connected to the light emitting elements in the first light emitting element group whose arrangement number is odd.

10. The display panel according to claim 2, wherein the display panel further comprises a plurality of gate lines extending in a row direction and a plurality of data lines extending in a column direction, the first arrangement direction including the row direction;

in the light emitting elements in odd-numbered rows, the first pixel driving circuit is electrically connected to the light emitting elements in the first light emitting element group whose arrangement number is even, and the second pixel driving circuit is electrically connected to the light emitting elements in the first light emitting element group whose arrangement number is odd;

in the light emitting elements in the even-numbered rows, the first pixel driving circuit is electrically connected to the light emitting elements in the first light emitting element group whose arrangement number is odd, and the second pixel driving circuit is electrically connected to the light emitting elements in the first light emitting element group whose arrangement number is even.

11. The display panel according to claim 1,

the pixel array includes a plurality of color light emitting elements, one of which is electrically connected to the first pixel driving circuit and the other of which is electrically connected to the second pixel driving circuit, among two adjacent light emitting elements of the same color.

12. The display panel according to claim 4,

each of the first light emitting element groups includes a plurality of color light emitting elements.

13. The display panel according to claim 8,

each of the second light emitting element groups includes a plurality of color light emitting elements.

14. The display panel according to claim 1, wherein the second pixel driving circuit further comprises:

and the control end of the node control module is electrically connected with the first scanning signal line, the first end of the node control module is electrically connected with the reference signal line, and the second end of the node control module is electrically connected with the second node and used for transmitting the reference signal output by the reference signal line to the second node under the control of the first scanning signal output by the first scanning signal line so as to pull down the voltage value of the second node.

15. The display panel according to claim 14, wherein the second pixel driving circuit further comprises:

the control end of the first light-emitting control module is electrically connected with the control signal wire, the first end of the first light-emitting control module is electrically connected with the first power supply voltage signal wire, and the second end of the first light-emitting control module is electrically connected with the second end of the driving module;

a second light emission control module, a control end of which is electrically connected to the control signal line, a first end of which is electrically connected to the first end of the driving module, and a second end of which is electrically connected to the first pole of the light emitting element;

the first scanning signal line is multiplexed with the control signal line.

16. The display panel according to claim 1, wherein a first terminal of another one of the at least two first switching elements is electrically connected to a reference signal line, and the first switching module is configured to transmit a reference signal output from the reference signal line to the first node under control of a scan signal output from the scan signal line to reset the first node.

17. The display panel according to claim 1, wherein a first terminal of another one of the at least two first switching elements is electrically connected to a third node between the first terminal of the driving module and the first electrode of the light emitting element, and the first switching module is configured to turn on the control terminal of the driving module and the first terminal of the driving module under control of a scan signal output from the scan signal line.

18. The display panel according to any one of claims 1 to 15, wherein the first switch module comprises a first sub-switch module and the second sub-switch module, and the second node comprises a first sub-node and a second sub-node;

the first sub-switching module comprises at least two first sub-switching elements arranged in series, control terminals of the at least two first sub-switching elements are electrically connected to a second scanning signal line, a first terminal of one of the at least two first sub-switching elements is electrically connected to the first node, a first terminal of another one of the at least two first sub-switching elements is electrically connected to a reference signal line, the first sub-node is a connection node between different ones of the at least two first sub-switching elements, the first sub-switch module is used for transmitting a reference signal output by a reference signal line to the first node under the control of a second scanning signal output by the second scanning signal line so as to reset the first node;

the second sub-switching module includes at least two second sub-switching elements, the at least two second sub-switching elements are connected in series, control terminals of the at least two second sub-switching elements are electrically connected to a third scan signal line, a first terminal of one of the at least two second sub-switching elements is electrically connected to the first node, a first terminal of another one of the at least two second sub-switching elements is electrically connected to a third node, the third node is located between the first terminal of the driving module and the first pole of the light emitting element, the second sub-node is a connection node between different ones of the at least two second sub-switching elements, and the second sub-switching module is configured to control a third scan signal output by the third scan signal line, and connecting the control end of the driving module with the first end of the driving module.

19. The display panel according to claim 18,

in a light emitting phase, a relationship among a voltage value of a first node in the first pixel driving circuit, a voltage value of a first sub-node in the first pixel driving circuit, and a voltage value of a second sub-node in the first pixel driving circuit includes:

(V122-V11)＞(V121-V11)

wherein V122 represents a voltage value of a second sub-node in the first pixel driving circuit, V11 represents a voltage value of a first node in the first pixel driving circuit, and V121 represents a voltage value of a first sub-node in the first pixel driving circuit;

in a light emitting phase, a relationship among a voltage value of the first node in the second pixel driving circuit, a voltage value of the first sub-node in the second pixel driving circuit, and a voltage value of the second sub-node in the second pixel driving circuit includes:

(V222-V21)＝(V221-V21)

where V222 denotes a voltage value of the second sub-node in the second pixel driving circuit, V21 denotes a voltage value of the first node in the second pixel driving circuit, and V221 denotes a voltage value of the first sub-node in the second pixel driving circuit.

20. The display panel according to claim 1, wherein the driving module comprises:

a first transistor having a gate electrically connected to the first node, a first electrode electrically connected to a first electrode of the light emitting element, and a second electrode electrically connected to a first power supply voltage signal line;

the first switch module comprises at least two second transistors, the at least two second transistors are arranged in series, the grid electrodes of the at least two second transistors are electrically connected with a scanning signal line, and the first pole of one of the at least two second transistors is electrically connected with the first node.

21. A display device characterized by comprising the display panel according to any one of claims 1 to 20.

Technical Field

The application belongs to the technical field of display, and particularly relates to a display panel and a display device.

Background

With the development of display technology, Light Emitting Diode (LED) display panels and Organic Light Emitting Diode (OLED) display panels have been widely used in the display field due to their advantages of self-luminescence, small size, Light weight, etc.

The inventor of the present application finds that, for example, the LED display panel and the OLED display panel have a problem of brightness jump during displaying, i.e., a flicker phenomenon.

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, which can improve or even eliminate the flicker phenomenon of the display panel.

In a first aspect, an embodiment of the present application provides a display panel, where the display panel includes a pixel array, where the pixel array includes a pixel driving circuit group and a plurality of light emitting elements arranged in an array, the pixel driving circuit group includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, and each light emitting element is electrically connected to one of the first pixel driving circuits and the second pixel driving circuits; in a first arrangement direction of the plurality of light emitting elements, the first pixel drive circuit and the second pixel drive circuit are electrically connected to different light emitting elements, respectively; the first pixel driving circuit and the second pixel driving circuit each include: the control end of the driving module is electrically connected with the first node and used for driving the light-emitting element to emit light under the control of the first node; the scanning signal line is electrically connected with the scanning signal line, the first end of one of the at least two first switching elements is electrically connected with a first node, and a connecting node between different first switching elements in the at least two first switching elements is a second node; in the light emitting phase, the relationship between the voltage values of the first node and the second node in the first pixel driving circuit and the voltage values of the first node and the second node in the second pixel driving circuit includes:

(V12-V11)*(V22-V21)＜0，

where V12 denotes a voltage value of the second node in the first pixel driving circuit, V11 denotes a voltage value of the first node in the first pixel driving circuit, V22 denotes a voltage value of the second node in the second pixel driving circuit, and V21 denotes a voltage value of the first node in the second pixel driving circuit.

In a second aspect, embodiments of the present application provide a display device, which includes the display panel provided in any one of the embodiments of the first aspect.

In the display panel and the display device of the embodiment of the application, one part of the light-emitting elements in the display panel is electrically connected with the first pixel driving circuit, and the other part of the light-emitting elements in the display panel is electrically connected with the second pixel driving circuit; in the light-emitting stage, the second node in the first pixel driving circuit leaks current to the first node, so that the brightness of a light-emitting element connected with the first pixel driving circuit is reduced; in the same stage, the first node in the second pixel driving circuit leaks current to the second node, so that the brightness of the light-emitting element connected with the second pixel driving circuit is increased. Therefore, the brightness of the light-emitting element connected with the second pixel driving circuit can compensate the brightness of the light-emitting element connected with the first pixel driving circuit, so that the mutual compensation between the brightness of different light-emitting elements in the display panel is realized, and the flicker phenomenon caused by the brightness jump of the light-emitting element connected with the first pixel driving circuit is improved or even eliminated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram illustrating brightness variation of a display panel according to the related art;

fig. 2 is a circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 3 is a timing diagram of the pixel driving circuit shown in FIG. 2;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 10 is a schematic view of another structure of a display panel according to an embodiment of the present application;

fig. 11 is a schematic view of another structure of a display panel according to an embodiment of the present application;

fig. 12 is a schematic view of another structure of a display panel according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 15 is a schematic view of another structure of a display panel according to an embodiment of the present application;

fig. 16 is a schematic view of another structure of a display panel according to an embodiment of the present application;

fig. 17 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 18 is another circuit diagram of a pixel driving circuit according to an embodiment of the present application;

fig. 19 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present application;

fig. 20 is a circuit diagram of a pixel driving circuit according to an embodiment of the present application;

fig. 21 is a schematic diagram of another structure of a pixel driving circuit according to an embodiment of the present application;

fig. 22 is a schematic diagram of another structure of a pixel driving circuit according to an embodiment of the present application;

fig. 23 is a schematic diagram of another structure of a pixel driving circuit according to an embodiment of the present application;

fig. 24 is a circuit diagram of a second pixel driving circuit according to an embodiment of the present application;

FIG. 25 is a timing diagram of the second pixel driving circuit shown in FIG. 24;

fig. 26 is a schematic diagram of driving current variation curves of a first pixel driving circuit and a second pixel driving circuit according to an embodiment of the present disclosure;

fig. 27 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the prior art:

the inventor of the application finds that the LED display panel and the OLED display panel have the problem of brightness jump during display, namely the Flicker phenomenon. Especially, in the case of low frequency display, the flicker phenomenon becomes more noticeable. In order to solve the flicker phenomenon of the display panel, the inventors of the present application first conducted research and analysis on the root causes leading to the above technical problems, and the specific research and analysis processes are as follows:

the inventor of the present application has found that, as shown in fig. 1, in the lighting period t3 (or referred to as a hold period) of each frame, the brightness of the display panel gradually decreases. That is, the brightness of the display panel is first reduced from a higher brightness to a lower brightness in each frame. After the data voltage signal is written in the next frame, the display panel can be lightened quickly. In this way, the display panel repeatedly changes between brightness and darkness, so that human eyes can observe the phenomenon of flickering.

The light emission of the light emitting elements in the display panel is driven by the pixel driving circuit, for example, the LED display panel and the OLED display panel are driven by the driving current generated by the pixel driving circuit, that is, the luminance of the light emitting elements in the LED display panel and the OLED display panel is affected by the driving current, so the inventors presume that the reason for the reduction in luminance of the display panel is the change in the driving current. The magnitude of the driving current is closely related to the gate voltage of the driving transistor in the pixel driving circuit. Therefore, the inventors presume that the gate voltage of the driving transistor changes.

Based on the above conjecture, the inventor has verified the pixel driving circuit adopted in some embodiments of the present application, and finally finds the root cause of the above technical problem as follows:

fig. 2 is a circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure. Fig. 3 is a timing diagram of the pixel driving circuit shown in fig. 2. The transistors in fig. 2 are illustrated as P-type transistors, but are not limited to P-type transistors, and may be replaced with N-type transistors. For a P-type transistor, when the gate of the P-type transistor is at a low level, the first pole and the second pole of the P-type transistor are turned on, and when the gate of the P-type transistor is at a high level, the first pole and the second pole of the P-type transistor are turned off. Depending on the signal of the gate of each transistor and the type thereof, the first pole thereof may be used as a source and the second pole thereof may be used as a drain, or the first pole thereof may be used as a drain and the second pole thereof may be used as a source, which is not distinguished herein.

As shown in fig. 2 and 3, in the reset phase t1, the scan signal line S1 'outputs a low level, the dual-gate transistor M3 is turned on, and the reference signal output from the reference signal line vref' is transmitted to the first node N1, so as to reset the first node N1. In the data writing stage t2, the scanning signal line S1 'jumps from the low level output at stage t1 to the high level output at stage t2, and due to the parasitic capacitance (or equivalent capacitance) in the dual-gate transistor M3, the potential of the connection node N21' between the two sub-transistors of the dual-gate transistor M3 is pulled up to a higher voltage V due to the coupling effect of the parasitic capacitance_N21’，V_N21’The potential of the connecting node N21' is higher than the potential V1 of the first node N1 > V1. In the data writing phase t2 and the light emitting phase M3, since the two sub-transistors of the dual-gate transistor M3 are turned off, the power of the connection node N21 'between the two sub-transistors cannot be discharged at one time, so that the connection node N21' always maintains a high potential. However, due to the influence of the characteristics of the transistor, the dual-gate transistor M3 cannot be turned off completely, so that the current leakage from the connection node N21' to the first node N1 continues during the light emitting period M3, and the voltage level at the first node N1 continues to rise. As the potential of the first node N1 continues to rise, the driving current flowing through the driving transistor T1 gradually decreases, so that the luminance of the light emitting element D gradually decreases, and a flicker phenomenon occurs.

Based on a similar principle, in the light-emitting period t3, the scanning signal line S2' jumps from the low level output in the period t2 to the high level output in the period t3Under the coupling effect of the parasitic capacitance of the double-gate transistor M4, the potential of the connection node N22' between the two sub-transistors of the double-gate transistor M4 is pulled up to a higher voltage value V_N22’，V_N22’The potential of the connecting node N22' is higher than the potential V1 of the first node N1 > V1. During the light-emitting period t3, the connection node N22' continues to leak current to the first node N1, further increasing the flicker phenomenon of the display panel.

In view of the above research by the inventors, embodiments of the present application provide a display panel and a display device, which can solve the problem of flicker of the display panel in the prior art.

The technical idea of the embodiment of the application is as follows: one part of the light-emitting elements in the display panel are electrically connected with the first pixel driving circuit, and the other part of the light-emitting elements in the display panel are electrically connected with the second pixel driving circuit; in the light-emitting stage, the second node in the first pixel driving circuit leaks current to the first node, so that the brightness of a light-emitting element connected with the first pixel driving circuit is reduced; in the same stage, the first node in the second pixel driving circuit leaks current to the second node, so that the brightness of the light-emitting element connected with the second pixel driving circuit is increased. Therefore, the brightness of the light-emitting element connected with the second pixel driving circuit can compensate the brightness of the light-emitting element connected with the first pixel driving circuit, so that the mutual compensation between the brightness of different light-emitting elements in the display panel is realized, and the flicker phenomenon caused by the brightness jump of the light-emitting element connected with the first pixel driving circuit is improved or even eliminated.

The following first describes a display panel provided in an embodiment of the present application.

As shown in fig. 4, an embodiment of the present application provides a display panel 10, where the display panel 10 includes a pixel array 100, and the pixel array 100 includes a pixel driving circuit group 101 and a plurality of light emitting elements 102 arranged in an array. The pixel driving circuit group 101 includes a plurality of first pixel driving circuits a and a plurality of second pixel driving circuits B. Each of the light emitting elements 102 is electrically connected to one of the first pixel driving circuit a and the second pixel driving circuit B, that is, for each of the light emitting elements 102, the light emitting element 102 may be electrically connected to the first pixel driving circuit a or the second pixel driving circuit B. The first pixel drive circuit a and the second pixel drive circuit B are electrically connected to different light emitting elements 102, respectively, in the first arrangement direction of the plurality of light emitting elements 102.

The first arrangement direction may be a row direction (X direction shown in fig. 4) or a column direction (Y direction shown in fig. 4), and may be flexibly adjusted according to actual conditions, which is not limited in the embodiment of the present application.

As shown in fig. 5, the first pixel driving circuit a and the second pixel driving circuit B each include a driving module 11 and a first switching module 12. The control terminal of the driving module 11 is electrically connected to the first node N1, and the driving module 11 is configured to drive the light emitting element 102 to emit light under the control of the first node N1. The first switch module 12 includes at least two first switch elements 121, the at least two first switch elements 121 are arranged in series, control ends of the at least two first switch elements 121 are electrically connected to the scan signal line S, a first end of one of the at least two first switch elements 121 is electrically connected to a first node N1, and a connection node between different first switch elements 121 of the at least two first switch elements 121 is a second node N2.

In the embodiment of the present application, in the light emitting period t3, the relationship between the voltage values of the first node N1 and the second node N2 in the first pixel driving circuit a and the voltage values of the first node N1 and the second node N2 in the second pixel driving circuit B includes:

(V12-V11)*(V22-V21)＜0 (1)

where V12 denotes a voltage value of the second node N2 in the first pixel driving circuit a, V11 denotes a voltage value of the first node N1 in the first pixel driving circuit a, V22 denotes a voltage value of the second node N2 in the second pixel driving circuit B, and V21 denotes a voltage value of the first node N1 in the second pixel driving circuit B.

When (V12-V11) × (V22-V21) < 0 is satisfied, there are two cases, respectively. The first case is: V12-V11 > 0, V22-V21 < 0, which indicates that the voltage value of the second node N2 in the first pixel driving circuit a is greater than the voltage value of the first node N1 in the first pixel driving circuit a, and the voltage value of the second node N2 in the second pixel driving circuit B is less than the voltage value of the first node N1 in the second pixel driving circuit B. In contrast, the second case is: V12-V11 < 0, V22-V21 > 0, which indicates that the voltage value of the second node N2 in the first pixel driving circuit a is smaller than the voltage value of the first node N1 in the first pixel driving circuit a, and the voltage value of the second node N2 in the second pixel driving circuit B is larger than the voltage value of the first node N1 in the second pixel driving circuit B. That is, one of the first pixel driving circuit a and the second pixel driving circuit B is a pixel driving circuit for increasing the luminance of the light emitting element, and the other is a pixel driving circuit for decreasing the luminance of the light emitting element. The first pixel driving circuit A and the second pixel driving circuit B can be interchanged, and when the first pixel driving circuit A is a pixel driving circuit which enables the brightness of the light-emitting element to be reduced, the second pixel driving circuit B is a pixel driving circuit which enables the brightness of the light-emitting element to be increased; in contrast, when the first pixel driving circuit a is a pixel driving circuit for increasing the luminance of the light emitting element, the second pixel driving circuit B is a pixel driving circuit for decreasing the luminance of the light emitting element, and neither the first case nor the second case described above affects the implementation of the embodiment of the present application.

Taking the first case of V12-V11 > 0 and V22-V21 < 0 as an example, in the light-emitting period t3, since the voltage value of the second node N2 in the first pixel driving circuit a is higher than the voltage value of the first node N1 in the first pixel driving circuit a, the second node N2 in the first pixel driving circuit a may leak current to the first node N1, so that the luminance of the light-emitting element 102 connected to the first pixel driving circuit a is reduced. At the same stage, since the voltage value of the second node N2 in the second pixel driving circuit B is lower than the voltage value of the first node N1 in the second pixel driving circuit B, the first node N1 in the second pixel driving circuit B leaks current to the second node N2, so that the luminance of the light emitting element 102 connected to the second pixel driving circuit B is increased. Thus, a part of the light emitting elements 102 in the display panel 10 is electrically connected to the first pixel driving circuit a, another part of the light emitting elements 102 is electrically connected to the second pixel driving circuit B, and the luminance of the light emitting elements 102 connected to the first pixel driving circuit a is compensated by the luminance of the light emitting elements 102 connected to the second pixel driving circuit B, so that the luminance of different light emitting elements 102 in the display panel 10 can be compensated with each other, thereby improving or even eliminating the flicker phenomenon caused by the luminance jump of the light emitting elements 102 connected to the first pixel driving circuit a.

As shown in fig. 6, according to some embodiments of the present application, the display panel 10 may optionally include M1 × M2 light emitting elements 102, M1 light emitting elements 102 are sequentially arranged in the first arrangement direction, the M1 light emitting elements 102 may include Q first light emitting element groups D1, and each first light emitting element group D1 may include at least one light emitting element 102. In the Q first light-emitting element groups D1, the light-emitting elements 102 in the Q1 first light-emitting element group D1 are electrically connected to the first pixel driving circuit a, the light-emitting elements 102 in the Q2 first light-emitting element group D1 are electrically connected to the second pixel driving circuit B, Q1+ Q2 is Q, and M1, M2, Q, Q1, and Q2 are all positive integers.

It should be noted that Q1 may be any number greater than 0 and smaller than Q, and the size of Q1 may be flexibly adjusted according to the actual situation, which is not limited in the embodiment of the present application. In addition, each of the first light emitting element groups D1 may include one light emitting element 102, or may include a plurality of light emitting elements 102. As shown in fig. 7, in some specific embodiments, each first light emitting element group D1 may include one light emitting element 102, M1 light emitting elements 102 may include a plurality of repeating units F1, each repeating unit F1 may include a plurality of first light emitting element groups D1, for example, each repeating unit F1 may include 4 first light emitting element groups D1. For each repeating unit F1, the light emitting elements 102 in the first to third light emitting element groups D1 to D1 are electrically connected to the first pixel driving circuit a, and the fourth first light emitting element group D1 is electrically connected to the second pixel driving circuit B, and such connection (or arrangement) may be referred to as "AAAB", where a in AAAB "refers to the first pixel driving circuit a, and B in AAAB" refers to the second pixel driving circuit B. Of course, each of the repeating units F1 may be formed such that the light emitting elements 102 in the first, second, and fourth light emitting element groups D1, D1, and D1 are electrically connected to the first pixel driving circuit a, and the third light emitting element group D1 is electrically connected to the second pixel driving circuit B, which may be referred to as "AABA", and similarly, a refers to the first pixel driving circuit a, and B refers to the second pixel driving circuit B. Other connection methods such as "BBAB", "BBBA", "AABB" and "BBAA" may be used. Alternatively, when each of the repeating units F1 includes another number of the first light-emitting element groups D1, other connection manners such as "AB", "BA", "AAB", or "AAAAB" may be adopted. In practical applications, any connection manner may be adopted according to specific display requirements, and the embodiment of the present application is not limited thereto.

Thus, by dividing M1 light emitting elements 102 sequentially arranged in the first arrangement direction into Q first light emitting element groups D1 and selectively connecting the first pixel driving circuit a or the second pixel driving circuit B in units of groups, it is possible not only to compensate the luminance of the light emitting elements 102 in the first light emitting element group D1 connected to the second pixel driving circuit B for the luminance of the light emitting elements 102 in the first light emitting element group D1 connected to the first pixel driving circuit a, thereby improving or even eliminating the flicker phenomenon of the display panel, but also to flexibly adjust the number of light emitting elements in each first light emitting element group D1 according to the actual display requirements, thereby satisfying different display requirements.

According to some embodiments of the present application, optionally, the ratio of q1 to q2 is 1: X1, and X1 is a positive number. Wherein, X1 may be less than 1, or greater than 1.

When X1 is less than 1, the number of light-emitting elements 102 to which the first pixel drive circuit a is connected is greater than the number of light-emitting elements 102 to which the second pixel drive circuit B is connected in the first arrangement direction, which can be applied to a scene in which the increase in luminance of the light-emitting elements 102 to which the second pixel drive circuit B is connected is greater than the decrease in luminance of the light-emitting elements 102 to which the first pixel drive circuit a is connected. In other words, if the luminance of the light emitting element 102 in the case where the first pixel driving circuit a does not generate the leakage current is taken as the theoretical luminance, then X1 may be adjusted to be smaller than 1 in the case where the difference between the luminance of the light emitting element 102 to which the second pixel driving circuit B is connected and the theoretical luminance is larger than the difference between the theoretical luminance and the luminance of the light emitting element 102 in the case where the first pixel driving circuit a generates the leakage current. Thus, the brightness of the light-emitting element 102 connected with one second pixel driving circuit B can compensate the brightness of the light-emitting elements 102 connected with a plurality of adjacent first pixel driving circuits a, so that the flicker problem is improved, the brightness uniformity of the display panel is ensured, and the mura phenomenon is avoided.

When X1 is greater than 1, the number of light-emitting elements 102 connected to the first pixel drive circuit a is smaller than the number of light-emitting elements 102 connected to the second pixel drive circuit B in the first arrangement direction, and this is applicable to a scenario in which the increase in luminance of the light-emitting elements 102 connected to the second pixel drive circuit B is smaller than the decrease in luminance of the light-emitting elements 102 connected to the first pixel drive circuit a, that is, a scenario in which the difference between the luminance of the light-emitting elements 102 connected to the second pixel drive circuit B and the theoretical luminance is smaller than the difference between the theoretical luminance and the luminance of the light-emitting elements 102 in the case where a leakage current occurs in the first pixel drive circuit a. In this way, the luminance of the light emitting element 102 connected to the plurality of second pixel driving circuits B can compensate the luminance of the light emitting element 102 connected to the adjacent first pixel driving circuit a, so that the luminance reduced by the light emitting element 102 connected to the first pixel driving circuit a can be sufficiently compensated, and the flicker problem of the display panel can be greatly improved or even eliminated.

In practical applications, the size of X1, that is, the ratio of the second pixel driving circuit B to the first pixel driving circuit a in the first arrangement direction, can be flexibly adjusted according to the increase of the luminance of the light emitting element 102 connected to the second pixel driving circuit B and the decrease of the luminance of the light emitting element 102 connected to the first pixel driving circuit a, which is not limited in the embodiments of the present application.

As shown in fig. 8, according to some embodiments of the present application, optionally, in the case where the ratio of q1 to q2 is 1:1, the light emitting elements 102 in one of the first light emitting element groups D1 in the two adjacent first light emitting element groups D1 are electrically connected to the first pixel driving circuit a, and the light emitting elements 102 in the other first light emitting element group D1 are electrically connected to the second pixel driving circuit B.

For example, when the first light emitting element group D1 includes one light emitting element 102, connection of "AB" or "BA" may be adopted, that is, one light emitting element 102 of the adjacent light emitting elements 102 is connected to the first pixel driving circuit a, and the other light emitting element is connected to the second pixel driving circuit B. When the first light-emitting element group D1 includes two light-emitting elements 102, a connection manner of "AABB" or "BBAA" may be adopted, that is, two light-emitting elements 102 in one first light-emitting element group D1 in the adjacent first light-emitting element group D1 are both electrically connected to the first pixel driving circuit a, and two light-emitting elements 102 in the other first light-emitting element group D1 are both electrically connected to the second pixel driving circuit B. When the first light emitting element group D1 includes other numbers of light emitting elements 102, similar to the case where the first light emitting element group D1 includes one light emitting element 102 or two light emitting elements 102, the description thereof is omitted.

In this way, since the light emitting elements 102 in the adjacent first light emitting element group D1 are respectively connected to the first pixel driving circuit a and the second pixel driving circuit B, that is, the first light emitting element group D1 connected to the second pixel driving circuit B and the first light emitting element group D1 connected to the first pixel driving circuit a are uniformly and alternately arranged in the first arrangement direction, the luminances of the regions in the first arrangement direction can be made to be the same or similar, the uniformity of the luminance of the display panel is ensured, and the flicker phenomenon of the display panel is improved to a large extent.

With continued reference to fig. 8, according to some embodiments of the present application, optionally, in a second arrangement direction perpendicular to the first arrangement direction, M2 light emitting elements are arranged in sequence along the second arrangement direction, i.e., the display panel 10 includes M1 × M2 light emitting elements 102, and M1 and M2 are both positive integers.

Illustratively, the first arrangement direction may be a row direction (X direction shown in fig. 8), and the second arrangement direction may be a column direction (Y direction shown in fig. 8), so that the display panel 10 may include M1 columns of light emitting elements and M2 rows of light emitting elements. In the M1 columns of light emitting elements, M2 light emitting elements 102 of one partial column may be all connected to the first pixel driving circuit a, and M2 light emitting elements 102 of another partial column may be all connected to the second pixel driving circuit B.

As shown in fig. 9, according to other embodiments of the present application, the first arrangement direction may alternatively be a column direction (Y direction shown in fig. 9), and the second arrangement direction may alternatively be a row direction (X direction shown in fig. 9), so that the display panel 10 may include M2 columns of light-emitting elements and M1 rows of light-emitting elements. In the M1 rows of light emitting elements, M2 light emitting elements 102 of one partial row may each be connected to the first pixel driving circuit a, and M2 light emitting elements 102 of another partial row may each be connected to the second pixel driving circuit B.

As shown in fig. 10, according to other embodiments of the present application, alternatively, in addition to that all of the M2 light emitting elements 102 shown in fig. 8 and 9 are connected to the same pixel driving circuit, some of the M2 light emitting elements 102 may be electrically connected to the first pixel driving circuit a, and another part of the light emitting elements may be electrically connected to the second pixel driving circuit B. Specifically, when the first arrangement direction is the row direction (X direction shown in fig. 11) and the second arrangement direction is the column direction (Y direction shown in fig. 11), in each column of M1 columns, some of the M2 light-emitting elements 102 are electrically connected to the first pixel driving circuit a, and some are electrically connected to the second pixel driving circuit B. Alternatively, when the first arrangement direction is a column direction and the second arrangement direction is a row direction, in each row of light-emitting elements of the M1 rows, a part of the M2 light-emitting elements 102 is electrically connected to the first pixel driving circuit a, and the other part is electrically connected to the second pixel driving circuit B.

In this way, the first pixel driving circuit a and the second pixel driving circuit B are not only electrically connected to the different light emitting elements 102 in the first arrangement direction, but also electrically connected to the different light emitting elements 102 in the second arrangement direction, so that not only can the brightness compensation between the different light emitting elements 102 in the first arrangement direction be realized, but also the brightness compensation between the different light emitting elements 102 in the second arrangement direction be realized, and the flicker phenomenon of the display panel can be improved or even eliminated to a greater extent.

As shown in fig. 11, according to some embodiments of the present application, alternatively, the M2 light emitting elements arranged in the second arrangement direction may include K second light emitting element groups D2, and each of the second light emitting element groups D2 may include at least one light emitting element 102, similar to the M1 light emitting elements arranged in the first arrangement direction. In the K second light emitting element groups D2, the light emitting elements 102 in the K1 second light emitting element group D2 are electrically connected to the first pixel driving circuit a, the light emitting elements 102 in the K2 second light emitting element group D2 are electrically connected to the second pixel driving circuit B, and K1+ K2 is K, and K, K1 and K2 are positive integers.

It should be noted that K1 may be any number greater than 0 and smaller than K, and the size of K1 may be flexibly adjusted according to the actual situation, which is not limited in the embodiment of the present application. In addition, each of the second light emitting element groups D2 may include one light emitting element 102, or may include a plurality of light emitting elements 102. Similar to the M1 light-emitting elements arranged in the first arrangement direction, the K second light-emitting element groups D2 arranged in the second arrangement direction may adopt any connection manner, such as "AAAB", "AABA", "BBAB", "BBBA", "AABB", "BBAA", "AB", "BA", "AAB", or "aaaaaab", in practical application, according to specific display requirements, which is not limited in this application.

Thus, by dividing M2 light emitting elements 102 sequentially arranged in the second arrangement direction into K second light emitting element groups D2 and selectively connecting the first pixel driving circuit a or the second pixel driving circuit B in units of groups, not only can the luminance of the light emitting elements 102 in the second light emitting element group D2 connected to the second pixel driving circuit B be compensated for the luminance of the light emitting elements 102 in the second light emitting element group D2 connected to the first pixel driving circuit a, improving or even eliminating the flicker phenomenon of the display panel, but also the number of light emitting elements in the second light emitting element group D2 can be flexibly adjusted according to actual display requirements, thereby satisfying different display requirements.

According to some embodiments of the present application, optionally, the ratio between k1 and k2 may be 1: X2, with X2 being a positive number. Similar to X1 above, X2 can be less than 1 and can also be greater than 1.

When X2 is less than 1, the number of light-emitting elements 102 to which the first pixel driving circuit a is connected is greater than the number of light-emitting elements 102 to which the second pixel driving circuit B is connected in the second arrangement direction, which can be applied to a scene in which the increase in luminance of the light-emitting elements 102 to which the second pixel driving circuit B is connected is greater than the decrease in luminance of the light-emitting elements 102 to which the first pixel driving circuit a is connected. Thus, the brightness of the light-emitting element 102 connected with one second pixel driving circuit B can compensate the brightness of the light-emitting elements 102 connected with a plurality of adjacent first pixel driving circuits a, so that the flicker problem is improved, the brightness uniformity of the display panel is ensured, and the mura phenomenon is avoided.

When X2 is greater than 1, the number of light-emitting elements 102 connected to the first pixel driving circuit a is smaller than the number of light-emitting elements 102 connected to the second pixel driving circuit B in the second arrangement direction, and this can be applied to a scenario in which the increase in luminance of the light-emitting elements 102 connected to the second pixel driving circuit B is smaller than the decrease in luminance of the light-emitting elements 102 connected to the first pixel driving circuit a, that is, a scenario in which the difference between the luminance of the light-emitting elements 102 connected to the second pixel driving circuit B and the theoretical luminance is smaller than the difference between the theoretical luminance and the luminance of the light-emitting elements 102 in the case where a leakage current occurs in the first pixel driving circuit a. In this way, the luminance of the light emitting element 102 connected to the plurality of second pixel driving circuits B can compensate the luminance of the light emitting element 102 connected to the adjacent first pixel driving circuit a, so that the luminance reduced by the light emitting element 102 connected to the first pixel driving circuit a can be sufficiently compensated, and the flicker problem of the display panel can be greatly improved or even eliminated.

Similarly to X1 above, in practical applications, the size of X2, that is, the ratio of the second pixel driving circuit B to the first pixel driving circuit a in the second arrangement direction, can be flexibly adjusted according to the increase amount of the luminance of the light emitting element 102 connected to the second pixel driving circuit B and the decrease amount of the luminance of the light emitting element 102 connected to the first pixel driving circuit a, which is not limited in the embodiments of the present application.

As shown in fig. 12, according to some embodiments of the present application, optionally, in the case that the ratio of k1 to k2 is 1:1, the light emitting elements 102 in one of the two adjacent second light emitting element groups D2, the second light emitting element group D2 are electrically connected to the first pixel driving circuit a, and the light emitting elements 102 in the other second light emitting element group D2 are electrically connected to the second pixel driving circuit B.

For example, when the second light emitting element group D2 includes one light emitting element 102, connection of "AB" or "BA" may be adopted, that is, in the second arrangement direction, one light emitting element 102 of the adjacent light emitting elements 102 is connected to the first pixel driving circuit a, and the other is connected to the second pixel driving circuit B. When the second light emitting element group D2 includes two light emitting elements 102, a connection manner of "AABB" or "BBAA" may be adopted, that is, in the second arrangement direction, two light emitting elements 102 in one second light emitting element group D2 in adjacent second light emitting element groups D2 are both electrically connected to the first pixel driving circuit a, and two light emitting elements 102 in the other second light emitting element group D2 are both electrically connected to the second pixel driving circuit B. When the second light emitting element group D2 includes other numbers of light emitting elements 102, similar to the case where the second light emitting element group D2 includes one light emitting element 102 or two light emitting elements 102, the description thereof is omitted.

In this way, since the light emitting elements 102 in the adjacent second light emitting element group D2 are respectively connected to the first pixel driving circuit a and the second pixel driving circuit B, that is, the second light emitting element group D2 connected to the second pixel driving circuit B and the second light emitting element group D2 connected to the first pixel driving circuit a are uniformly and alternately arranged in the second arrangement direction, the luminance of each region in the second arrangement direction can be made the same or similar, the uniformity of the luminance of the display panel is ensured, and the flicker phenomenon of the display panel is improved to a greater extent.

As shown in fig. 13, according to some embodiments of the present application, the display panel 10 may further optionally include a plurality of gate lines Sn extending in a row direction (X direction) and a plurality of data lines Dn' extending in a column direction (Y direction). Wherein the first arrangement direction may comprise a row direction. In the odd-numbered light-emitting elements 102, the first pixel driving circuit a may be electrically connected to the light-emitting elements 102 in the odd-numbered first light-emitting element group D1, and the second pixel driving circuit B may be electrically connected to the light-emitting elements 102 in the even-numbered first light-emitting element group D1. In the light emitting elements 102 in the even-numbered rows, the first pixel driving circuit a may be electrically connected to the light emitting elements 102 in the first light emitting element group D1 with the even-numbered arrangement, and the second pixel driving circuit B may be electrically connected to the light emitting elements 102 in the first light emitting element group D1 with the odd-numbered arrangement.

For example, the display panel 10 may include n rows of light emitting elements 102 arranged along the column direction, where n is a positive integer. Odd rows are understood to be rows of n that are ordered as odd, such as row 1, row 3 and row 5; even rows are understood to be rows ordered as even in n rows, such as row 2, row 4 and row 6. Similarly, each row of the light emitting elements 102 may include Q first light emitting element groups D1 arranged in the row direction, the first light emitting element group D1 with the odd arrangement number may include, for example, the first light emitting element group D1, the third first light emitting element group D1, the fifth first light emitting element group D1 and the other odd first light emitting element groups D1 arranged in the row direction, and the first light emitting element group D1 with the even arrangement number may include, for example, the second first light emitting element group D1, the fourth first light emitting element group D1, the sixth first light emitting element group D1 and the other even first light emitting element groups D1 arranged in the row direction.

As can be seen from fig. 13, the first light emitting element group D1 connected to the second pixel driving circuit B and the first light emitting element group D1 connected to the first pixel driving circuit a are not only uniformly and alternately arranged in the first arrangement direction, so that the luminances of the regions in the first arrangement direction are the same or similar, but also uniformly and alternately arranged in the second arrangement direction, so that the luminances of the regions in the second arrangement direction are the same or similar, thereby ensuring the uniformity of the luminance of the display panel to a greater extent and improving the flicker phenomenon of the display panel to a greater extent.

As shown in fig. 14, unlike the embodiment shown in fig. 13, according to other embodiments of the present application, the first arrangement direction may also be a column direction (Y direction) optionally. Accordingly, in the light emitting elements 102 in the odd-numbered rows, the first pixel driving circuit a is electrically connected to the light emitting elements 102 in the first light emitting element group D1 in the even-numbered row, and the second pixel driving circuit B is electrically connected to the light emitting elements 102 in the first light emitting element group D1 in the odd-numbered row. In the light emitting elements 102 in the even-numbered rows, the first pixel driving circuit a is electrically connected to the light emitting elements 102 in the first light emitting element group D1 with the odd-numbered arrangement, and the second pixel driving circuit B is electrically connected to the light emitting elements 102 in the first light emitting element group D1 with the even-numbered arrangement.

As can be seen from fig. 14, similar to the embodiment shown in fig. 13, the first light emitting element group D1 connected to the second pixel driving circuit B and the first light emitting element group D1 connected to the first pixel driving circuit a are not only arranged uniformly and alternately in the first arrangement direction so that the luminances of the respective regions in the first arrangement direction are the same or similar, but also arranged uniformly and alternately in the second arrangement direction so that the luminances of the respective regions in the second arrangement direction are the same or similar, thereby ensuring the uniformity of the luminance of the display panel to a greater extent and improving the flicker phenomenon of the display panel to a greater extent.

As shown in fig. 15, according to some embodiments of the present application, optionally, the pixel array 100 may include a plurality of color light emitting elements 102, and among two light emitting elements 102 of adjacent and same color, one light emitting element 102 is electrically connected to the first pixel driving circuit a, and the other light emitting element 102 is electrically connected to the second pixel driving circuit B.

For example, the pixel array 100 may include a red light emitting element R1, a green light emitting element G1, and a blue light emitting element B1. Of course, the pixel array 100 may also include other color light emitting elements, such as a white light emitting element (W light emitting element), which is not limited in this embodiment. For each color light emitting element, in some examples, there may be two light emitting elements 102 of the same color adjacent in the first arrangement direction, one light emitting element 102 being electrically connected to the first pixel driving circuit a, and the other light emitting element 102 being electrically connected to the second pixel driving circuit B. In other examples, one light emitting element 102 may be electrically connected to the first pixel driving circuit a and the other light emitting element 102 may be electrically connected to the second pixel driving circuit B, among two light emitting elements 102 of the same color that are adjacent in the second arrangement direction. In still other examples, it is also possible that, among two light emitting elements 102 adjacent in the first arrangement direction and of the same color, one light emitting element 102 is electrically connected to the first pixel driving circuit a, and the other light emitting element 102 is electrically connected to the second pixel driving circuit B, and, among two light emitting elements 102 adjacent in the second arrangement direction and of the same color, one light emitting element 102 is electrically connected to the first pixel driving circuit a, and the other light emitting element 102 is electrically connected to the second pixel driving circuit B.

Taking the red light emitting element as an example, the pixel array 100 includes a plurality of red light emitting elements arranged in a first arrangement direction (e.g., a row direction), for example. It is easy to understand that the 1 st red light emitting element is adjacent to the 2 nd red light emitting element, for example, the 1 st red light emitting element is connected to the first pixel driving circuit a, and the 2 nd red light emitting element is connected to the second pixel driving circuit B. The 2 nd red light emitting element is adjacent to the 3 rd red light emitting element, and since the 2 nd red light emitting element is connected to the second pixel driving circuit B, the 3 rd red light emitting element is connected to the first pixel driving circuit a. Similarly, the 4 th red light emitting element is connected to the second pixel driving circuit B. That is, the light emitting elements 102 of the same color connected to the first pixel driving circuit a and the second pixel driving circuit B are uniformly and alternately arranged in the first arrangement direction, so that the luminance and the chromaticity of each region of the display panel 10 in the first arrangement direction are the same or similar, that is, the uniformity of the luminance and the uniformity of the chromaticity of the display panel 10 can be ensured.

Similarly, the light emitting elements 102 of the same color connected to the first pixel driving circuit a and the second pixel driving circuit B can be arranged uniformly and alternately in the second arrangement direction, so that the luminance and the chromaticity of each region of the display panel 10 in the second arrangement direction are the same or similar, i.e., the uniformity of the luminance and the uniformity of the chromaticity of the display panel 10 can be ensured.

In addition, the light emitting elements 102 of the same color connected to the first pixel driving circuit a and the second pixel driving circuit B may be arranged uniformly and alternately in the first arrangement direction and in the second arrangement direction, so that the luminance and the chromaticity of each region of the display panel 10 in the first arrangement direction are the same or similar, the luminance and the chromaticity of each region of the display panel 10 in the second arrangement direction are the same or similar, and the uniformity of the luminance and the uniformity of the chromaticity of the display panel 10 are ensured to a greater extent.

As shown in fig. 16, according to some embodiments of the present application, each of the first light emitting element groups D1 may alternatively include a plurality of color light emitting elements, the light emitting elements 102 in one of the first light emitting element groups D1 in two adjacent first light emitting element groups D1 being electrically connected to the first pixel driving circuit a, and the light emitting elements 102 in the other first light emitting element group D1 being electrically connected to the second pixel driving circuit a.

For example, the first light emitting element group D1 may include a red light emitting element, a green light emitting element, and a blue light emitting element. In the first arrangement direction, the red light-emitting elements, the green light-emitting elements, and the blue light-emitting elements in one first light-emitting element group D1 in the adjacent first light-emitting element group D1 are all electrically connected to the first pixel driving circuit a, and the red light-emitting elements, the green light-emitting elements, and the blue light-emitting elements in the other first light-emitting element group D1 are all electrically connected to the second pixel driving circuit B.

In this way, all the multi-color light emitting elements in one first light emitting element group D1 in the adjacent first light emitting element group D1 are connected to the first pixel driving circuit a, and all the multi-color light emitting elements in the other first light emitting element group D1 are connected to the second pixel driving circuit B, so that not only can the luminance compensation between the adjacent first light emitting element groups D1 be realized, and the flicker phenomenon of the display panel be improved or even eliminated, but also the arbitrary color light emitting elements connected to the first pixel driving circuit a and the corresponding color light emitting elements connected to the second pixel driving circuit B can be ensured to be arranged in a staggered manner in the first arrangement direction, and therefore, the luminance and the chromaticity of each region in the first arrangement direction can be made to be the same or similar, and the uniformity of the luminance and the uniformity of the chromaticity of the display panel can be ensured.

Similar to the embodiment shown in fig. 16, as shown in fig. 17, according to some embodiments of the present application, optionally, each of the second light emitting element groups D2 includes light emitting elements of multiple colors, the light emitting elements 102 in one of the second light emitting element groups D2 of two adjacent second light emitting element groups D2 are electrically connected to the first pixel driving circuit a, and the light emitting elements 102 in the other second light emitting element group D2 are electrically connected to the second pixel driving circuit B.

For example, the second light emitting element group D2 may include a red light emitting element, a green light emitting element, and a blue light emitting element. In the second arrangement direction, the red light emitting element, the green light emitting element, and the blue light emitting element in one second light emitting element group D2 of the adjacent second light emitting element groups D2 are all electrically connected to the first pixel driving circuit a, and the red light emitting element, the green light emitting element, and the blue light emitting element in the other second light emitting element group D2 are all electrically connected to the second pixel driving circuit B.

In this way, all the multi-color light emitting elements in one second light emitting element group D2 in the adjacent second light emitting element group D2 are connected to the first pixel driving circuit a, and all the multi-color light emitting elements in the other second light emitting element group D2 are connected to the second pixel driving circuit B, so that not only can the luminance compensation between the adjacent second light emitting element groups D2 be realized, and the flicker phenomenon of the display panel be improved or even eliminated, but also the arbitrary color light emitting elements connected to the first pixel driving circuit a and the corresponding color light emitting elements connected to the second pixel driving circuit B can be ensured to be arranged in a staggered manner in the second arrangement direction, and therefore, the luminance and the chromaticity of each region in the second arrangement direction can be made to be the same or similar, and the uniformity of the luminance and the uniformity of the chromaticity of the display panel can be ensured.

To facilitate understanding of the embodiments of the present application, the first pixel driving circuit a and the second pixel driving circuit B are described below with reference to some embodiments.

As described above, in the embodiment of the present application, each of the first pixel driving circuit a and the second pixel driving circuit B includes the driving module 11 and the first switching module 12. As shown in fig. 18, according to some embodiments of the present application, the driving module 11 may optionally include a first transistor T1, a gate of the first transistor T1 is electrically connected to the first node N1, a first pole of the first transistor T1 is electrically connected to the first pole of the light emitting element 102, and a second pole of the first transistor T1 is electrically connected to the first power voltage signal line PVDD. The first switching module 12 may include at least two first switching elements 121, each of the first switching elements 121 may include a second transistor T2, at least two second transistors T2 are arranged in series, gates of the at least two second transistors T2 are each electrically connected to the scan signal line S, and a first pole of one second transistor T2 of the at least two second transistors T2 is electrically connected to the first node N1.

As shown in fig. 19, according to some embodiments of the present application, optionally, in order to satisfy (V12-V11) × (V22-V21) < 0, the second pixel driving circuit B may further include a node control module 13, a control terminal of the node control module 13 is electrically connected to the first scan signal line S1, a first terminal of the node control module 13 is electrically connected to the reference signal line Vref, a second terminal of the node control module 13 is electrically connected to the second node N2, and the node control module 13 is configured to transmit the reference signal output by the reference signal line Vref to the second node N2 under the control of the first scan signal output by the first scan signal line S1, so as to pull down the voltage value of the second node N2.

Specifically, in the light emission period t3, the first scan signal is at the on level. The node control module 13 is turned on in response to the on level, and transmits the reference signal output from the reference signal line Vref to the second node N2. Since the voltage value of the reference signal is smaller than the voltage value of the first node N1 in the second pixel driving circuit B, for example, a negative voltage value, the voltage value of the second node N2 of the second node N2 is pulled low after the reference signal is inputted, so that the voltage value of the second node N2 in the second pixel driving circuit B is smaller than the voltage value of the first node N1 in the second pixel driving circuit B.

In this way, by adding the node control module 13 in the second pixel driving circuit B, the voltage value of the second node N2 in the second pixel driving circuit B can be pulled down at the lighting phase t3, so that the voltage value of the second node N2 in the second pixel driving circuit B is smaller than the voltage value of the first node N1 in the second pixel driving circuit B, the first node N1 leaks current to the second node N2, so that the brightness of the light emitting element 102 connected to the second pixel driving circuit B is increased, the brightness of the light emitting element 102 connected to the first pixel driving circuit a is compensated, the brightness of different light emitting elements 102 in the display panel is compensated with each other, and the flicker phenomenon is improved or even eliminated.

As shown in fig. 20, according to some embodiments of the present disclosure, the node control module 13 may optionally include a third transistor T3, a gate of the third transistor T3 is electrically connected to the first scan signal line S1, a first pole of the third transistor T3 is electrically connected to the reference signal line Vref, a second pole of the third transistor T3 is electrically connected to the second node N2, and the third transistor T3 is configured to transmit the reference signal output from the reference signal line Vref to the second node N2 under the control of the first scan signal output from the first scan signal line S1 so as to pull down the voltage value of the second node N2.

In the light emitting period t3, the first scan signal is at the on level. The third transistor T3 is turned on in response to the on level, and transmits the reference signal output from the reference signal line Vref to the second node N2. Since the voltage value of the reference signal is smaller than the voltage value of the first node N1 in the second pixel driving circuit B, for example, a negative voltage value, the voltage value of the second node N2 of the second node N2 is pulled low after the reference signal is inputted, so that the voltage value of the second node N2 in the second pixel driving circuit B is smaller than the voltage value of the first node N1 in the second pixel driving circuit B.

As shown in fig. 19, according to some embodiments of the present application, optionally, the second pixel driving circuit B may further include a first light emitting control module 14 and a second light emitting control module 15. A control end of the first light-emitting control module 14 is electrically connected to the control signal line EM, a first end of the first light-emitting control module 14 is electrically connected to the first power voltage signal line PVDD, and a second end of the first light-emitting control module 14 is electrically connected to the second end of the driving module 11. A control terminal of the second light emission control module 15 is electrically connected to the control signal line EM, a first terminal of the second light emission control module 15 is electrically connected to a first terminal of the driving module 11, and a second terminal of the second light emission control module 15 is electrically connected to a first pole of the light emitting element 102. Alternatively, the first scanning signal line S1 is multiplexed with the control signal line EM.

In the light emission period t3, the control signal line EM outputs the on level. The first light emission control module 14 and the second light emission control module 15 are turned on in response to the on level output from the control signal line EM, and control the light emitting element 102 to emit light. Meanwhile, the node control module 13 is turned on in response to the on level output from the control signal line EM, and transmits the reference signal output from the reference signal line Vref to the second node N2.

In this way, the first scanning signal line S1 for controlling the on/off of the node control module 13 multiplexes the control signal line EM in the second pixel driving circuit B, which can reduce the number of wirings in the display panel, is beneficial to the light and thin and narrow frame design of the display panel, and reduces the production cost of the display panel.

As shown in fig. 20, according to some embodiments of the present application, the first lighting control module 14 may optionally include a fourth transistor T4, a gate of the fourth transistor T4 being electrically connected to the control signal line EM, a first pole of the fourth transistor T4 being electrically connected to the first power voltage signal line PVDD, and a second pole of the fourth transistor T4 being electrically connected to the second pole of the first transistor T1. The second light emission control module 15 may include a fifth transistor T5, a gate of the fifth transistor T5 being electrically connected to the control signal line EM, a first pole of the fifth transistor T5 being electrically connected to the first pole of the first transistor T1, and a second pole of the fifth transistor T5 being electrically connected to the first pole of the light emitting element 102.

In the light emission period t3, the control signal line EM outputs the on level. The fourth transistor T4 and the fifth transistor T5 are turned on in response to the on level output from the control signal line EM, and control the light emitting element 102 to emit light. Meanwhile, the third transistor T3 is turned on in response to the on level output from the control signal line EM, and transmits the reference signal output from the reference signal line Vref to the second node N2.

In this way, the first scan signal line S1 controlling the third transistor T3 to be turned on/off multiplexes the control signal line EM in the second pixel driving circuit B, which can reduce the number of wirings in the display panel, facilitate the light and thin display panel and narrow frame design, and reduce the production cost of the display panel.

According to some embodiments of the present application, the first switching module 12 may optionally be a first node reset module (not shown) for resetting the first node N1. Specifically, as shown in fig. 21, the first switch module 12 includes at least two first switch elements 121, control terminals of the at least two first switch elements 121 are electrically connected to the scan signal line S, a first terminal of one of the at least two first switch elements 121 is electrically connected to a first node N1, a first terminal of another one of the at least two first switch elements 121 is electrically connected to a reference signal line Vref, and the first switch module 12 is configured to transmit a reference signal output from the reference signal line Vref to a first node N1 under control of a scan signal output from the scan signal line S to reset the first node N1.

Specifically, in the reset phase t1, the scan signal line S outputs the on level. The at least two first switching elements 121 are turned on in response to the turn-on level output from the scan signal line S, and transmit the reference signal output from the reference signal line Vref to the first node N1 to reset the first node N1.

According to some embodiments of the present application, the first switching module 12 may optionally be a threshold compensation module (not shown in the figures) for threshold compensation of the driving module 11. Specifically, as shown in fig. 22, the first switch module 12 includes at least two first switch elements 121, control terminals of the at least two first switch elements 121 are electrically connected to the scan signal line S, a first terminal of one of the at least two first switch elements 121 is electrically connected to a first node N1, a first terminal of one of the at least two first switch elements 121 is electrically connected to a third node N3, the third node N3 is located between the first terminal of the driving module 11 and the first pole of the light emitting element 102, and the first switch module 12 is configured to switch on the control terminal of the driving module 11 and the first terminal of the driving module 11 under the control of the scan signal output by the scan signal line S.

Specifically, in the embodiment different from that shown in fig. 21, in the data writing phase t2, the scanning signal line S outputs the on level. The at least two first switching elements 121 are turned on in response to the turn-on level output by the scanning signal line S, and turn on the control terminal of the driving module 11 and the first terminal of the driving module 11, so as to compensate the threshold voltage of the driving module 11 under the action of the data signal.

According to some embodiments of the present application, the first switching module 12 may optionally include both a first node reset module that resets the first node N1 and a threshold compensation module that threshold compensates the driving module 11. Specifically, as shown in fig. 23, the first switch module 12 may include a first sub-switch module 122 and a second sub-switch module 123, and the second node N2 may include a first sub-node N21 and a second sub-node N22.

The first sub-switching module 122 may include at least two first sub-switching elements 122a, the at least two first sub-switching elements 122a being arranged in series, control terminals of the at least two first sub-switching elements 122a each being electrically connected to the second scan signal line S2, a first terminal of one of the at least two first sub-switching elements 122a being electrically connected to a first node N1, a first terminal of another one of the at least two first sub-switching elements 122a being electrically connected to a reference signal line Vref, the first sub-node N21 being a connection node between different ones of the at least two first sub-switching elements 122a, the first sub-switching module 122 being configured to transmit the reference signal output from the reference signal line Vref to the first node N1 under control of the second scan signal output from the second scan signal line S2 to reset the first node N1.

Specifically, in the reset phase t1, the second scan signal line S2 outputs an on level. The at least two first sub switching elements 122a are turned on in response to the turn-on level output from the second scan signal line S2, and transmit the reference signal output from the reference signal line Vref to the first node N1 to reset the first node N1.

The second sub-switching module 123 may include at least two second sub-switching elements 123a, the at least two second sub-switching elements 123a being arranged in series, control terminals of each of the at least two second sub-switching elements 123a being electrically connected to the third scan signal line S3, a first terminal of one of the at least two second sub-switching elements 123a being electrically connected to the first node N1, and a first terminal of another one of the at least two second sub-switching elements 123a being electrically connected to the third node N3. As shown in fig. 24, the third node N3 is located between the first terminal of the driving module 11 and the first pole of the light emitting element 102, and the second sub-node N22 is a connection node between different second sub-switching elements 123a of the at least two second sub-switching elements 123 a. The second sub-switch module 123 may be configured to switch on the control terminal of the driving module 11 and the first terminal of the driving module 11 under the control of the third scan signal output by the third scan signal line S3.

Specifically, in the data writing phase t2, the third scan signal line S3 outputs an on level. The at least two second sub-switching elements 123a are turned on in response to the turn-on level output from the third scan signal line S3, and turn on the control terminal of the driving module 11 and the first terminal of the driving module 11, so as to compensate for the threshold voltage of the driving module 11 under the action of the data signal.

In the light emitting period t3, the relationship among the voltage value of the first node N1 in the first pixel driving circuit a, the voltage value of the first sub-node N21 in the first pixel driving circuit a, and the voltage value of the second sub-node N22 in the first pixel driving circuit a includes:

(V122-V11)＞(V121-V11) (2)

where V122 denotes a voltage value of the second sub-node N22 in the first pixel driving circuit a, V11 denotes a voltage value of the first node N1 in the first pixel driving circuit a, and V121 denotes a voltage value of the first sub-node N21 in the first pixel driving circuit a.

As can be seen from the above expression (2), in the light emitting period t3, the voltage value of the second sub-node N22 in the first pixel driving circuit a is higher than the voltage value of the first sub-node N21 in the first pixel driving circuit a. This is because the voltage value of the reference signal output from the reference signal line Vref is lower than that of the data signal, and therefore the potential of the second sub-node N22 is higher than that of the first sub-node N21 before the capacitive decoupling, so that the potential of the second sub-node N22 in the first pixel driving circuit a is still higher than that of the first sub-node N21 in the first pixel driving circuit a in the case where the magnitude of the boosted voltage value is the same or similar, i.e., after the capacitive coupling.

Unlike the first pixel driving circuit a, in the light emitting period t3, a relationship among a voltage value of the first node N1 in the second pixel driving circuit B, a voltage value of the first sub-node N21 in the second pixel driving circuit B, and a voltage value of the second sub-node N22 in the second pixel driving circuit B includes:

(V222-V21)＝(V221-V21) (3)

where V222 denotes a voltage value of the second sub-node N22 in the second pixel driving circuit B, V21 denotes a voltage value of the first node N1 in the second pixel driving circuit B, and V221 denotes a voltage value of the first sub-node N21 in the second pixel driving circuit B.

As can be seen from the above expression (3), in the light emission period t3, the voltage value of the first sub-node N21 in the second pixel driving circuit B is equal to the voltage value of the second sub-node N22 in the first pixel driving circuit a. This is because, in the lighting period t3, the node control module 13 in the second pixel driving circuit B is turned on in response to the turn-on level, and transmits the reference signal output from the reference signal line Vref to the first sub-node N21 and the second sub-node N22 in the second pixel driving circuit B, so that the voltage values of the first sub-node N21 and the second sub-node N22 are both pulled down to the same voltage value.

Fig. 24 schematically illustrates a second pixel driving circuit B in some embodiments of the present application. As shown in fig. 24, the first sub-switching module 122 may include a double-gate transistor T21, and the first sub-node N21 may be a connection node between two transistors of the double-gate transistor T21. The gates of both of the double gate transistors T21 are electrically connected to the second scan signal line S2, the first gate of one of the double gate transistors T21 is electrically connected to the first node N1, and the first gate of the other of the double gate transistors T21 is electrically connected to the reference signal line Vref. In the reset phase T1, the dual-gate transistor T21 transmits the reference signal output from the reference signal line Vref to the first node N1 under the control of the second scan signal output from the second scan signal line S2 to reset the first node N1.

The second sub-switching module 123 may include a double-gate transistor T22, and the second sub-node N22 may be a connection node between two transistors of the double-gate transistor T22. The gates of both of the dual gate transistors T22 are electrically connected to the third scan signal line S3, the first gate of one of the dual gate transistors T22 is electrically connected to the first node N1, and the first gate of the other of the dual gate transistors T22 is electrically connected to the third node N3. In the data writing phase T2, the dual-gate transistor T22 turns on the control terminal of the driving block 11 and the first terminal of the driving block 11 under the control of the third scan signal outputted from the third scan signal line S3 to compensate the threshold voltage of the first transistor T1 under the action of the data signal.

According to some embodiments of the present application, optionally, the first scanning signal line S1 and the control signal line EM may be multiplexed, so as to reduce the number of traces in the display panel and reduce the cost.

In addition to the transistors mentioned above, the second pixel driving circuit B may further include:

a sixth transistor T6, a gate of the sixth transistor T6 is electrically connected to the third scan signal line S3, a first pole of the sixth transistor T6 is electrically connected to the data signal line Vdata, and a second pole of the sixth transistor T6 is electrically connected to the first pole of the first transistor T1, and is used for writing a data signal under the control of the third scan signal output from the third scan signal line S3.

A seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to the second scan signal line S2, a first pole of the seventh transistor T7 is electrically connected to the reference signal line Vref, and a second pole of the seventh transistor T7 is electrically connected to the first pole of the light emitting element 102, and is configured to transmit the reference signal output from the reference signal line Vref to the first pole of the light emitting element 102 under the control of the second scan signal output from the second scan signal line S2, so as to reset the first pole of the light emitting element 102. The first electrode of the light emitting element 102 may be an anode of the light emitting element 102.

The storage capacitor C1, the first plate of the storage capacitor C1 is electrically connected to the first node N1, and the second plate of the storage capacitor C1 is electrically connected to the first power voltage signal line PVDD, for maintaining the potential of the first node N1.

Fig. 25 is a timing chart of the second pixel driving circuit B shown in fig. 24. As shown in fig. 24 and 25 in conjunction, in the reset phase t1, the second scan signal line S2 outputs an on level, and the third scan signal line S3 and the control signal line EM output an off level. The double gate transistor T21 is turned on in response to the turn-on level of the second scan signal line S2, and transmits the reference signal output from the reference signal line Vref to the first node N1 to reset the first node N1. The seventh transistor T7 is turned on in response to the on level of the second scan signal line S2, and transmits the reference signal output from the reference signal line Vref to the first pole of the light emitting element 102 to reset the first pole of the light emitting element 102. In the data writing phase t2, the third scanning signal line S3 outputs an on level, and the second scanning signal line S2 and the control signal line EM output an off level. The sixth transistor T6 and the dual gate transistor T22 are turned on in response to the turn-on level of the third scan signal line S3, and compensate for the threshold voltage Vth of the first transistor T1 while writing the data signal output from the data signal line Vdata to the first node N1. In the light-emitting period t3, the control signal line EM outputs the on level, and the second scanning signal line S2 and the third scanning signal line S3 output the off level. The fourth transistor T4 and the fifth transistor T5 are turned on in response to the turn-on level of the control signal line EM, the first transistor T1 is turned on under the control of the first node N1, and the driving current supplied from the first power voltage signal line PVDD flows into the first pole of the light emitting element 102 through the fourth transistor T4, the first transistor T1, and the fifth transistor T5, driving the light emitting element 102 to emit light. At the same stage, the third transistor T3 is turned on in response to the on level of the control signal line EM, and transmits the reference signal outputted from the reference signal line Vref to the first sub-node N21 and the second sub-node N22, so as to pull down the voltage values of the first sub-node N21 and the second sub-node N22 to be less than the voltage value of the first node N1, thereby allowing the first node N1 to leak current to the first sub-node N21 and the second sub-node N22. As the voltage value of the first node N1 gradually decreases, the degree of conduction of the first transistor T1 increases, so that the driving current flowing into the light emitting element 102 increases and the luminance of the light emitting element 102 gradually increases.

Fig. 26 schematically shows drive current variation curves of the first pixel drive circuit a and the second pixel drive circuit B. As shown in fig. 26, in the light emission period t3 of each frame, as time increases, the drive current of the first pixel drive circuit a decreases from the first 80.45nA to 79.36nA at the end of the frame, and the change in the drive current is (80.45-79.36)/80.45-1.35%. And as time goes up, the drive current of the second pixel drive circuit B rises from the first 80.77nA to 81.91nA at the end of the frame. In the case where the ratio of the first pixel driving circuit a to the second pixel driving circuit B is 1:1, the average value of the drive current of the entire display panel is: the lighting period t3 starts at (80.45+80.77)/2 equals 80.61nA per frame, and ends at (i.e., the end of each frame) t3 at (81.91+79.36)/2 equals 80.63nA per frame, and the change in driving current or the change in brightness is only 0.03%, thereby improving the flicker phenomenon.

Based on the display panel provided in the foregoing embodiment, correspondingly, the present application also provides a display device, as shown in fig. 27, the display device 1000 may include an apparatus body 20 and the display panel 10 in the foregoing embodiment, and the display panel 10 is covered on the apparatus body 20. The apparatus body 20 may be provided with various devices, such as a sensing device, a processing device, and the like, but is not limited thereto. The display device 1000 may be a device having a display function, such as a mobile phone, a computer, a tablet computer, a digital camera, a television, and electronic paper, and is not limited herein.

It should be clear that the embodiments in this specification are described in a progressive manner, and the same or similar parts in the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. For the display panel embodiment and the display device embodiment, the related matters can be referred to the description parts of the pixel driving circuit embodiment and the array substrate embodiment. The present application is not limited to the particular structures described above and shown in the figures. Those skilled in the art may make various changes, modifications and additions after comprehending the spirit of the present application. Also, a detailed description of known techniques is omitted herein for the sake of brevity.

It will be appreciated by persons skilled in the art that the above embodiments are illustrative and not restrictive. Different features which are present in different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art upon studying the drawings, the specification, and the claims. In the claims, the term "comprising" does not exclude other structures; the quantities relate to "a" and "an" but do not exclude a plurality; the terms "first" and "second" are used to denote a name and not to denote any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.