阅读说明：本技术 驱动电路和驱动方法，以及显示装置 (Driving circuit and driving method, and display device ) 是由 孙建 王珍 许梦兴 山岳 秦文文 杨小艳 王继国 张寒 王德帅 闫伟 张健 张 于 2020-06-09 设计创作，主要内容包括：本发明公开了驱动电路和驱动方法,以及显示装置。该驱动电路的驱动芯片被配置为向栅极驱动单元提供栅极驱动信号,并通过数据总线向多路复用单元提供源极驱动信号,驱动电路包括第一极性数据总线和第二极性数据总线,每个多路复用单元与一个数据总线相连,并将源极驱动信号输出至多个数据线上,每个数据线与一个像素列相连,位于同一行的多个第三子像素与第一极性数据总线和第二极性数据总线相连；位于同一行的多个第四子像素与所述第一极性数据总线和所述第二极性数据总线相连。由此,可令每一像素行中颜色相同的子像素均具有相反的极性。(The invention discloses a driving circuit and a driving method, and a display device. The driving chip of the driving circuit is configured to provide a gate driving signal to the gate driving unit and provide a source driving signal to the multiplexing units through the data buses, the driving circuit includes a first polarity data bus and a second polarity data bus, each multiplexing unit is connected with one data bus and outputs the source driving signal to a plurality of data lines, each data line is connected with one pixel column, and a plurality of third sub-pixels located in the same row are connected with the first polarity data bus and the second polarity data bus; a plurality of fourth sub-pixels located in the same row are connected to the first polarity data bus line and the second polarity data bus line. Therefore, the sub-pixels with the same color in each pixel row have opposite polarities.)

1. A driving circuit of a liquid crystal display panel, the liquid crystal display panel having a plurality of pixel units arranged in an array, the pixel unit including 6 sub-pixels, the 6 sub-pixels being arranged in two pixel rows and three pixel columns, a first pixel column having two first sub-pixels, a second pixel column having two second sub-pixels, a third pixel column having one third sub-pixel and one fourth sub-pixel, the third sub-pixel and the fourth sub-pixel of the third pixel column being arranged in an opposite order in two adjacent pixel units in a direction in which the pixel rows extend, the driving circuit including a driving chip, a gate driving unit, and a plurality of multiplexing units,

the driving chip is configured to provide a gate driving signal to the gate driving unit and a source driving signal to the multiplexing unit through a data bus,

the driving circuit comprises a first polarity data bus and a second polarity data bus, each multiplexing unit is connected with one data bus and outputs the source electrode driving signal to a plurality of data lines, each data line is connected with one pixel column,

a part of the plurality of third sub-pixels in the same row is connected to the first polarity data bus line, and the other part is connected to the second polarity data bus line;

and one part of the plurality of fourth sub-pixels in the same row is connected with the first polarity data bus, and the other part of the plurality of fourth sub-pixels in the same row is connected with the second polarity data bus.

2. The driving circuit of claim 1, wherein the first sub-pixel is red, the second sub-pixel is green, the third sub-pixel is blue, and the fourth sub-pixel is white,

the opening area of the first sub-pixel is the same as that of the second sub-pixel, the ratio of the opening area of the fourth sub-pixel to that of the first sub-pixel is 0.3-0.6, and the opening area of the third sub-pixel is 1.5-2.5 times that of the first sub-pixel.

3. The driving circuit according to claim 2, wherein the third sub-pixel and the fourth sub-pixel have the same width, the length of the third sub-pixel is 1.5-2.5 times the length of the fourth sub-pixel,

the width of the third sub-pixel is larger than that of the first sub-pixel, and the length of the third sub-pixel is larger than that of the first sub-pixel.

4. The drive circuit according to claim 1, wherein the multiplexing unit includes:

the input end is connected with the data bus and used for receiving the source electrode driving signal;

the data line comprises three control ends and three output ends, wherein the control ends receive control signals, each control end is used for controlling the output of one output end, and the three output ends are respectively connected with different data lines.

5. The drive circuit according to claim 4, wherein the drive circuit comprises a plurality of multiplexing unit groups having a first multiplexing unit, a second multiplexing unit, a third multiplexing unit, and a fourth multiplexing unit,

the source driving signals output by the first multiplexing unit and the third multiplexing unit have a first polarity, the source driving signals output by the second multiplexing unit and the fourth multiplexing unit have a second polarity, and the driving circuit can apply voltage to the data lines in a period of 12 sub-pixel columns.

6. The driving circuit according to claim 5, wherein the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are arranged in order along a direction in which the pixel row extends,

the first multiplexing unit is connected with one first polarity data bus and has a first polarity, a first output end of the first multiplexing unit is connected with a first pixel column of the first pixel unit, a second output end of the first multiplexing unit is connected with a third pixel column of the first pixel unit, and the third output end of the first multiplexing unit is connected with a second pixel column of the second pixel unit;

the second multiplexing unit is connected with one second polarity data bus to have a second polarity, a first output end of the second multiplexing unit is connected with the second pixel column of the first pixel unit, a second output end of the second multiplexing unit is connected with the first pixel column of the second pixel unit, and a third output end of the second multiplexing unit is connected with the third pixel column of the second pixel unit;

the third multiplexing unit is connected with the other first polarity data bus to have the first polarity, a first output end of the third multiplexing unit is connected with the first pixel column of the third pixel unit, a second output end of the third multiplexing unit is connected with the second pixel column of the fourth pixel unit, and a third output end of the third multiplexing unit is connected with the third pixel column of the fourth pixel unit;

the fourth multiplexing unit is connected with the other second polarity data bus to have the second polarity, a first output end of the fourth multiplexing unit is connected with the second pixel column of the third pixel unit, a second output end of the fourth multiplexing unit is connected with the third pixel column of the third pixel unit, and a third output end of the fourth multiplexing unit is connected with the first pixel column of the fourth pixel unit,

the first pixel column has a plurality of red subpixels, the second pixel column has a plurality of green subpixels, and the third pixel column has a plurality of white and blue subpixels.

7. The driving circuit according to any of claims 1-6, comprising a plurality of cascaded gate driving units, wherein the gate driving units comprise a gate input terminal for receiving the gate driving signal, a clock input terminal, a reset input terminal, and an output terminal,

the four grid driving units comprise a first-stage grid driving unit, a second-stage grid driving unit, a third-stage grid driving unit and a fourth-stage grid driving unit,

the output terminal of the third gate driving unit is connected to the reset input terminal of the first gate driving unit, the output terminal of the first gate driving unit is connected to the gate input terminal of the third gate driving unit,

the clock input ends of the first-stage grid driving unit and the third-stage grid driving unit are connected with a first grid clock signal and a third grid clock signal, and the clock input ends of the second-stage grid driving unit and the fourth-stage grid driving unit are connected with a second grid clock signal and a fourth grid clock signal.

8. A method of driving the driver circuit according to any one of claims 1 to 7, comprising:

and providing a gate driving signal to the gate driving unit by using a driving chip to scan the pixel rows line by line, providing a source driving signal to the multiplexing unit through a data bus by using the driving chip and applying a voltage to the data line so that the sub-pixels positioned in the same column have the same polarity, and the sub-pixels positioned in the same row and having the same color can have opposite polarities.

9. The method according to claim 8, wherein the voltage is applied to the data lines in a cycle at every adjacent 12 pixel columns,

outputting a first polarity voltage signal to the data lines of the first pixel column of the first pixel unit, the third pixel column and the second pixel column of the second pixel unit using a first multiplexing unit connected to a first polarity data bus line,

outputting a second polarity voltage signal to the data lines of the second pixel column of the first pixel unit, the first pixel column of the second pixel unit, and the third pixel column using a second multiplexing unit connected to a second polarity data bus line,

outputting the first polarity voltage signals to the data lines of a first pixel column of a third pixel unit and a second pixel column and a third pixel column of the fourth pixel unit by using a third multiplexing unit connected with another first polarity data bus,

outputting the second polarity voltage signal to the data lines of the second pixel column of the third pixel unit, the third pixel column, and the first pixel column of the fourth pixel unit using a fourth multiplexing unit connected to another one of the second polarity data buses,

the first pixel column has a plurality of red subpixels, the second pixel column has a plurality of green subpixels, and the third pixel column has a plurality of white and blue subpixels.

10. The method of claim 9, wherein the control signals are applied to the plurality of control terminals of the multiplexing unit in sequence to turn on the plurality of output terminals of the multiplexing unit in an order from the first pixel column, the second pixel column, and the third pixel column.

11. The method according to claim 10, wherein the source driving signals sent by the driver chip to the input terminals of the first multiplexing unit and the fourth multiplexing unit use a first set of clock signals, and the source driving signals sent to the input terminals of the second multiplexing unit and the third multiplexing unit use a second set of clock signals, and the first set of clock signals and the second set of clock signals are not turned on at the same time.

12. The method of claim 8, wherein the polarity of each of the pixel columns is inverted every predetermined time interval.

13. A display panel, comprising: a drive circuit as claimed in any one of claims 1 to 7.

Technical Field

The present invention relates to the field of display, and in particular, to a driving circuit and a driving method, and a display device.

Background

In order to improve the transmittance of the panel, the liquid crystal display device, especially designed based on RGB pixels, can replace half of the B pixels with W pixels on the basis of the original RGB pixels, so as to achieve the effects of improving the overall transmittance of the panel and reducing the backlight power consumption. But when the RGBW pixel design is not properly designed to connect with the multiplexing circuit (MUX), poor crosstalk will occur.

Therefore, liquid crystal display devices, particularly driving circuits and driving methods based on RGBW pixel designs, and display devices still need to be improved.

Disclosure of Invention

The invention provides a driving circuit based on a liquid crystal display panel. The liquid crystal display panel has a plurality of pixel units arranged in an array, the pixel unit including 6 sub-pixels, the 6 sub-pixels being arranged in two pixel rows and three pixel columns, a first pixel column having two first sub-pixels, a second pixel column having two second sub-pixels, a third pixel column having one third sub-pixel and one fourth sub-pixel, the arrangement order of the third sub-pixel and the fourth sub-pixel of the third pixel column among two of the pixel units adjacent in a direction in which the pixel rows extend being opposite, the driving circuit including a driving chip, a gate driving unit, and a plurality of multiplexing units, the driving chip being configured to supply a gate driving signal to the gate driving unit and supply a source driving signal to the multiplexing unit through a data bus, the driving circuit including a first polarity data bus and a second polarity data bus, each multiplexing unit is connected with a data bus and outputs the source driving signal to a plurality of data lines, each data line is connected with a pixel column, one part of a plurality of third sub-pixels in the same row is connected with the first polarity data bus, and the other part of the plurality of third sub-pixels in the same row is connected with the second polarity data bus; and one part of the plurality of fourth sub-pixels in the same row is connected with the first polarity data bus, and the other part of the plurality of fourth sub-pixels in the same row is connected with the second polarity data bus. Therefore, the sub-pixels with the same color in each pixel row have opposite polarities, so that the coupling to the common electrode (VCOM) during display caused by the consistent polarities of the sub-pixels with the same color in the same row can be relieved and even solved, and the cross color problem caused by the change of the voltage difference between the common electrode and the pixel electrode can be relieved.

According to an embodiment of the present invention, the first sub-pixel is red, the second sub-pixel is green, the third sub-pixel is blue, the fourth sub-pixel is white, the aperture area of the first sub-pixel is the same as the aperture area of the second sub-pixel, a ratio of the aperture area of the fourth sub-pixel to the aperture area of the first sub-pixel is 0.3 to 0.6, and the aperture area of the third sub-pixel is 1.5 to 2.5 times the aperture area of the first sub-pixel. Therefore, the PPI can be kept from being reduced while the transmittance is improved.

According to the embodiment of the present invention, the widths of the third sub-pixel and the fourth sub-pixel are the same, the length of the third sub-pixel is 1.5-2.5 times the length of the fourth sub-pixel, the width of the third sub-pixel is greater than the width of the first sub-pixel, and the length of the third sub-pixel is greater than the length of the first sub-pixel. Therefore, the PPI can be kept from being reduced while the transmittance is improved.

According to an embodiment of the present invention, the multiplexing unit includes: the input end is connected with the data bus and used for receiving the source electrode driving signal; the data line comprises three control ends and three output ends, wherein the control ends receive control signals, each control end is used for controlling the output of one output end, and the three output ends are respectively connected with different data lines. Therefore, the source driving can be carried out on the 3 columns of sub-pixels by using one source driving signal, so that the size of a driving chip can be reduced, and the cost can be reduced.

According to an embodiment of the present invention, the driving circuit includes a plurality of multiplexing unit groups having a first multiplexing unit, a second multiplexing unit, a third multiplexing unit, and a fourth multiplexing unit, the source driving signals output from the first multiplexing unit and the third multiplexing unit each have a first polarity, the source driving signals output from the second multiplexing unit and the fourth multiplexing unit each have a second polarity, and the driving circuit may apply the voltage to the data lines in a cycle of every 12 sub-pixel columns using the first multiplexing unit, the second multiplexing unit, the third multiplexing unit, and the fourth multiplexing unit. Thus, it is possible to achieve that the sub-pixels of the plurality of colors in each pixel row may have opposite polarities.

According to the embodiment of the present invention, along the extending direction of the pixel row, the first pixel unit, the second pixel unit, the third pixel unit and the fourth pixel unit are sequentially arranged, the first multiplexing unit is connected to one of the first polarity data buses and has a first polarity, the first output end of the first multiplexing unit is connected to the first pixel column of the first pixel unit, the second output end of the first multiplexing unit is connected to the third pixel column of the first pixel unit, and the third output end of the first multiplexing unit is connected to the second pixel column of the second pixel unit; the second multiplexing unit is connected with one second polarity data bus to have a second polarity, a first output end of the second multiplexing unit is connected with the second pixel column of the first pixel unit, a second output end of the second multiplexing unit is connected with the first pixel column of the second pixel unit, and a third output end of the second multiplexing unit is connected with the third pixel column of the second pixel unit; the third multiplexing unit is connected with the other first polarity data bus to have the first polarity, a first output end of the third multiplexing unit is connected with the first pixel column of the third pixel unit, a second output end of the third multiplexing unit is connected with the second pixel column of the fourth pixel unit, and a third output end of the third multiplexing unit is connected with the third pixel column of the fourth pixel unit; the fourth multiplexing unit is connected with another second polarity data bus to have the second polarity, a first output end of the fourth multiplexing unit is connected with the second pixel column of the third pixel unit, a second output end of the fourth multiplexing unit is connected with the third pixel column of the third pixel unit, a third output end of the fourth multiplexing unit is connected with the first pixel column of the fourth pixel unit, the first pixel column is provided with a plurality of red sub-pixels, the second pixel column is provided with a plurality of green sub-pixel columns, and the third pixel column is provided with a plurality of white and blue sub-pixels. Therefore, the sub-pixels with different colors in the same pixel row can be simply made to have opposite polarities.

According to an embodiment of the present invention, the driving circuit includes a plurality of cascaded gate driving units, the gate driving units include a gate input terminal, a clock input terminal, a reset input terminal and an output terminal for receiving the gate driving signal, four of the gate driving units include a first stage gate driving unit, a second stage gate driving unit, a third stage gate driving unit and a fourth stage gate driving unit, the output terminal of the third gate driving unit is connected to the reset input terminal of the first gate driving unit, the output terminal of the first gate driving unit is connected to the gate input terminal of the third gate driving unit, the clock input terminals of the first stage gate driving unit and the third stage gate driving unit are both connected to a first gate clock signal and a third gate clock signal, the clock input ends of the second-stage grid driving unit and the fourth-stage grid driving unit are connected with a second grid clock signal and a fourth grid clock signal. This can further improve the performance of the drive circuit.

In a further aspect of the invention, the invention proposes a method of driving a drive circuit as described above. The method comprises the following steps: and providing a gate driving signal to the gate driving unit by using a driving chip to scan the pixel rows line by line, providing a source driving signal to the multiplexing unit through a data bus by using the driving chip and applying a voltage to the data line so that the sub-pixels positioned in the same column have the same polarity, and the sub-pixels positioned in the same row and having the same color can have opposite polarities. Therefore, the coupling of the common electrode (VCOM) in the display process caused by the consistent polarity of the same-color sub-pixels in the same row can be relieved and even solved, and the cross color problem caused by the change of the voltage difference between the common electrode and the pixel electrode can be relieved.

According to the embodiment of the present invention, voltages are applied to the data lines in cycles every 12 adjacent pixel columns, a first polarity voltage signal is output to the data lines of a first pixel column of a first pixel unit, a third pixel column, and a second pixel column of a second pixel unit using a first multiplexing unit connected to one first polarity data bus line, a second polarity voltage signal is output to the data lines of a second pixel column of the first pixel unit, a first pixel column of the second pixel unit, and a third pixel column using a second multiplexing unit connected to one second polarity data bus line, and the first polarity voltage signal is output to the first pixel column of a third pixel unit and the second pixel column of the fourth pixel unit, the data lines of a third pixel column using a third multiplexing unit connected to the other first polarity data bus line, outputting the second polarity voltage signal to the data lines of a second pixel column of the third pixel unit, a third pixel column and a first pixel column of the fourth pixel unit by using a fourth multiplexing unit connected to another second polarity data bus, the first pixel column having a plurality of red sub-pixels, the second pixel column having a plurality of green sub-pixel columns, and the third pixel column having a plurality of white and blue sub-pixels.

According to an embodiment of the present invention, control signals are sequentially applied to the plurality of control terminals of the multiplexing unit to turn on the plurality of output terminals of the multiplexing unit in an order from the first pixel column, the second pixel column, to the third pixel column. This can further improve the effect of display by the driving method.

According to an embodiment of the present invention, the source driving signals sent by the driving chip to the input terminals of the first multiplexing unit and the fourth multiplexing unit use a first set of clock signals, the source driving signals sent to the input terminals of the second multiplexing unit and the third multiplexing unit use a second set of clock signals, and the first set of clock signals and the second set of clock signals are not turned on at the same time. Therefore, the sub-pixels which are positioned in the same row and have the same color can have opposite polarities easily.

According to the embodiment of the invention, the polarity of each pixel column is inverted every preset time. Thus, fatigue due to long-term deflection of liquid crystal molecules to the same side can be prevented.

In yet another aspect of the present invention, a display panel is provided. The display panel comprises the driving circuit described above. Therefore, the display panel can enable the coupling of the sub-pixels (such as B pixels) in the same pixel row to VCOM to be mutually cancelled, and further improve the poor crosstalk.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 shows a schematic diagram of a driving circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a pixel structure according to an embodiment of the invention;

FIG. 3 shows a schematic partial structure diagram of a pixel structure according to an embodiment of the invention;

FIG. 4 shows a schematic diagram of a driving circuit according to an embodiment of the present invention;

FIG. 5 shows a block schematic diagram of a multiplexing circuit according to one embodiment of the invention;

FIG. 6 shows a schematic diagram of a part of a driving circuit and a pixel structure of comparative example 1 according to the present invention;

FIG. 7 shows a schematic diagram of a portion of a driver circuit and a pixel structure according to an embodiment of the invention;

FIG. 8 shows a voltage diagram of each line under a cross-talk picture of a blue picture according to the present invention;

FIG. 9 is a voltage diagram of the lines of a blue display according to one embodiment of the present invention;

FIG. 10 is a circuit diagram of a gate driving unit according to an embodiment of the invention;

FIG. 11 shows a circuit schematic of a plurality of cascaded gate drive units according to one embodiment of the present invention;

fig. 12 shows a timing diagram of a driving method according to an embodiment of the invention;

fig. 13 is a diagram showing a result of a lighting test of an example in the related art;

fig. 14 is a graph showing the result of a lighting test according to an example of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

Some embodiments of the present invention provide a driving circuit of a liquid crystal display panel. The driving circuit comprises a driving chip, a grid driving unit and a plurality of multiplexing units, and can enable a plurality of sub-pixels with the same color in the same pixel row to have different polarities during displaying, so that the coupling of a common electrode (VCOM) caused by the same polarity of the sub-pixels with the same color in the same row can be relieved and even solved, and the cross color problem caused by the change of the voltage difference between the common electrode and the pixel electrode can be relieved.

Specifically, referring to fig. 1 and 2, the pixel structure of the display panel includes a plurality of pixel units 100 (100A and 100B shown in the figure) arranged in an array, the pixel unit 100 includes 6 sub-pixels, the 6 sub-pixels are arranged in two pixel rows and three pixel columns, the first pixel column has two first sub-pixels 1, the second pixel column has two second sub-pixels 2, the third pixel column has one third sub-pixel 3 and one fourth sub-pixel 4, and the arrangement order of the third sub-pixel 3 and the fourth sub-pixel 4 of the third pixel column in two adjacent pixel units along the extending direction of the pixel rows is opposite. That is, in the extending direction of the pixel row, the sub-pixel of the third column in two adjacent pixel units in the pixel structure is not the third sub-pixel 3 at the same time, nor the fourth sub-pixel 4 at the same time. The sub-pixels in each pixel column are connected to the same data line 11 (11A-11F as shown in the figure). The driving circuit includes a first polarity data bus line and a second polarity data bus line (not shown), each multiplexing unit is connected to one data bus line and outputs source driving signals to a plurality of data lines, each data line is connected to one pixel column, a portion of the plurality of third sub-pixels in the same row is connected to the first polarity data bus line, another portion is connected to the second polarity data bus line, and a portion of the plurality of fourth sub-pixels in the same row is connected to the first polarity data bus line and another portion is connected to the second polarity data bus line. For convenience of understanding, the following first briefly explains the principle that the driving circuit can achieve the beneficial effect:

in an RGBW pixel, when the first sub-pixel is red and the second sub-pixel is green, half of the B pixels are replaced with the W pixels to increase the transmittance of the panel as described above. If a scheme that every other pixel column is connected to the same MUX (multiplexing unit), the output end of each MUX is connected to three data lines, and the polarities of the source driving signals of two adjacent MUXs are opposite (one is positive, and the other is negative), the sub-pixels in the same row and with the same color may have the same polarity. For example, a first multiplexing circuit may be used to supply positive source driving signals to the data lines 11A, 11C, and 11E, and a second multiplexing circuit may be used to supply negative source driving signals to the data lines 11B, 11D, and 11F. At this time, for the first sub-pixel 1, the polarities of the first sub-pixel 1 (connected to the data line 11A) in the pixel unit 100A and the first sub-pixel 1 (connected to the data line 11D) in the second pixel unit 100B are opposite. For the first pixel row, the third sub-pixel 3 (connected to the data line 11C) in the pixel unit 100A has a different color from the fourth sub-pixel 4 (the first pixel row of the pixel unit 100B) connected to the data line 11F, although the polarity is opposite. Therefore, when the pixel structure is arranged in an array, the sub-pixel in the third row of the first pixel column of the next pixel unit adjacent to the pixel unit 100B is still the electrically positive third sub-pixel. Referring to fig. 7, that is, the connection manner will result in the polarities of the third sub-pixels in the same pixel row being all the same, and the polarities of the fourth sub-pixels in the same pixel row being all the same. Therefore, when displaying the color of the third sub-pixel (B) or the fourth sub-pixel (W), the coupling effect of the pixel row data line to the common electrode (VCOM) cannot be cancelled.

According to the embodiment of the invention, the connection of the data lines is designed, so that the third sub-pixel and the fourth sub-pixel which are positioned in the same row can have two different polarities, and the coupling effect of the data lines on the common electrode can be eliminated in the direction of the pixel rows. This prevents color crosstalk caused by coupling to the common electrode when a picture of a certain color is displayed. It can be understood by those skilled in the art that the color of the sub-pixels is not particularly limited as long as the two colors of sub-pixels of adjacent pixel units are interchanged in a certain pixel column.

For example, according to an embodiment of the present invention, the first sub-pixel may be red, the second sub-pixel may be green, the third sub-pixel may be blue, and the fourth sub-pixel may be white. Therefore, the transmittance of the panel using the pixel structure can be improved by using the white fourth sub-pixel. Specifically, referring to fig. 3, the opening areas of 2 first sub-pixels in the same pixel unit are equal, and the opening areas of 2 second sub-pixels are equal. The opening areas of the first sub-pixel and the second sub-pixel may be the same, and the opening area of the third sub-pixel is 1.5-2.5 times, for example, 2 times, the opening area of the first sub-pixel. The ratio of the opening area of the fourth sub-pixel to the opening area of the first sub-pixel may be 0.3 to 0.6, and may be, for example, 0.5. Therefore, the transmission rate of the display panel using the pixel structure can be improved, and the PPI of the display panel is kept not to be reduced.

It should be noted that, in the embodiment of the present invention, unless otherwise specified, the "width" of a sub-pixel is the size of the sub-pixel along the pixel row direction, and the "length" is the size of the sub-pixel along the pixel column direction. Unless otherwise specified, the terms "equal," "same," "consistent," and the like are to be construed broadly, i.e., they may be defined as being equal in area, length, width, and the like, but not strictly equal, and may have tolerances within the scope permitted in the art.

Specifically, referring to fig. 3, appropriately increasing the area of the third sub-pixel (i.e., the blue sub-pixel) may alleviate the problem of picture yellowing due to the introduction of the white sub-pixel. Specifically, the widths of the third sub-pixel and the fourth sub-pixel may be the same, and the length of the third sub-pixel is 2 times the length of the fourth sub-pixel. In addition, in order to avoid the additional increase of the area of the pixel unit to decrease the PPI of the display panel, the width of the third sub-pixel may be greater than the width of the first sub-pixel, and the length of the third sub-pixel may be greater than the length of the first sub-pixel. That is, the first and second sub-pixels may be made slightly narrower, and the third and fourth sub-pixels may have the same width and be larger than the first sub-pixel, so as to increase the opening area of the third sub-pixel and maintain the total area of the pixel units in the pixel structure. Specifically, taking the pixel unit having 6 sub-pixels shown in table 1 below as an example, when the 6 sub-pixels are 2R, 2G and 2B sub-pixels arranged in three columns (i.e., the W sub-pixel is not used to replace the B sub-pixel), the sizes of the 6 sub-pixels may be 21 μm × 63 μm. The area of the B pixel in the RGBW pixel unit (the structure is as shown in fig. 3) according to the embodiment of the present invention is the largest, so that the yellow phenomenon caused by the introduction of the W pixel can be alleviated. But by adjusting the length and width of each sub-pixel, the sub-pixel average value of the pixel unit is consistent with the sub-pixel average value of the RGB pixel unit. Therefore, the pixel structure does not cause a reduction in PPI.

TABLE 1

Sub-pixel size	RGB	RGBW
			R pixel	21μm×63μm	18μm×63μm
G pixel	21μm×63μm	18μm×63μm
			B pixel	21μm×63μm	27μm×84μm
W pixel	Is free of	27μm×42μm
			Sub-pixel average	21μm×63μm	21μm×63μm

Referring to fig. 1, the driving circuit includes a driving chip 400, a gate driving unit 300, and a multiplexing unit 200. The driving chip is configured to provide a gate driving signal to the gate driving unit and a source driving signal to the multiplexing unit. The driving circuit can be provided with a plurality of data buses, and the first polarity data bus has a first polarity, such as an anode; the second polarity data bus has a second polarity, which may be negative, for example. Each multiplexing unit is connected to a data bus and outputs source driving signals to a plurality of data lines, each of which is connected to a pixel column. A part of the plurality of third sub-pixels in the same row is connected with the first polarity data bus, and the other part is connected with the second polarity data bus; a part of the plurality of fourth sub-pixels in the same row is connected to the first polarity data bus line, and the other part is connected to the second polarity data bus line. Similarly, the first sub-pixels in the same row have the first and second polarities, and the second sub-pixels in the same row have the first and second polarities. Therefore, the sub-pixels with the same color in each pixel row have opposite polarities, so that the coupling to the common electrode (VCOM) during display caused by the consistent polarities of the sub-pixels with the same color in the same row can be relieved and even solved, and the cross color problem caused by the change of the voltage difference between the common electrode and the pixel electrode can be relieved.

According to the embodiment of the present invention, referring to fig. 4, the type of the driving chip is not particularly limited, and for example, TED technology, i.e. a mode of integrating TCON and Driver into one IC for processing, may be adopted. The driving chip (IC) may be bound to a Flexible Printed Circuit (FPC) and integrated on the display panel by means including, but not limited to, COF. When the oxide thin film transistor is adopted, the on-state current (I) can be higher than that of a polycrystalline silicon-based thin film transistor_on) Therefore, the data line can be fully filled in a short time, and a higher data line multiplexing mode can be realized. Specifically, according to an embodiment of the present invention, referring to fig. 5, the multiplexing unit may include an input terminal 210 to receive a source driving signal, the input terminal 210 being connected to a data bus. The three control terminals (221, 222 and 223) and the three output terminals (231, 232 and 233) are in one-to-one correspondence, the control terminals receive control signals, each control terminal is used for controlling the output of one output terminal, and the three output terminals are respectively connected with different data lines. For example, the three control terminals may respectively correspond to the pixel columns in the pixel structure, for example, the control terminal 221 may correspond to a pixel column (MUXR) where a red sub-pixel is located, the control terminal 222 may correspond to a pixel column (MUXG) where a green sub-pixel is located, and the control terminal 223 may correspond to a pixel column (MUXB) where a blue sub-pixel and a white sub-pixel are located, so that one source driving signal may be used to perform source driving on 3 columns of sub-pixels, thereby reducing the size of the driving chip and the cost.

Specifically, referring to fig. 7, the driving circuit may have a plurality of multiplexing unit groups, each of which specifically includes a first multiplexing unit, a second multiplexing unit, a third multiplexing unit, and a fourth multiplexing unit. The first multiplexer receives the source driving signals from the first polarity data bus S1 at its input, the third multiplexer receives the source driving signals from the second polarity data bus S3 with a first polarity (illustrated as positive), the second multiplexer receives the source driving signals from the other first polarity data bus S2 at its input, and the fourth multiplexer receives the source driving signals from the other second polarity data bus S4 with a second polarity (illustrated as negative). The polarity of the source driving signal output by the output end of the multiplexing unit to the data line (11A, 11D, etc. as shown in the figure) is consistent with the polarity of the source driving signal received by the output end of the multiplexing unit. The driving circuit can utilize the first multiplexing unit, the second multiplexing unit, the third multiplexing unit and the fourth multiplexing unit to apply voltage to the data lines in a period of every 12 sub-pixel columns. The multiplexing units cooperate to apply voltages to the data lines in the display panel to achieve display. Thus, it is possible to achieve that the sub-pixels of the plurality of colors in each pixel row may have opposite polarities. Specifically, the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are sequentially arranged, and each pixel unit has 3 pixel columns, that is, one period constituting 12 sub-pixel columns. The first output end of the first multiplexing unit is connected with the first pixel column of the first pixel unit, the second output end of the first multiplexing unit is connected with the third pixel column of the first pixel unit, and the third output end of the first multiplexing unit is connected with the second pixel column of the second pixel unit; the first output end of the second multiplexing unit is connected with the second pixel column of the first pixel unit, the second output end of the second multiplexing unit is connected with the first pixel column of the second pixel unit, and the third output end of the second multiplexing unit is connected with the third pixel column of the second pixel unit; the first output end of the third multiplexing unit is connected with the first pixel column of the third pixel unit, the second output end of the third multiplexing unit is connected with the second pixel column of the fourth pixel unit, and the third output end of the third multiplexing unit is connected with the third pixel column of the fourth pixel unit; the first output end of the fourth multiplexing unit is connected with the second pixel column of the third pixel unit, the second output end of the fourth multiplexing unit is connected with the third pixel column of the third pixel unit, and the third output end of the fourth multiplexing unit is connected with the first pixel column of the fourth pixel unit. Therefore, the sub-pixels with different colors in the same pixel row have opposite polarities. Specifically, the data lines to which the output terminals of the first multiplexing unit and the second multiplexing voltage are connected may be spaced from each other, when the polarities of the first 6 sub-pixels in the first pixel row are positive and negative intervals. The second and third output ends of the third multiplexing unit are connected with the last two of the 12 sub-pixels, and the data lines connected with the first output end and the data lines connected with the second output end are separated by the data lines connected with the 3 output ends of the fourth multiplexing unit. Thus, the first of the last 6 subpixels of the 12 subpixels is of a first polarity (positive polarity), the middle three are of a second polarity (negative polarity), and the last two are of the first polarity (positive polarity). Since the arrangement order of the third sub-pixel (B) and the fourth sub-pixel (W) in the third sub-pixel column in the pixel structure is exchanged in the next pixel unit, the connection mode of the driving circuit can ensure that all the color sub-pixels in the same row have opposite polarities by taking 12 sub-pixels as a period.

According to the embodiments of the present invention, the specific type and number of the gate driving units are not particularly limited as long as the gate driving can be achieved. Specifically, the driving circuit includes a plurality of cascaded gate driving units. Referring to fig. 10 and 11, the plurality of gate driving units may have a plurality of input terminals, such as may include a gate input terminal, a clock input terminal, a reset input terminal, etc., for receiving a gate driving Signal (STV), a timing signal, etc. The circuit structure of the gate driving unit may be as shown in fig. 11, that is, the gate driving unit may include a plurality of thin film transistors, capacitors, and the like, and specifically may have a plurality of thin film transistors connected in parallel, so that the performance of the driving circuit may be further improved. For example, CN and CNB in the gate driving unit are signals for controlling positive and negative scanning, CN is high level, CNB is positive scanning when it is low level, and vice versa, thereby preventing the device lifetime from being shortened due to maintaining a certain electrical property for a long time. VGH _ G and VGL _ G provide signals of high and low levels in the gate driving. RESET is a RESET signal and is low level during normal display. EN _ Touch is a signal related to a Touch module (Touch), and at the time of Touch, EN _ Touch is at a high level and is at a low level when displayed.

The cascade connection of the plurality of Gate driving units may be as shown in fig. 11, and the four Gate driving units may include a first stage Gate driving unit, a second stage Gate driving unit, a third stage Gate driving unit and a fourth stage Gate driving unit, an output terminal of the third Gate driving unit (e.g., Gate _ N +2 shown in the figure) is connected to a reset input terminal of the first Gate driving unit (e.g., Gate _ N shown in the figure), and an output terminal of the first Gate driving unit is connected to a Gate input terminal of the third Gate driving unit. That is, the Output (OUT) of the first Gate driving unit may control the opening of Gate _ N (i.e., the nth row of Gate lines, as in the structure perpendicular to the data lines in fig. 7), while being connected to the input terminal (STV) controlling the Gate line Gate _ N +2 spaced therefrom by one row. The Output (OUT) of the Gate line Gate _ N +2 spaced apart from it by one row may be simultaneously connected to the reset input terminal (RST) of the Gate line Gate _ N spaced apart from it by one row. Thereby, progressive scanning of the gate lines is realized. The clock input terminals of the first stage Gate driving unit and the third stage Gate driving unit are connected to the first Gate clock signal and the third Gate clock signal (shown as CK1 and CK3), and the clock input terminals of the second stage Gate driving unit and the fourth stage Gate driving unit (shown as Gate _ N +3) are connected to the second Gate clock signal and the fourth Gate clock signal (shown as CK1 and CK 3). Therefore, the plurality of cascaded gate driving units can control the gate lines of each row to be opened sequentially at one time.

Further embodiments of the present invention provide a method of driving the foregoing driving circuit. The method comprises the following steps: the driving chip is used for providing a gate driving signal to the gate driving unit to scan the pixel rows line by line, providing a source driving signal to the multiplexing unit through the data bus and applying a voltage to the data line, so that the sub-pixels in the same column have the same polarity, and the sub-pixels in the same row and the same color can have opposite polarities. Therefore, the coupling of the common electrode (VCOM) in the display process caused by the consistent polarity of the same-color sub-pixels in the same row can be relieved and even solved, and the cross color problem caused by the change of the voltage difference between the common electrode and the pixel electrode can be relieved.

According to the embodiment of the present invention, a voltage is applied to the data line in a cycle at every adjacent 12 pixel columns. Referring to fig. 7 and 11, the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are sequentially arranged in a direction extending along the pixel row, the first pixel column, the third pixel column, and the second pixel column (the 5 th column from the left in the figure) of the first pixel unit are made to have a first polarity (e.g., positive) by the first multiplexing unit (the input terminal is connected to S1 shown in fig. 7), the second pixel column, the third pixel column, and the second pixel column (the 5 th column from the left in the figure) of the second pixel unit are made to have a second polarity (e.g., negative) by the second multiplexing unit (the input terminal is connected to S2 shown in fig. 8), the first pixel column, and the third pixel column of the second pixel unit are made to have a second polarity (e.g., negative), the first pixel column, the second pixel column, and the third pixel column of the fourth pixel unit are made to have a first polarity (e.g., positive) by the third multiplexing unit (the input terminal is connected to S3 shown in fig. 7), the fourth multiplexing unit (the input terminal is connected to S4 shown in fig. 7) is used to make the second pixel column of the third pixel unit, the third pixel column and the first pixel column of the fourth pixel unit have the second polarity (e.g., negative). Therefore, a plurality of sub-pixels which are positioned in the same row and have the same color can have opposite polarities.

According to the embodiment of the present invention, control signals are sequentially applied to the plurality of control terminals of the multiplexing unit to cause the plurality of output terminals of the multiplexing unit to be turned on in the order from the first pixel column, the second pixel column to the third pixel column. This can further improve the effect of display by the driving method. In addition, the driving chip may use a first set of clock signals for the source driving signals sent to the input terminals of the first multiplexing unit and the fourth multiplexing unit, and use a second set of clock signals for the source driving signals sent to the input terminals of the second multiplexing unit and the third multiplexing unit, where the first set of clock signals and the second set of clock signals are not turned on simultaneously. Therefore, the sub-pixels which are positioned in the same row and have the same color can have opposite polarities easily.

Specifically, referring to fig. 12, a timing signal (e.g., CK1-CK4) to the gate driving unit can make the gate driving unit control a plurality of gate lines to be sequentially opened, so as to implement progressive scanning. Fig. 12 is a timing chart showing the combination of the gate driver and the MUX, in which the control terminal of the multiplexing circuit is turned on in the order of the first pixel row (MUXB), the second pixel row (MUXG) to the third pixel row (MUXR), and different signals are required to be output for different frames, for example, for displaying a blue frame. The cascade of the gate driving units is as described above, and will not be described herein. Taking Gate _ N-2 (the structure of the Gate driving unit is similar to that of Gate _ N +2 shown in fig. 11) in fig. 12 as an example, when CK3 outputs a first pulse signal, the output terminal of Gate _ N-2 outputs the first pulse signal to the Gate line of Gate _ N-2. At the moment, when each row of grid lines is opened, the input ends of the MUXs are opened sequentially according to the sequence, and the MUXB outputs a third pulse signal. At this time, the first set of clock signals of S1 and S4 is turned on, the second set of clock signals of S2 and S3 is turned off, and S1 and S4 output the second pulse signal when the MUXB is turned on, applying a voltage to the data line of the positive polarity pixel column shown in fig. 7. Similarly, when the Gate _ N-1 outputs the first pulse signal, the first set of clock signals of S1 and S4 is turned off, the second set of clock signals of S2 and S3 is turned on, and the second set of clock signals of S2 and S3 outputs the second pulse signal when the MUXB is turned on, and voltage is applied to the data line of the pixel column of negative polarity shown in fig. 7, thereby realizing blue screen display.

According to the embodiment of the invention, the polarity of each pixel column can be inverted every predetermined time. Thus, fatigue due to long-term deflection of liquid crystal molecules to the same side can be prevented. The predetermined time may be a time when one frame picture is displayed, that is, when the first frame picture is displayed, S1 and S4 are made positive and S2 and S3 are made negative, and when the next frame picture is displayed, S1 and S4 are made negative and S2 and S3 are made positive. Therefore, the device life can be prolonged, and fatigue caused by long-time deflection of liquid crystal molecules in the same direction can be relieved.

Specifically, taking the example of displaying a blue screen in the center of the display panel using this method as an example, referring to fig. 9 and 7, the data lines 11C and 11F are located across the blue lighting area shown in fig. 14 (the area shown by the broken line frame in the figure), and the data line 11A is located in the white screen area on the left side of the blue lighting area. Referring to fig. 9, positive frame display is performed during a period t1-t3, and negative frame display is performed during a subsequent period. the time t1 is gray scale display, the positions of the three data lines are all gray scale pictures, the data lines are not inverted and always keep one level (2.5V), the time t2, 11C and 11F are blue picture display, at this time, the data lines are continuously turned over between high level (5V) and 0V, and the data lines 11A are still gray scale pictures and still keep 2.5V. 11C is opposite in polarity to 11F, so that there is no coupling capacitance between the common electrode VCOM and the data line at the time of inversion, and the Pixel electrode voltage (Pixel E) is not affected. Whereby the blue picture is free from crosstalk. When the connection relationship as shown in fig. 6 is adopted, since the data lines 11C and 11F are both positive, there is a coupling capacitance between the data line and VCOM, which is affected by the coupling capacitance. Referring to fig. 8, when the data line makes an upward transition, the VCOM is coupled upward, when the data line makes a downward transition, the VCOM is coupled downward, and the voltage makes an upward or downward transition, and then although the VCOM is slowly restored to the set value, the VCOM restoration time is longer than the data line inversion time, and the VCOM is not restored to the set value (0V), so that the voltage difference between the pixel electrode and the common electrode is changed, and the crosstalk phenomenon shown in fig. 13 occurs, in which the region shown by the dotted line frame is a blue lighting region.

Other embodiments of the present invention provide a display panel. The display panel includes a front driving circuit. Therefore, the display panel can enable the coupling of the sub-pixels (such as B pixels) in the same pixel row to VCOM to be mutually cancelled, and further improve the poor crosstalk.

In the description herein, references to the description of "one embodiment," "another embodiment," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.