阅读说明：本技术 显示面板 (Display panel ) 是由 白一晨 严允晟 于 2021-09-13 设计创作，主要内容包括：本申请公开了一种显示面板。显示面板包括：多个画素、第一主数据线和第一次数据线以及第一连接线。第一主数据线与排列在至少两列的画素电连接。第一次数据线与第一主数据线间隔M列画素,并且第一次数据线与排列在至少另两列的画素电连接。第一连接线连接第一主数据线与第一次数据线。本申请可实现同一行画素中正极性的画素与负极性的画素数量相等,进而改善显示面板的水平串扰问题。(The application discloses a display panel. The display panel includes: a plurality of pixels, a first main data line, a first sub data line and a first connection line. The first main data line is electrically connected with the pixels arranged in at least two rows. The first sub data line and the first main data line are separated by M columns of pixels, and the first sub data line is electrically connected with pixels arranged in at least another two columns. The first connecting line is connected with the first main data line and the first secondary data line. The display panel and the display method can achieve the purpose that the number of positive-polarity pixels and the number of negative-polarity pixels in the same row of pixels are equal, and further improve the horizontal crosstalk problem of the display panel.)

1. A display panel, comprising:

a plurality of pixels arranged in an array along a row direction and a column direction;

a first main data line extending in the column direction, wherein the first main data line is electrically connected to pixels arranged in at least two columns;

a first sub data line extending in the column direction, wherein the first sub data line is spaced from the first main data line by M columns of pixels, and the first sub data line is electrically connected to pixels arranged in at least another two columns; and

and the first connecting line is used for connecting the first main data line and the first secondary data line.

2. The display panel of claim 1, wherein the display panel further comprises:

a second main data line extending in the column direction and adjacent to the first main data line;

a second sub data line extending along the column direction and adjacent to the first sub data line, wherein the second sub data line is spaced from the second main data line by M columns of pixels, and the second main data line and the second sub data line are electrically connected to the pixels arranged in at least two columns, respectively; and

and a second connection line connecting the second main data line and the second sub data line, wherein the first main data line and the first sub data line are configured to transmit signals of a first polarity, and the second main data line and the second sub data line are configured to transmit signals of a second polarity opposite to the first polarity.

3. The display panel of claim 2, wherein the first main data lines alternately connect pixels arranged in a first column and pixels arranged in a second column, and the first sub data lines alternately connect pixels arranged in an nth column and pixels arranged in an N +1 th column; and

the second main data lines alternately connect the pixels arranged in the second column and the pixels arranged in the third column, and the second sub data lines alternately connect the pixels arranged in the (N + 1) th column and the pixels arranged in the (N +2) th column.

4. The display panel of claim 3, wherein the first main data line connects the pixels of the first row, the second column and the second row, the first column, and the second main data line connects the pixels of the first row, the third column and the second row, the second column and the second column.

5. The display panel according to claim 2, wherein the first main data line is electrically connected to pixels arranged in four columns, and the first sub data line is electrically connected to pixels arranged in another four columns;

in odd-numbered rows of pixels, the first main data line and the first sub data line are electrically connected with pixels of two columns of four columns of pixels corresponding to each other; and

in the even-numbered pixel rows, the first main data line and the first sub data line are electrically connected with the pixels of the other two columns of the four columns of pixels corresponding to the first main data line and the first sub data line respectively.

6. The display panel of claim 5, wherein in the odd-numbered rows of pixels, the first main data line is electrically connected to pixels of a second column and a third column of the corresponding four columns of pixels, and the first sub data line is electrically connected to pixels of a first column and a fourth column of the corresponding four columns of pixels; and

in the even-numbered pixels, the first main data line is electrically connected with the pixels of the first row and the fourth row of the corresponding four rows of pixels, and the first sub data line is electrically connected with the pixels of the second row and the third row of the corresponding four rows of pixels.

7. The display panel according to claim 6, wherein the second main data line is electrically connected to pixels arranged in four columns, and the second sub data line is electrically connected to pixels arranged in another four columns;

in odd-numbered rows of pixels, the second main data line and the second sub data line are electrically connected with pixels of two columns of four columns of pixels respectively corresponding to the second main data line and the second sub data line; and

in the even-numbered pixel rows, the second main data line and the second sub data line are electrically connected with the pixels of the other two columns of the four columns of pixels respectively corresponding to the second main data line and the second sub data line.

8. The display panel according to claim 7, wherein the first main data line is electrically connected to pixels arranged in an X-th column, an X + 1-th column, an X + 2-th column, and an X + 3-th column, and the second main data line is electrically connected to pixels arranged in an X + 2-th column, an X + 3-th column, an X + 4-th column, and an X + 5-th column;

in the odd-numbered rows of pixels, the first main data line is electrically connected to pixels arranged in the X +1 th column and the X +2 th column, and the second main data line is electrically connected to pixels arranged in the X +3 th column and the X +5 th column; and

in the pixels of the even-numbered rows, the first main data line is electrically connected to the pixels arranged in the X-th and X + 3-th columns, and the second main data line is electrically connected to the pixels arranged in the X + 2-th and X + 4-th columns.

9. The display panel of claim 1, wherein the display panel further comprises:

a source driver; and

and a wiring line connecting the source driver and the first main data line, wherein the first connection line is disposed between one end of the wiring line and the first row of pixels, and the end is a connection end of the wiring line and the first main data line.

10. The display panel of claim 1, further comprising a plurality of gate lines extending along the row direction, wherein two gate lines are disposed between two adjacent rows of pixels;

the gate lines comprise a first gate line and a second gate line which are respectively arranged at two sides of the first row of pixels, and the first gate line and the second gate line are respectively connected with at least one pixel in the first row of pixels; and

in the first row of pixels, the number of positive polarity pixels is equal to the number of negative polarity pixels.

Technical Field

The application relates to the technical field of display, in particular to a display panel.

Background

With the development of the panel industry, the resolution and refresh frequency of the panel are improved, but the number of Chip On Film (COF) packages disposed in the source driver is increased, and thus the risk of poor COF bonding is increased, and the cost is increased. Therefore, a Data Line Share (DLS) architecture is proposed. In the DLS architecture, the number of COFs is reduced to half of that of the conventional architecture, so that the risk of poor adhesion caused by arranging a plurality of COFs is reduced and the cost is reduced.

Fig. 1 shows a schematic diagram of a display panel 10 in the prior art. The display panel 10 includes a plurality of data lines D1-D7, a plurality of gate lines G1-G16, and a plurality of pixels P, wherein the plurality of pixels include a plurality of red pixels R, a plurality of green pixels G, and a plurality of blue pixels B. The display panel 10 adopts a DLS architecture, i.e., pixels in different columns are connected to the same data line. The polarities of signals transmitted by two adjacent data lines are opposite. As shown in fig. 1, when the display panel 10 displays an image in which two red lines and two white lines are alternately arranged, the first to third rows of pixels display the first white line, the fourth to sixth rows of pixels display the second white line, the seventh row of pixels display the first red line, the tenth row of pixels display the second red line, and the switches of the remaining rows of pixels are turned off to display black.

However, as shown in fig. 1, when the first gate line G1 is opened, the ratio of positive pixels to negative pixels is 3: 1. when the eleventh gate line G11 is turned on, the ratio of positive pixels to negative pixels is 1: 3. that is, the difference between the number of positive pixels and the number of negative pixels connected to the same gate line in the same row of pixels is large, so that the conventional DLS architecture has a serious horizontal crosstalk problem, and the image quality of the panel is reduced.

In view of the above, it is desirable to provide a display panel to solve the problems in the prior art.

Disclosure of Invention

To solve the above-mentioned problems of the prior art, an object of the present application is to provide a display panel to improve the horizontal crosstalk problem of the display panel and improve the picture quality of the display panel.

To achieve the above object, the present application provides a display panel, including: a plurality of pixels arranged in an array along a row direction and a column direction; a first main data line extending in the column direction, wherein the first main data line is electrically connected to pixels arranged in at least two columns; a first sub data line extending in the column direction, wherein the first sub data line is spaced from the first main data line by M columns of pixels, and the first sub data line is electrically connected to pixels arranged in at least another two columns; and a first connection line connecting the first main data line and the first sub data line.

In some embodiments, the display panel further comprises: a second main data line extending in the column direction and adjacent to the first main data line; a second sub data line extending along the column direction and adjacent to the first sub data line, wherein the second sub data line is spaced from the second main data line by M columns of pixels, and the second main data line and the second sub data line are electrically connected to the pixels arranged in at least two columns, respectively; and a second connection line connecting the second main data line and the second sub data line, wherein the first main data line and the first sub data line are configured to transmit signals of a first polarity, and the second main data line and the second sub data line are configured to transmit signals of a second polarity opposite to the first polarity.

In some embodiments, the first main data line alternately connects pixels arranged in a first column and pixels arranged in a second column, and the first sub data line alternately connects pixels arranged in an nth column and pixels arranged in an N +1 th column; and the second main data line alternately connects the pixels arranged in the second column and the pixels arranged in the third column, and the second sub data line alternately connects the pixels arranged in the (N + 1) th column and the pixels arranged in the (N +2) th column.

In some embodiments, the first main data line connects the pixels of the first row, the second column and the second row, the first column, and the second main data line connects the pixels of the first row, the third column and the second row, the second column and the second column.

In some embodiments, the first main data line is electrically connected to the pixels arranged in four columns, and the first sub data line is electrically connected to the pixels arranged in another four columns;

in odd-numbered rows of pixels, the first main data line and the first sub data line are electrically connected with pixels of two columns of four columns of pixels corresponding to each other; and in the even-numbered pixel rows, the first main data line and the first sub data line are electrically connected with the pixels of the other two columns of the four columns of pixels corresponding to the first main data line and the first sub data line respectively.

In some embodiments, in the odd-numbered rows of pixels, the first main data line is electrically connected to pixels of a second column and a third column of the corresponding four columns of pixels, and the first sub data line is electrically connected to pixels of a first column and a fourth column of the corresponding four columns of pixels; and in the even-numbered pixels, the first main data line is electrically connected with the pixels of the first row and the fourth row in the corresponding four rows of pixels, and the first secondary data line is electrically connected with the pixels of the second row and the third row in the corresponding four rows of pixels.

In some embodiments, the second main data line is electrically connected to the pixels arranged in four columns, and the second sub data line is electrically connected to the pixels arranged in another four columns; in odd-numbered rows of pixels, the second main data line and the second sub data line are electrically connected with pixels of two columns of four columns of pixels respectively corresponding to the second main data line and the second sub data line; and in the even-numbered pixel rows, the second main data line and the second secondary data line are electrically connected with the pixels of the other two columns of the four columns of pixels respectively corresponding to the second main data line and the second secondary data line.

In some embodiments, the first main data line is electrically connected to pixels arranged in an X-th column, an X + 1-th column, an X + 2-th column, and an X + 3-th column, and the second main data line is electrically connected to pixels arranged in an X + 2-th column, an X + 3-th column, an X + 4-th column, and an X + 5-th column; in the odd-numbered rows of pixels, the first main data line is electrically connected to pixels arranged in the X +1 th column and the X +2 th column, and the second main data line is electrically connected to pixels arranged in the X +3 th column and the X +5 th column; and in the even-numbered pixels, the first main data line is electrically connected to the pixels arranged in the X-th and X + 3-th columns, and the second main data line is electrically connected to the pixels arranged in the X + 2-th and X + 4-th columns.

In some embodiments, the display panel further comprises: a source driver; and a wiring line connecting the source driver and the first main data line, wherein the first connection line is disposed between one end of the wiring line and the first row of pixels, and the end is a connection end of the wiring line and the first main data line.

In some embodiments, the display panel further includes a plurality of gate lines extending along the row direction, and two gate lines are disposed between two adjacent rows of pixels; the gate lines comprise a first gate line and a second gate line which are respectively arranged at two sides of the first row of pixels, and the first gate line and the second gate line are respectively connected with at least one pixel in the first row of pixels; and in the first row of pixels, the number of positive pixels is equal to that of negative pixels.

Compared with the prior art, the secondary data lines connected with the main data lines are arranged in the display panel, so that the number of positive pixels and the number of negative pixels in the same row of pixels are close to each other while a small number of connectors used for connecting the source driver and the display panel are used, and the crosstalk problem of the display panel is improved and the picture quality of the display panel is improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a display panel in the prior art.

Fig. 2 is a schematic diagram of a pixel circuit of a display panel according to a first embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a pixel circuit of a display panel according to a second embodiment of the present application.

Fig. 4 shows a schematic diagram of a display device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 2, which shows a pixel circuit diagram of a display panel 200 according to an embodiment of the present disclosure, the display panel 200 includes a plurality of pixels, a plurality of data lines (including main data lines D1-1 to D8-1, sub data lines D1-2 to D8-2, and connecting lines C1-C8), and a plurality of gate lines G1-G6. The plurality of pixels are arranged in an array along a row direction and a column direction, and include red pixels R, green pixels G, and blue pixels B. The plurality of data lines extend in a column direction, and the plurality of gate lines extend in a row direction.

As shown in FIG. 2, each data line includes a main data line, a sub data line and a connecting line, for example, the first data line includes a first main data line D1-1, a first sub data line D1-2 and a first connecting line C1, and the second data line includes a second main data line D2-1, a second sub data line D2-2 and a second connecting line C2. The first main data line D1-1 and the first sub data line D1-2 are connected by a first connection line C1, and the second main data line D2-1 and the second sub data line D2-2 are connected by a second connection line C2. The first and second main data lines D1-1 and D2-1 are adjacent, and the first and second sub data lines D1-2 and D2-2 are adjacent. It should be noted that the first data line is not limited to the data line arranged in the first row in the display panel 200, and may be any one data line, that is, the first data line and the second data line should be understood as any two adjacent data lines in the display panel 200.

As shown in FIG. 2, M columns of pixels are spaced between the first main data line D1-1 and the first sub data line D1-2. The second main data line D2-1 and the second sub data line D2-2 are also separated by M columns of pixels, wherein M is a positive integer greater than or equal to 1. In the present embodiment, M is 4, i.e. the main data line and the sub data line are connected with each other by four columns of pixels. In some embodiments, M is preferably less than or equal to 2, which can effectively avoid the risk of electrostatic discharge (ESD) caused by too many cross-line designs in the connection lines connecting the main data lines and the sub data lines and reduce the charging speed of the pixel P.

In the present embodiment, in one group of the connected data lines, the main data line is electrically connected to the pixels arranged in at least two rows, and the sub data line is electrically connected to the pixels arranged in at least another two rows. It should be understood that the data line connected to the pixels arranged in a specific column is connected to at least one pixel of the column of pixels, not to all pixels of the column of pixels. As shown in fig. 2, the same main data line or sub data line is alternately connected to the pixels arranged in two rows. For example, the first main data line D1-1 is disposed between the first and second columns of pixels, and the first main data line D1-1 alternately connects the pixels arranged in the first column and the pixels arranged in the second column. The first sub data line D1-2 is disposed between the nth column of pixels and the (N + 1) th column of pixels, and the first sub data line D1-2 alternately connects the pixels arranged in the nth column and the pixels arranged in the (N + 1) th column, where N is a positive integer greater than or equal to 1. In this embodiment, N is 5. That is, the first sub data line D1-2 is disposed between the fifth column of pixels and the sixth column of pixels, and alternately connects the pixels arranged in the fifth column and the pixels arranged in the sixth column. The second main data line D2-1 is disposed between the second and third columns of pixels, and the second main data line D2-1 alternately connects the pixels arranged in the second column and the pixels arranged in the third column. The second sub data line D2-2 is disposed between the sixth and seventh columns of pixels, and the second sub data line D2-2 alternately connects the pixels arranged in the sixth column and the pixels arranged in the seventh column.

It should be understood that, in the present embodiment, the alternate connection of the data lines means that the data lines connect odd-numbered pixels or even-numbered pixels in the same column of pixels. That is, the data line is alternately connected to the odd-numbered pixels in one row of pixels and the even-numbered pixels in another adjacent row of pixels, or the data line is connected to the odd-numbered pixels in two adjacent rows of pixels, or the data line is connected to the even-numbered pixels in two adjacent rows of pixels. As shown in fig. 2, the first main data line D1-1 connects the pixels of the first row, the second column and the second row and the first column. Therefore, for the first main data line D1-1, the alternating connection of the data lines means that the first main data line D1-1 is connected to the even-numbered pixels in the first column of pixels and to the odd-numbered pixels in the second column of pixels. Similarly, the second main data line D2-1 connects the pixels of the first row, the third column and the second row and the second column. For the second main data line D2-1, the alternating connection of the data lines means that the second main data line D2-1 is connected to the even-numbered pixels in the second column of pixels and to the odd-numbered pixels in the third column of pixels.

As shown in fig. 2, the pixels in the same row are controlled by two adjacent gate lines, and two gate lines are disposed between two adjacent rows of pixels. For example, the first row of pixels is disposed between the first gate line G1 and the second gate line G2, and the second gate line G2 and the third gate line G3 are disposed between the first row of pixels and the second row of pixels. In the present embodiment, the pixels in the same row are correspondingly connected to two adjacent gate lines, for example, the first gate line G1 is correspondingly connected to at least one pixel in the first row of pixels, and the second gate line G2 is correspondingly connected to at least another pixel in the first row of pixels. Similarly, the third gate line G3 is correspondingly connected to at least one pixel in the second row of pixels, and the fourth gate line G4 is correspondingly connected to at least one pixel in the second row of pixels. It should be understood that the corresponding connection of the gate lines includes an ordered connection or a disordered connection, that is, the pixels in the same row may be connected with the two adjacent gate lines at intervals of the same or different numbers of pixels. As shown in fig. 2, four pixels in a row of pixels are connected to two adjacent gate lines alternately. For example, the first gate line G1 is connected to the first to fourth columns and the ninth to twelfth columns of the first row of pixels. The second gate line G2 is connected to the fifth to eighth columns and the thirteenth to sixteenth columns of the first row of pixels. In some embodiments, the same row of pixels may be connected to two adjacent gate lines at intervals of the same or different number of pixels.

In the present embodiment, a Data Line Share (DLS) architecture is implemented by alternately connecting pixels arranged in different columns by a same data line and correspondingly connecting pixels in a same row with two adjacent gate lines. Therefore, in the present embodiment, the number of connectors for connecting the source driver and the display panel can be reduced to half of that of the conventional architecture, thereby reducing the risk of poor adhesion caused by providing a plurality of connectors and reducing the cost.

It should be understood that, in the present embodiment, the display panel 200 contains liquid crystal. The liquid crystal unit corresponding to each pixel has a respective signal electrode. In order to prevent polarization of liquid crystal, it is necessary to drive the liquid crystal cell by alternately changing the polarity electric field. That is, the polarity of the voltage applied to each liquid crystal cell is inverted at two consecutive frames. For a liquid crystal cell, if the voltage polarity is driven to positive polarity in the current time frame, then the voltage polarity is driven to negative polarity in the next time frame.

As shown in fig. 2, the connected main data line and the sub data line are configured to transfer signals of the same polarity, and two adjacent data lines are configured to transfer signals of opposite polarities. For example, the first main data line D1-1 and the first sub data line D1-2 are configured to convey signals of a first polarity, the second main data line D2-1 and the second sub data line D2-2 are configured to convey signals of a second polarity opposite to the first polarity, and so on. As shown in FIG. 2, when the first main data line D1-1 and the first sub data line D1-2 are configured to transmit signals of negative polarity, the second main data line D2-1 and the second sub data line D2-2 are configured to transmit signals of positive polarity.

As shown in fig. 2, the pixels in the same row are of the same color. In addition, two adjacent pixels in the same row of pixels have opposite polarities. For example, when the first main data line D1-1 and the first sub data line D1-2 are configured to transmit signals of negative polarity, the pixels of the first row and the first column are positive polarity, the pixels of the second row and the first column are negative polarity, the pixels of the third row and the first column are positive polarity, and so on.

The cause of horizontal crosstalk in a particular picture is strongly related to the polarity of the pixels. In the displayed picture, the more the number of the positive pixels and the negative pixels in the same row of pixels is close to each other, the coupling capacitance with the common electrode can be eliminated, and further the horizontal crosstalk of the display panel is slight.

Therefore, as shown in fig. 2, the polarities of the pixels in the same row of pixels are arranged in a regular manner of "+ - - + - + - +" or "+ - + + - + - + - - -". When displaying a special picture, if two adjacent pixels in the same row of pixels have opposite column inversion voltage polarity patterns, the crosstalk of the whole perception can be reduced. For example, when the display panel 200 displays a special image in which two red lines and two white lines are alternately arranged, a special image in which one red line and two white lines are alternately arranged, or a special image in which one white line and one black line are alternately arranged, the number of pixels of positive polarity and the number of pixels of negative polarity connected to the same gate line in the same row of pixels are the same. When the display panel 200 displays a special picture containing a plurality of continuous W characters, the ratio of the positive polarity pixels to the negative polarity pixels connected to the same gate line in the same row of pixels is between 3/4 and 1. When the display panel 200 displays a special picture with two columns of white lines and two columns of black lines alternately arranged, the ratio of positive polarity pixels to negative polarity pixels connected to the same gate line in the same row of pixels is between 2/3 and 3/4. Therefore, when the display panel 200 displays the five special images, the risk of horizontal crosstalk is low, and the image quality of the display panel is further improved. In addition, in the same row of pixels, the polarity of the pixels is inverted every other one or two pixels, that is, (1+2) dot inversion (1+2dot inversion) driving in the row direction is realized.

It should be understood that, if the voltages applied to two adjacent pixels are the same but opposite in polarity, the coupling capacitance with the common electrode can be eliminated, thereby avoiding crosstalk. Specifically, a coupling capacitance is generated between the pixel and the data line, and the value of the coupling capacitance is inversely proportional to the distance between the pixel and the data line. That is, the larger the distance between the pixel and the data line, the smaller the capacitance value of the pixel and the data line. As shown in fig. 2, two opposite sides of each pixel are adjacent to the data line, and another pixel is not disposed between the data line and the side of the pixel. The two adjacent data lines are configured to transmit signals with opposite polarities, so that the polarities of the coupling capacitors at the two sides of each pixel are opposite, and the coupling capacitor between each pixel and one of the data lines is similar to the coupling capacitor between the other data line. Therefore, the method and the device can solve the problems of rough image quality and vertical crosstalk caused by the fact that the distance difference between the pixel and two adjacent data lines on two sides of the pixel is large and the coupling capacitors on two sides of the pixel are asymmetric.

Referring to fig. 3, which shows a pixel circuit diagram of a display panel 300 according to a second embodiment of the present application, the display panel 300 includes a plurality of pixels, a plurality of data lines (including main data lines D1-1 to D4-1, sub data lines D1-2 to D4-2, and connecting lines C1-C4), and a plurality of gate lines G1-G4. The plurality of pixels are arranged in an array along a row direction and a column direction, and include red pixels R, green pixels G, and blue pixels B. The plurality of data lines extend in a column direction, and the plurality of gate lines extend in a row direction.

As shown in FIG. 3, each data line includes a main data line, a sub data line and a connecting line, for example, the first data line includes a first main data line D1-1, a first sub data line D1-2 and a first connecting line C1, and the second data line includes a second main data line D2-1, a second sub data line D2-2 and a second connecting line C2. The first main data line D1-1 and the first sub data line D1-2 are connected by a first connection line C1, and the second main data line D2-1 and the second sub data line D2-2 are connected by a second connection line C2. The first and second main data lines D1-1 and D2-1 are adjacent, and the first and second sub data lines D1-2 and D2-2 are adjacent. It should be noted that the first data line is not limited to the data line arranged in the first row of the display panel 300, and may be any one data line, that is, the first data line and the second data line should be understood as any two adjacent data lines in the display panel 300.

As shown in FIG. 3, M columns of pixels are spaced between the first main data line D1-1 and the first sub data line D1-2. The second main data line D2-1 and the second sub data line D2-2 are also separated by M columns of pixels. In the present embodiment, M is 4, i.e. the main data line and the sub data line are connected with each other by four columns of pixels. In some embodiments, M is preferably less than or equal to 2, which can effectively avoid the risk of electrostatic discharge and reduce the charging speed of the pixel P due to the connection line connecting the main data line and the sub data line including too many cross-line designs.

As shown in fig. 3, in the present embodiment, in one group of connected data lines, the main data lines are electrically connected to the pixels arranged in four columns, and the sub data lines are electrically connected to the pixels arranged in another four columns. For example, the first main data line D1-1 is electrically connected to the pixels arranged in the first to fourth rows. The first sub data line D1-2 is electrically connected to pixels arranged in the nth to N +3 th columns. In this embodiment, N is 5. That is, the first sub data line D1-2 is electrically connected to the pixels arranged in the fifth to eighth columns.

As shown in fig. 3, in the odd-numbered pixels, the connected main data line and the sub data line are electrically connected to two of the four corresponding pixels. In the even-numbered pixel rows, the connected main data line and the secondary data line are electrically connected with the pixels of the other two columns of the four columns of pixels respectively corresponding to the main data line and the secondary data line. For example, in the odd-numbered rows of pixels, the first main data line D1-1 is electrically connected to the pixels of the second and third columns of the corresponding four columns of pixels, and the first sub data line D1-2 is electrically connected to the pixels of the first and fourth columns of the corresponding four columns of pixels. In the odd-numbered pixels, the second main data line D2-1 is electrically connected to the pixels of the second and fourth columns of the four corresponding columns of pixels, and the second sub data line D2-2 is electrically connected to the pixels of the first and third columns of the four corresponding columns of pixels. In the even-numbered rows of pixels, the first main data line D1-1 is electrically connected to the pixels of the first and fourth columns of the corresponding four columns of pixels, and the first sub data line D1-2 is electrically connected to the pixels of the second and third columns of the corresponding four columns of pixels. In the even-numbered pixels, the second main data line D2-1 is electrically connected to the pixels of the first and third columns of the corresponding four columns of pixels, and the second sub data line D2-2 is electrically connected to the pixels of the second and fourth columns of the corresponding four columns of pixels.

As shown in fig. 3, the same row of pixels is connected to different data lines. One of the main or secondary data lines is electrically connected with pixels arranged in the X +2 th column, the X +1 th column, the X +2 th column and the X +3 th column, and the other adjacent main or secondary data line is electrically connected with pixels arranged in the X +2 th column, the X +3 th column, the X +4 th column and the X +5 th column, wherein X is a positive integer greater than or equal to 1. For example, the first main data line D1-1 is electrically connected to the pixels arranged in the first to fourth columns, and the second main data line D2-1 is electrically connected to the pixels arranged in the third to sixth columns. The first sub data line D1-2 is electrically connected to the pixels arranged in the fifth to eighth columns, and the second sub data line D2-2 is electrically connected to the pixels arranged in the seventh to tenth columns. In the odd-numbered rows of pixels, the first main data line D1-1 is electrically connected to the pixels arranged in the second and third columns, the second main data line D2-1 is electrically connected to the pixels arranged in the fourth and sixth columns, the first sub data line D1-2 is electrically connected to the pixels arranged in the fifth and eighth columns, and the second sub data line D2-2 is electrically connected to the pixels arranged in the seventh and ninth columns. In the even-numbered pixels, the first main data line D1-1 is electrically connected to the pixels arranged in the first and fourth columns, the second main data line D2-1 is electrically connected to the pixels arranged in the third and fifth columns, the first sub data line D1-2 is electrically connected to the pixels arranged in the sixth and seventh columns, and the second sub data line D2-2 is electrically connected to the pixels arranged in the eighth and tenth columns.

As shown in fig. 3, the pixels in the same row are controlled by two adjacent gate lines, and two gate lines are disposed between two adjacent rows of pixels. For example, the first row of pixels is disposed between the first gate line G1 and the second gate line G2, and the second gate line G2 and the third gate line G3 are disposed between the first row of pixels and the second row of pixels. In the present embodiment, the pixels in the same row are correspondingly connected to two adjacent gate lines, for example, the first gate line G1 is correspondingly connected to at least one pixel in the first row of pixels, and the second gate line G2 is correspondingly connected to at least another pixel in the first row of pixels. Similarly, the third gate line G3 is correspondingly connected to at least one pixel in the second row of pixels, and the fourth gate line G4 is correspondingly connected to at least one pixel in the second row of pixels. It should be understood that the corresponding connection of the gate lines includes an ordered connection or a disordered connection, that is, the pixels in the same row may be connected with the two adjacent gate lines at intervals of the same or different numbers of pixels. In the embodiment, the data line sharing architecture is realized by the design that the same data line is connected with the pixels in different columns and the pixels in the same row are correspondingly connected with the two gate lines. Therefore, in the present embodiment, the number of connectors for connecting the source driver and the display panel can be reduced to half of that of the conventional architecture, thereby reducing the risk of poor adhesion caused by providing a plurality of connectors and reducing the cost.

It should be understood that, in the present embodiment, the display panel 300 contains liquid crystal. The liquid crystal unit corresponding to each pixel has a respective signal electrode. In order to prevent polarization of liquid crystal, it is necessary to drive the liquid crystal cell by alternately changing the polarity electric field. That is, the polarity of the voltage applied to each liquid crystal cell is inverted at two consecutive frames. For a liquid crystal cell, if the voltage polarity is driven to positive polarity in the current time frame, then the voltage polarity is driven to negative polarity in the next time frame.

As shown in fig. 3, the connected main data line and the sub data line are configured to transfer signals of the same polarity, and two adjacent data lines are configured to transfer signals of opposite polarities. For example, the first main data line D1-1 and the first sub data line D1-2 are configured to convey signals of a first polarity, the second main data line D2-1 and the second sub data line D2-2 are configured to convey signals of a second polarity opposite to the first polarity, and so on. As shown in FIG. 3, when the first main data line D1-1 and the first sub data line D1-2 are configured to transmit signals of positive polarity, the second main data line D2-1 and the second sub data line D2-2 are configured to transmit signals of negative polarity.

The cause of horizontal crosstalk in a particular picture is strongly related to the polarity of the pixels. In the displayed picture, the more the number of the positive pixels and the negative pixels in the same row of pixels is close to each other, the coupling capacitance with the common electrode can be eliminated, and further the horizontal crosstalk of the display panel is slight.

Therefore, as shown in fig. 3, the pixels in the same row are of the same color, and the polarities of two adjacent pixels in the same row are opposite. In the same row of pixels, the polarities of the pixels are arranged in a regular pattern of "+ - - - + - + -" or "+ - + - -". When displaying a special picture, if two adjacent pixels in the same row of pixels have opposite column inversion voltage polarity patterns, the crosstalk of the whole perception can be reduced. For example, when the display panel 300 displays a special screen in which one row of red lines and two rows of white lines are alternately arranged, a special screen in which one row of white lines and one row of black lines are alternately arranged, a special screen in which two rows of red lines and two rows of white lines are alternately arranged, or a special screen in which two rows of white lines and two rows of black lines are alternately arranged, the number of pixels of positive polarity and the number of pixels of negative polarity connected to the same gate line in the same row of pixels are the same. Moreover, when the display panel 300 displays a special picture containing a plurality of continuous W characters, the ratio of the two pixels with opposite polarities connecting to the same gate line in the same row of pixels is between 3/4 and 1. Accordingly, when the five special screens are displayed, the risk of horizontal crosstalk is low, and the picture quality of the display panel is improved. In addition, in one row of pixels, the polarity of the pixels is inverted every other one or two pixels, that is, (1+2) dot inversion (1+2dot inversion) driving in the row direction is realized.

Referring to fig. 4, a schematic diagram of a display device according to an embodiment of the present application is shown. The display device 20 includes a display panel 100, a controller 21, a gate driver 22, a source driver 23, and a plurality of connectors 24. The display panel 100 includes a fan-out area 101, a connection area 102, and a display area 103, wherein the connection area 102 is between the fan-out area 101 and the display area 103. It should be understood that the display panel 100 may be the display panel 200 of the first embodiment described above or the display panel 300 of the second embodiment described above. The display panel 200 of fig. 2 and the display panel 300 of fig. 3 show only a connection region and a display region corresponding to the display panel 100 of fig. 4.

As shown in fig. 4, the controller 21 is connected to the power supply to supply power to the display device 20, so as to control the display device 20 to be turned on or off. The controller 21 may include a timing controller, a microprocessor, a gamma voltage generator, and the like. The controller 21 is connected to the gate driver 22 and the source driver 23, and the gate driver 22 and the source driver 23 are connected to the display panel 100. The connector 24 is configured to couple (bonding) the source driver 23 to the display panel 100. The connection 24 may include, but is not limited to, a Chip On Film (COF). The display panel 100 includes a plurality of data lines DL extending along a column direction, a plurality of gate lines GL extending along a row direction, and a plurality of pixels P arranged in an array along the row direction and the column direction.

As shown in fig. 4, the source driver 23 is correspondingly connected to the pixels P via a plurality of data lines DL. The source driver 23 is correspondingly connected to the pixels P via a plurality of gate lines GL. The plurality of pixels P include different color pixels, such as red pixels, green pixels, blue pixels or white pixels, and are configured to emit red, green, blue or white light correspondingly. It should be noted that one or more rows of pixels P may be disposed between two adjacent data lines DL of the display panel 100.

As shown in fig. 4, the controller 21 is configured to generate a gate control signal and a data control signal. The gate driver 22 generates a gate signal according to the gate control signal and transmits the gate signal to the plurality of pixels P through the plurality of gate lines GL. On the other hand, the controller 21 transmits a data control signal (e.g., an analog video signal, a reference gamma voltage signal, etc.) to the source driver 23. The source driver 23 generates corresponding data signals according to the data control signals, and transmits the data signals to the pixels P through the data lines DL.

As shown in fig. 4, the fan-out area 101 is provided with a plurality of wirings W. The connection region 102 is provided with a plurality of data lines DL and a plurality of connection lines, such as a first connection line C1 and a second connection line C2. The display region 103 is provided with a plurality of pixels P, a plurality of data lines DL and a plurality of gate lines GL, wherein the plurality of data lines DL extend from the connection region 102 to the display region 103. The plurality of wires W in the fan-out area 101 are configured to connect the source driver 23 and the corresponding main data lines (e.g., the first main data line D1-1, the second main data line D2-1, etc.) of the plurality of data lines DL through the connectors 24. When the display device 20 is turned on, the controller 21 obtains an image data signal related to a frame of picture to generate a corresponding gate control signal and a corresponding data control signal, so as to control the display area 103 of the display panel 100 to display the picture.

As shown in fig. 4, in the present embodiment, a connection line connecting the main data line and the sub data line is provided at the connection region 102. Specifically, the connection line is disposed between the plurality of wirings W located in the fan-out area 101 and the first row of pixels P located in the display area 103. That is, the connection line is disposed between one end of the wiring W and the first row of pixels P, and the end is a connection end of the wiring W and the corresponding main data line. By disposing the connection lines at the connection regions 102 instead of the fan-out region 101, ESD risk caused by too dense circuit layout of the fan-out region 101 can be avoided and the charging speed of the pixels P can be reduced.

To sum up, this application is through setting up the time data line of being connected with main data line in display panel for the quantity that is used for connecting source driver and display panel's connecting piece can reduce for half of traditional framework, and then has reduced because the bad risk of laminating and reduce cost that set up a plurality of connecting pieces and arouse. Moreover, through the pixel circuit of the display panel, the number of positive pixels and the number of negative pixels in the same row of pixels can be similar, so that the horizontal crosstalk problem of the display panel is improved, and the picture quality of the display panel is improved.

A display panel provided by an embodiment of the present application is described in detail above. The principles and implementations of the present application are described herein using specific examples. The above description of the embodiments is only for assisting understanding of the technical solutions of the present application and the core ideas thereof. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.