阅读说明：本技术 FinFET的阈值电压调节方法 (Threshold voltage adjusting method of FinFET ) 是由 周真真 于 2021-08-31 设计创作，主要内容包括：本发明公开了一种FinFET的阈值电压调节方法,包括：步骤一、提供完成了第零层介电层的化学机械研磨工艺的半导体衬底；步骤二、形成光刻胶图形定义出阈值电压调节注入区域进行阈值电压调节注入,之后去除光刻胶图形,利用第一栅介质层埋在多晶硅伪栅底部的特性使第一栅介质层在去除光刻胶图形的过程中被保护；步骤三、进行金属栅置换工艺,在利用金属栅置换工艺中的热过程实现对阈值电压调节注入的杂质进行激活。本发明能避免阈值电压调节注入后对鳍体和输入输出FinFET的栅介质层产生损伤。(The invention discloses a threshold voltage adjusting method of a FinFET, which comprises the following steps: step one, providing a semiconductor substrate which is subjected to a chemical mechanical polishing process of a zero dielectric layer; forming a photoresist pattern to define a threshold voltage adjusting injection region for threshold voltage adjusting injection, removing the photoresist pattern, and protecting a first gate dielectric layer in the process of removing the photoresist pattern by utilizing the characteristic that the first gate dielectric layer is buried at the bottom of the polycrystalline silicon pseudo gate; and step three, performing a metal gate replacement process, and activating the impurities injected by adjusting the threshold voltage by utilizing a thermal process in the metal gate replacement process. The method can avoid damage to the fin body and the gate dielectric layer of the input-output FinFET after threshold voltage adjustment injection.)

1. A threshold voltage adjustment method of a FinFET is characterized by comprising the following steps:

step one, providing a semiconductor substrate which completes the chemical mechanical polishing process of the zero dielectric layer, a fin body, a shallow trench isolation dielectric layer, a first gate dielectric layer and a polysilicon pseudo gate are formed on the semiconductor substrate, the shallow trench isolation dielectric layer is located between the fin bodies and the top portions of the fin bodies are located on the top surfaces of the shallow trench isolation dielectric layer, a well region is formed in the top part of the fin body, the first gate dielectric layer covers the side surface and the top surface of the top part of the fin body, the polysilicon dummy gate is formed on the first gate dielectric layer in a covering manner, the well region covered by the polysilicon dummy gate is used as a channel region of FinFeT, the zero dielectric layer completely fills the region between the polycrystalline silicon dummy gates, and the top surface of the zero dielectric layer is level to the top surface of the polycrystalline silicon dummy gates;

forming a photoresist pattern by adopting a photoetching process to define a threshold voltage adjusting injection region and performing threshold voltage adjusting injection, wherein the threshold voltage adjusting injection penetrates through the polycrystalline silicon pseudo gate on the top of the top part of the fin body and the first gate dielectric layer and then enters the top part of the fin body, and the doping of the channel region is adjusted, so that the threshold voltage of the FinFET is adjusted; removing the photoresist pattern, and protecting the first gate dielectric layer in the process of removing the photoresist pattern by utilizing the characteristic that the first gate dielectric layer is buried at the bottom of the polycrystalline silicon pseudo gate;

and step three, performing a metal gate replacement process, and activating the impurities injected by adjusting the threshold voltage by utilizing a thermal process in the metal gate replacement process.

2. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: the semiconductor substrate includes a silicon substrate.

3. The method of threshold voltage adjustment of a FinFET of claim 2, wherein: the semiconductor substrate comprises a core region and an input-output region, wherein a core FinFET is formed in the core region, and an input-output FinFET is formed in the input-output region.

4. The method of threshold voltage adjustment of a FinFET of claim 3, wherein: and in the first step, the first gate dielectric layer is directly grown according to the thickness requirement of the gate dielectric layer of the input-output FinFET.

5. The method of threshold voltage adjustment of a FinFET of claim 4, wherein: the gate dielectric layer of the core FinFET includes a high dielectric constant layer.

6. The method of threshold voltage adjustment of a FinFET of claim 5, wherein: the metal gate replacement process of the third step comprises the following steps:

step 31, removing the polysilicon dummy gate in the core region and the input and output region;

step 32, removing the first gate dielectric layer in the core region;

step 33, forming a gate dielectric layer of the core FinFET in the core region;

step 34, forming metal gates of the core FinFET and the input-output FinFET.

7. The method of threshold voltage adjustment of a FinFET of claim 4, wherein: the first gate dielectric layer is made of an oxide layer.

8. The method of threshold voltage adjustment of a FinFET of claim 7, wherein: the first gate dielectric layer is formed by adopting an in-situ water vapor growth process.

9. The method of threshold voltage adjustment of a FinFET of claim 6, wherein: activating the threshold voltage adjustment implant impurity is accomplished using the thermal process of forming the high dielectric constant layer of the gate dielectric layer of the core FinFET in step 33.

10. The method of threshold voltage adjustment of a FinFET of claim 9, wherein: the material of the high dielectric constant layer includes hafnium oxide.

11. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: in the first step, the fin body is formed by performing patterned etching on the semiconductor substrate.

12. The method of threshold voltage adjustment of a FinFET of claim 11, wherein: the shallow trench isolation medium layer is formed by adopting a deposition and etch-back process, and can completely fill the interval area between the fin bodies after the deposition of the shallow trench isolation medium layer is finished; and after the back etching process of the shallow trench isolation medium layer is completed, the shallow trench isolation medium layer is only positioned in the bottom area of the interval area between the fin bodies and exposes the top parts of the fin bodies.

13. The method of threshold voltage adjustment of a FinFET of claim 12, wherein: and after the shallow trench isolation medium layer is deposited, the shallow trench isolation medium layer is formed by completely filling the spacing region between the fin bodies and performing an ion injection and push well process under the condition that the top surface of the shallow trench isolation medium layer is the same as the top surface of the fin body, and the back etching process of the shallow trench isolation medium layer is performed after the well region is formed.

14. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: in the first step, after the polycrystalline silicon dummy gate is formed, a step of forming an embedded epitaxial layer in the fin body on two sides of the polycrystalline silicon dummy gate and a step of performing source and drain injection to form a source region and a drain region are further included, and the source region and the drain region are located in the embedded epitaxial layer.

15. The method of threshold voltage adjustment of a FinFET of claim 14, wherein: and in the second step, the impurities injected by the threshold voltage adjustment are also injected into the embedded epitaxial layer, the type of the impurities injected by the threshold voltage adjustment is opposite to that of the impurities injected by the source and drain, and the injection dosage is increased in the source and drain injection so as to compensate the impurities injected by the threshold voltage adjustment.

Technical Field

The present invention relates to the Field of semiconductor integrated circuit manufacturing, and in particular, to a method for adjusting a threshold voltage of a Fin Field Effect Transistor (FinFET).

Background

The FinFET forming process comprises a step of threshold voltage adjusting injection, and the step is used for setting the doping concentration of the surface of a channel region and enabling the threshold voltage of the device to meet requirements.

As shown in fig. 1A, it is a process flow diagram of a threshold voltage adjusting method of a prior art first FinFET; FIG. 1B is a cross-sectional view of the device of FIG. 1A during a threshold voltage adjustment implant; the existing first method for adjusting the threshold voltage of a FinFET includes the following steps:

providing a semiconductor substrate 101a, forming fins 101 formed by performing patterned etching on the semiconductor substrate 101a, filling shallow trench isolation dielectric layers 102 in spaced areas between the fins 101, wherein the shallow trench isolation dielectric layers 102 are typically oxide layers, and forming lining oxide layers 102a on inner side surfaces of the spaced areas between the fins 101.

Performing Well implantation (Well implantation) corresponding to the mark S101;

performing threshold voltage adjustment injection (Vt infill) corresponding to the mark S201; the arrowed line corresponding to reference 103 in fig. 1B represents the threshold voltage adjustment implant.

Performing Well annealing (Well annealing) corresponding to the mark S102; the thermal process of the well anneal also activates the threshold voltage adjusting implanted dopants at the same time. This completes the step of threshold voltage adjustment.

The subsequent steps required to form the FinFET may then be performed, including:

a Fin real process corresponding to the mark S103 is performed, in which the shallow trench isolation dielectric layers 102 in the spaced areas on both sides of the Fin 101 are etched to make the top surfaces of the shallow trench isolation dielectric layers 102 lower than the top surfaces of the Fin 101, so that the top portions of the Fin 101 are exposed on the shallow trench isolation dielectric layers 102.

And then, forming a first gate dielectric layer corresponding to the mark S104. Typically, a Core (Core) region and an input/output (IO) region are included on the same semiconductor substrate 101a, the finfets in the input/output region are input/output finfets, and the finfets in the Core region are Core finfets. The gate dielectric layer of the input/output FinFET is thicker, so that the first gate dielectric layer is usually directly adopted as the gate dielectric layer of the subsequent input/output FinFET in the input/output region; while the first gate dielectric layer in the core region may be removed during the metal gate replacement process and may reform the gate dielectric layer required for the core FinFET, the gate dielectric layer of the core FinFET typically comprises a high dielectric constant (HK) material. The gate dielectric layer of the input/output FinFET is usually an oxide layer and formed by an in-situ water vapor growth process (ISSG), so the forming process of the first gate dielectric layer corresponding to the mark S104 is also denoted by ISSG OX in fig. 1A.

Then, a Poly circulation (Poly loop) process step corresponding to the mark S105 is performed. The polysilicon circulation process forms a pattern structure on the polysilicon dummy.

And then, forming a side wall, a source drain region and the like required by the FinFET by using the polycrystalline silicon pseudo gate.

As can be seen from fig. 1B, when the threshold voltage adjustment implant 103 is performed, the top of the Fin 101 has no protection structure, so the Fin 101 is most likely to be damaged (Fin Damage); in addition, most of the implantation impurities of the threshold voltage adjustment implantation 103 are implanted to the outside of the fin 101, so that dose loss (dose loss) occurs.

Fig. 2A is a process flow diagram of a threshold voltage adjustment method of a second FinFET in the prior art; FIG. 2B is a cross-sectional view of the device of FIG. 2A during a threshold voltage adjustment implant; the existing second method for adjusting the threshold voltage of a FinFET includes the following steps:

the difference between the existing second FinFET threshold voltage adjustment method and the existing first FinFET threshold voltage adjustment method is: in the existing second FinFET threshold voltage adjustment method, the threshold voltage adjustment implant corresponding to the mark S201 is placed between the steps corresponding to the marks S104 and S105.

The arrowed line corresponding to reference 103a in fig. 2B represents the threshold voltage adjustment implant. As can be seen from fig. 2B, the top portion of the fin 101 is exposed, and the threshold voltage adjustment implantation can be performed by angled implantation, which has good implantation sensitivity and facilitates threshold voltage adjustment, but may damage the first gate dielectric layer and the fin 101 at the same time. Generally, a photoresist pattern is formed before the threshold voltage adjustment implantation to define an implantation region, and then, after the photoresist pattern is removed, the first gate dielectric layer is mainly damaged in the process of removing the photoresist.

Disclosure of Invention

The invention aims to provide a threshold voltage adjusting method of a FinFET, which can avoid damage to a fin body and a gate dielectric layer of an input/output FinFET after threshold voltage adjustment injection.

In order to solve the above technical problem, the threshold voltage adjusting method of the FinFET provided in the present invention includes the following steps:

step one, providing a semiconductor substrate which completes the chemical mechanical polishing process of the zero dielectric layer, a fin body, a shallow trench isolation dielectric layer, a first gate dielectric layer and a polysilicon pseudo gate are formed on the semiconductor substrate, the shallow trench isolation dielectric layer is located between the fin bodies and the top portions of the fin bodies are located on the top surfaces of the shallow trench isolation dielectric layer, a well region is formed in the top part of the fin body, the first gate dielectric layer covers the side surface and the top surface of the top part of the fin body, the polysilicon dummy gate is formed on the first gate dielectric layer in a covering manner, the well region covered by the polysilicon dummy gate is used as a channel region of FinFeT, the zero dielectric layer completely fills the region between the polycrystalline silicon dummy gates, and the top surface of the zero dielectric layer is level with the top surface of the polycrystalline silicon dummy gates.

Forming a photoresist pattern by adopting a photoetching process to define a threshold voltage adjusting injection region and performing threshold voltage adjusting injection, wherein the threshold voltage adjusting injection penetrates through the polycrystalline silicon pseudo gate on the top of the top part of the fin body and the first gate dielectric layer and then enters the top part of the fin body, and the doping of the channel region is adjusted, so that the threshold voltage of the FinFET is adjusted; and removing the photoresist pattern, and protecting the first gate dielectric layer in the process of removing the photoresist pattern by utilizing the characteristic that the first gate dielectric layer is buried at the bottom of the polycrystalline silicon pseudo gate.

And step three, performing a metal gate replacement process, and activating the impurities injected by adjusting the threshold voltage by utilizing a thermal process in the metal gate replacement process.

In a further refinement, the semiconductor substrate comprises a silicon substrate.

In a further improvement, the semiconductor substrate comprises a core region and an input-output region, wherein a core FinFET is formed in the core region, and an input-output FinFET is formed in the input-output region.

In a further improvement, the first gate dielectric layer is directly used as the gate dielectric layer of the input-output FinFET, and in step one, the first gate dielectric layer is directly grown according to the thickness requirement of the gate dielectric layer of the input-output FinFET.

In a further improvement, the gate dielectric layer of the core FinFET includes a high dielectric constant layer.

The further improvement is that the metal gate replacement process of the third step comprises the following steps:

step 31, removing the polysilicon dummy gate in the core region and the input and output region;

step 32, removing the first gate dielectric layer in the core region;

step 33, forming a gate dielectric layer of the core FinFET in the core region;

step 34, forming metal gates of the core FinFET and the input-output FinFET.

In a further improvement, the first gate dielectric layer is made of an oxide layer.

The further improvement is that the first gate dielectric layer is formed by adopting an in-situ water vapor growth process.

In a further refinement, activating the threshold voltage adjustment implant impurity is accomplished using a thermal process that forms the high dielectric constant layer of the gate dielectric layer of the core FinFET in step 33.

In a further refinement, the material of the high dielectric constant layer comprises hafnium oxide.

In a further improvement, in the first step, the fin body is formed by performing patterned etching on the semiconductor substrate.

The further improvement is that the shallow trench isolation dielectric layer is formed by adopting a deposition and etch-back process, and the shallow trench isolation dielectric layer can completely fill the interval region between the fin bodies after the deposition of the shallow trench isolation dielectric layer is finished; and after the back etching process of the shallow trench isolation medium layer is completed, the shallow trench isolation medium layer is only positioned in the bottom area of the interval area between the fin bodies and exposes the top parts of the fin bodies.

The further improvement is that the well region is formed by performing an ion injection and push well process under the condition that the shallow trench isolation medium layer completely fills the spacing region between the fin bodies and the top surfaces of the shallow trench isolation medium layer and the fin bodies are the same after the shallow trench isolation medium layer is deposited, and performing a back etching process of the shallow trench isolation medium layer after the well region is formed.

In the first step, after the polysilicon dummy gate is formed, a step of forming an embedded epitaxial layer in the fin body on both sides of the polysilicon dummy gate and a step of performing source-drain injection to form a source region and a drain region are further included, and the source region and the drain region are located in the embedded epitaxial layer.

A further improvement is that the impurities injected in the step two for threshold voltage adjustment are also injected into the embedded epitaxial layer, the type of the impurities injected in the threshold voltage adjustment is opposite to that of the impurities injected in the source drain, and the injection dosage is increased in the source drain injection to compensate the impurities injected in the threshold voltage adjustment.

The invention makes special setting for the sequence of threshold voltage adjustment injection in the whole process flow, namely, after the chemical mechanical grinding process of the threshold voltage adjustment injection is completed on the zero dielectric layer, at the moment, the zero dielectric layer is level with the surface of the polysilicon pseudo gate, the zero dielectric layer and the polysilicon pseudo gate together protect the fin body and the first gate dielectric layer formed on the surface of the fin body, thus simultaneously preventing the damage to the fin body and the first FinFET gate dielectric layer in the process of removing photoresist after the threshold voltage adjustment injection, wherein the first gate dielectric layer is usually the gate dielectric layer used for input and output FinFET, therefore, the invention can avoid the damage to the fin body and the gate dielectric layer used for input and output by the threshold voltage adjustment injection.

In addition, after the threshold voltage adjusting injection is completed, a metal gate replacement process is carried out subsequently, and the impurity of the threshold voltage adjusting injection can be activated by directly utilizing the thermal process in the metal gate replacement process, so that the additional heat treatment process is not added, the process is simple, and the additional thermal process is not added.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1A is a process flow diagram of a prior art method of threshold voltage adjustment for a first FinFET;

FIG. 1B is a cross-sectional block diagram of the corresponding device of FIG. 1A during a threshold voltage adjustment implant;

FIG. 2A is a process flow diagram of a second prior art method of threshold voltage adjustment for a FinFET;

FIG. 2B is a cross-sectional block diagram of the corresponding device of FIG. 2A during a threshold voltage adjustment implant;

FIG. 3 is a flow chart of a threshold voltage adjustment method of a FinFET in accordance with an embodiment of the present invention;

FIG. 4 is a process flow diagram developed based on FIG. 3 in accordance with a specific process;

FIG. 5 is a three-dimensional structure diagram of a device corresponding to the threshold voltage adjustment implantation in the method according to the embodiment of the present invention;

FIG. 6A is a cross-sectional view of the device along line AA in FIG. 5;

fig. 6B is a cross-sectional structural view of the device along the line BB in fig. 5.

Detailed Description

FIG. 3 is a flow chart of a threshold voltage adjustment method for a FinFET according to an embodiment of the present invention; as shown in fig. 4, a process flow chart developed based on fig. 3 according to a specific process is provided; as shown in fig. 5, it is a three-dimensional structure diagram of a device corresponding to the threshold voltage adjustment implantation in the method according to the embodiment of the present invention; FIG. 6A is a cross-sectional view of the device taken along line AA in FIG. 5; as shown in fig. 6B, the cross-sectional structure of the device is along the BB line in fig. 5.

The threshold voltage adjusting method of the FinFET comprises the following steps:

step one, providing the semiconductor substrate 201a after the chemical mechanical polishing process of the zero dielectric layer 204 is completed, a fin body 201, a shallow trench isolation dielectric layer 202, a first gate dielectric layer 206 and a polysilicon dummy gate 203 are formed on the semiconductor substrate 201a, the shallow trench isolation dielectric layer 202 is located between the fins 201 and the top portion of the fins 201 is located on the top surface of the shallow trench isolation dielectric layer 202, a well region is formed in the top portion of the fin 201, the first gate dielectric layer 206 covers the side surfaces and the top surface of the top portion of the fin 201, the polysilicon dummy gate 203 is formed on the first gate dielectric layer 206 in a covering manner, the well region covered by the polysilicon dummy gate 203 is used as a channel region of FinFeT, the zero dielectric layer 204 completely fills the region between the polysilicon dummy gates 203 and the top surface of the zero dielectric layer 204 is even with the top surface of the polysilicon dummy gates 203.

In fig. 4, the process steps prior to the formation of the well region are omitted. The semiconductor substrate 201a before the well region is formed is similar to the semiconductor substrate 101a of fig. 1B. At this time, the fin body 201 is formed on the semiconductor substrate 201a, and the top surface of the shallow trench isolation dielectric layer 202 filled in the spaced area of the fin body 201 is flush with the top surface of the fin body 201.

The fin body 201 is formed by performing patterned etching on the semiconductor substrate 201 a.

After the shallow trench isolation dielectric layer 202 is deposited, the shallow trench isolation dielectric layer 202 completely fills the spacer between the fins 201.

After that, well implantation corresponding to the marker S301 is performed.

And performing well annealing corresponding to the mark S302, and finishing the formation process of the well region after the well annealing is finished. Generally, the well region is divided into an N-type well region and a P-type well region according to the difference between a P-type FinFET and an N-type FinFET, and the N-type well region is formed in a formation region of the P-type FinFET and the P-type well region is formed in a formation region of the N-type FinFET. The well injection of the N-type well region and the P-type well region is separately carried out, and the annealing process can be carried out simultaneously or separately.

Then, the fin 201 exposing process corresponding to the mark S303 is performed. In the fin body 201 exposure process, the shallow trench isolation dielectric layer 202 is etched back, and after the shallow trench isolation dielectric layer 202 is etched back, the shallow trench isolation dielectric layer 202 is only located in the bottom area of the spacer between the fin bodies 201 and exposes the top portions of the fin bodies 201.

And then, performing a forming process of the first gate dielectric layer 206 corresponding to the mark S304. In the method according to the embodiment of the present invention, the semiconductor substrate 201a includes a silicon substrate. The semiconductor substrate 201a includes a core region in which a core FinFET is formed and an input-output region in which an input-output FinFET is formed. The first gate dielectric layer 206 is directly used as a gate dielectric layer of the input/output FinFET, and in step one, the first gate dielectric layer 206 is directly grown according to the thickness requirement of the gate dielectric layer of the input/output FinFET.

Generally, the first gate dielectric layer 206 is an oxide layer, the formation process of the first gate dielectric layer 206 is generally ISSG, and the first gate dielectric layer 206 is also called ISSG OX.

The subsequent steps may include a polysilicon recycle process, which forms the polysilicon dummy gate 203.

After the polysilicon dummy gate 203 is formed, forming a side wall 207 on the side surface of the polysilicon dummy gate 203, forming an embedded epitaxial layer 205 in the fin body 201 on two sides of the polysilicon dummy gate 203, and performing source-drain injection to form a source region and a drain region, where the source region and the drain region are located in the embedded epitaxial layer 205.

A zero dielectric layer 205 is formed, the zero dielectric layer 205 is deposited to fill the region between the polysilicon dummy gates 203 and extend into the top region of the polysilicon dummy gates 203, and then the top surfaces of the zero dielectric layer 205 and the polysilicon dummy gates 203 are leveled by a chemical mechanical polishing process. In fig. 4, ILD CMP3 corresponding to reference S305 represents the CMP process of the zeroth dielectric layer 205.

Step two, forming a photoresist pattern by adopting a photoetching process to define a threshold voltage adjusting injection region, and if a Core region is defined as the threshold voltage adjusting injection region, performing threshold voltage adjusting injection, wherein the threshold voltage adjusting injection penetrates through the polycrystalline silicon pseudo gate 203 and the first gate dielectric layer 206 on the top of the top part of the fin body 201 and then enters the top part of the fin body 201 to adjust the doping of the channel region and further adjust the threshold voltage of the FinFET; and removing the photoresist pattern, and protecting the first gate dielectric layer 206 in the process of removing the photoresist pattern by utilizing the characteristic that the first gate dielectric layer 206 is buried at the bottom of the polysilicon dummy gate 203. Since the photoresist pattern is a photoresist pattern used to define a Core region, i.e., the Core region, is opened, and the IO region is covered by the photoresist, the first gate dielectric layer 206 according to the embodiment of the present invention is not in contact with the photoresist pattern, and thus the first gate dielectric layer 206 is not damaged during the process of removing the photoresist pattern, i.e., the remaining photoresist. For comparison, in the second conventional method corresponding to fig. 2B, when the threshold voltage adjustment injection of the Core region is performed, the IO region may be covered by the photoresist, so that the photoresist may directly contact the first gate dielectric layer of the IO region, and the first gate dielectric layer of the IO region may be easily damaged in the process of removing the photoresist after the threshold voltage adjustment injection is completed.

As shown in fig. 6A and 6B, the fin 201 and the first gate dielectric layer 206 are covered by the polysilicon dummy gate 203 and the zero dielectric layer 204, so that the fin 201 and the first gate dielectric layer 206 are protected from being damaged in the process of removing the photoresist pattern after the threshold voltage adjustment implantation is completed.

In general, the threshold voltage adjusting implant impurities are also implanted into the embedded epitaxial layer 205, and the type of the threshold voltage adjusting implant impurities is opposite to that of the source drain implant impurities, so that the implantation dose can be increased in the source drain implant in advance to compensate for the threshold voltage adjusting implant impurities.

And step three, performing a metal gate replacement process, and activating the impurities injected by adjusting the threshold voltage by utilizing a thermal process in the metal gate replacement process.

In the method of the embodiment of the present invention, the metal gate replacement process in the third step includes the following steps:

and 31, removing the polysilicon dummy gate 203 in the core region and the input and output region.

And step 32, removing the first gate dielectric layer 206 in the core region. Step 32 corresponds to Core OX remove as indicated by reference 307 in FIG. 4.

And step 33, forming a gate dielectric layer of the core FinFET in the core area. The gate dielectric layer of the core FinFET includes a high dielectric constant layer. Activating the threshold voltage adjustment implant impurity is accomplished using the thermal process of forming the high dielectric constant layer of the gate dielectric layer of the core FinFET in step 33.

The material of the high dielectric constant layer includes hafnium oxide. Step 33 corresponds to HK loop corresponding to reference 308 in fig. 4.

Step 34, forming metal gates of the core FinFET and the input-output FinFET.

The embodiment of the invention particularly sets the sequence of the threshold voltage adjusting injection in the whole process flow, namely, after the chemical mechanical polishing process of the threshold voltage adjusting injection is completed on the zero dielectric layer 204, the zero dielectric layer 204 is leveled with the surface of the polysilicon dummy gate 203, the zero dielectric layer 204 and the polysilicon dummy gate 203 together protect the fin body 201 and the first gate dielectric layer 206 formed on the surface of the fin body 201, so that the damage to the fin body 201 and the first gate dielectric layer 206 in the photoresist removing process after the threshold voltage adjusting injection can be simultaneously prevented, wherein the first gate dielectric layer 206 is usually a gate dielectric layer for acting as an input/output FinFET, therefore, the invention can prevent the damage to the fin body 201 and the gate dielectric layer of the input/output FinFET in the photoresist removing process after the threshold voltage adjusting injection.

In addition, after the threshold voltage adjusting injection is completed, a metal gate replacement process is performed subsequently, and the thermal process in the metal gate replacement process can be directly utilized to activate the impurities for threshold voltage adjusting injection, so that an additional thermal treatment process is not added, the process is simple, and the additional thermal process is not added.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.