阅读说明：本技术 一种半导体器件及其形成方法 (Semiconductor device and forming method thereof ) 是由 李勇 于 2021-08-31 设计创作，主要内容包括：本发明提供一种半导体器件及其形成方法,通过提供衬底结构,该衬底结构包括衬底、一个或多个有源鳍片、多个栅极结构、外延源漏极和覆盖外延源漏极的底部层间介质层,形成覆盖栅极结构顶部的盖帽层,形成覆盖盖帽层和底部层间介质层的层间介质层并平坦化,图案化层间介质层以形成接触开口,露出外延源漏极,在接触开口中形成接触插塞并平坦化,对间隔栅极结构外延源漏极上方的的接触插塞进行全部刻蚀、栅极结构上方的层间介电层进行部分刻蚀,对间隔外延源漏极栅极结构上方的盖帽层进行全部刻蚀、外延源漏极上方的的接触插塞进行部分刻蚀,在刻蚀形成的沟槽中沉积金属并平坦化,有效减小了有源鳍之间的间距,实现了标准单元面积进一步地微缩。(The invention provides a semiconductor device and a forming method thereof, wherein a substrate structure is provided, the substrate structure comprises a substrate, one or more active fins, a plurality of gate structures, an epitaxial source drain and a bottom interlayer dielectric layer covering the epitaxial source drain, a cap layer covering the top of the gate structure is formed, an interlayer dielectric layer covering the cap layer and the bottom interlayer dielectric layer is formed and flattened, the interlayer dielectric layer is patterned to form a contact opening, the epitaxial source drain is exposed, a contact plug is formed in the contact opening and flattened, the contact plug above the epitaxial source drain of the interval gate structure is completely etched, the interlayer dielectric layer above the gate structure is partially etched, the cap layer above the gate structure of the interval epitaxial source drain is completely etched, the contact plug above the epitaxial source drain is partially etched, metal is deposited in a groove formed by etching and is flattened, the space between the active fins is effectively reduced, and the area of the standard unit is further reduced.)

1. A method for forming a semiconductor device, comprising the steps of:

providing a substrate structure, wherein the substrate structure comprises a substrate, one or more active fins positioned on the substrate, a plurality of gate structures positioned on the active fins, epitaxial source and drain electrodes positioned in the active fins and positioned on two sides of the gate structures, and a bottom interlayer dielectric layer covering the epitaxial source and drain electrodes;

step two, forming a cap layer covering the top of the grid structure;

forming an interlayer dielectric layer covering the cap layer and the bottom interlayer dielectric layer and flattening;

patterning the interlayer dielectric layer to form a contact opening, and exposing the epitaxial source drain electrode;

step five, forming a contact plug in the contact opening and flattening;

step six, performing total etching on the contact plug above the epitaxial source drain of the interval grid structure and performing partial etching on the interlayer dielectric layer above the grid structure;

step seven, performing all etching on the cap layer above the interval epitaxial source drain electrode grid structure, and performing partial etching on the contact plug above the epitaxial source drain electrode;

and step eight, depositing metal in the grooves formed by etching in the step six and the step seven and flattening.

2. The method of claim 1, wherein the material of the cap layer in the second step is any one of silicon nitride, silicon oxynitride, silicon carbide nitride and silicon carbide.

3. The method of claim 1, wherein the contact hole is filled with a conductive material in step five to form the contact plug, wherein the conductive material is tungsten or cobalt.

4. The method of claim 1, further comprising forming a metal silicide at the contact opening after step four and before step five.

5. The method of claim 1, wherein step five further forms a conductive pattern in said contact opening to contact said contact plug, said conductive pattern being a power supply conductive line.

6. The method of claim 1, wherein the metal in step eight is tungsten or cobalt.

7. The method of claim 1, further comprising a ninth step of sequentially performing a sixth step and a seventh step along the length of the active fins to the end of the active fins.

8. A semiconductor device, characterized in that the semiconductor device comprises:

a substrate;

one or more active fins on the substrate;

a plurality of gate structures located over the active fins;

the epitaxial source and drain electrodes are positioned on at least one side of the gate structure in the active fins, and the interlayer dielectric layer covers the epitaxial source and drain electrodes;

a cap layer covering the top of the gate structure;

an interlayer dielectric layer covering the cap layer and the bottom interlayer dielectric layer;

a contact hole, a metal silicide layer, a wire pattern and a contact plug are formed above the epitaxial source drain electrode;

a first contact spanning the gate structure and located above the epitaxial source drain;

and the second contact piece stretches across the epitaxial source drain and is positioned above the grid structure.

9. The semiconductor device according to claim 8, wherein the first contact is formed by entirely etching a contact plug above the epitaxial source drain of the spacer gate structure and partially etching an interlayer dielectric layer above the gate structure; the second contact is formed by completely etching the cap layer above the interval epitaxial source/drain gate structure and partially etching the contact plug above the epitaxial source/drain.

10. The semiconductor device of claim 8, wherein the first and second contacts are arranged sequentially along a length of the active fin.

Technical Field

The invention relates to the field of semiconductor formation, in particular to a semiconductor device and a forming method thereof.

Background

The principal semiconductor devices of integrated circuits, particularly very large scale integrated circuits, are metal-oxide-semiconductor field effect transistors (MOS transistors). With the continuous development of integrated circuit manufacturing technology, the technology node of the semiconductor device is continuously reduced, and the geometric dimension of the semiconductor device is continuously reduced following moore's law. As semiconductor device dimensions are reduced to a certain extent, scaling down of feature sizes of semiconductor devices becomes increasingly difficult.

In the case of Fin-Field-Effect-transistors (finfets), further reduction of the cell height requires further scaling of the standard cell area as the track height moves towards smaller track heights, but in the FinFET architecture, a 2 dummy Fin (dummy Fin) spacing between the N-type and P-type fins within the standard cell is necessary to prevent bridging of the gate and diffusion contacts, which results in the spacing between the N-type and P-type fins not being able to become smaller.

Therefore, how to make the spacing between Active Fins (AF) smaller to achieve further miniaturization of standard cell area is a problem that needs to be solved.

Disclosure of Invention

In view of the above, the present invention provides a semiconductor device and a method for forming the same, which is used to reduce the spacing between active fins and achieve the purpose of further shrinking the standard cell area.

The invention provides a semiconductor device forming method, which comprises the following steps:

providing a substrate structure, wherein the substrate structure comprises a substrate, one or more active fins positioned on the substrate, a plurality of gate structures positioned on the active fins, epitaxial source and drain electrodes positioned in the active fins and positioned on two sides of the gate structures, and an interlayer dielectric layer covering the epitaxial source and drain electrodes;

step two, forming a cap layer covering the top of the grid structure;

forming an interlayer dielectric layer covering the cap layer and the bottom interlayer dielectric layer and flattening;

patterning the interlayer dielectric layer to form a contact opening, and exposing the epitaxial source drain electrode;

step five, forming a contact plug in the contact opening and flattening;

step six, performing total etching on the contact plug above the epitaxial source drain of the interval grid structure and performing partial etching on the interlayer dielectric layer above the grid structure;

step seven, performing all etching on the cap layer above the interval epitaxial source-drain gate structure and performing partial etching on the contact plug above the source-drain;

and step eight, depositing metal in the grooves formed by etching in the step six and the step seven and flattening.

Preferably, the material of the cap layer in the second step includes any one of silicon nitride, silicon oxynitride, silicon carbide nitride and silicon carbide.

Preferably, the contact hole is filled with a conductive material in step five to form the contact plug, the conductive material being tungsten or cobalt.

Preferably, after the fourth step, before the fifth step, a metal silicide is formed at the contact opening.

Preferably, in the fifth step, a conductive line pattern contacting the contact plug is further formed in the contact opening, and the conductive line pattern is a power supply conductive line.

Preferably, the metal in step eight is tungsten or cobalt.

Preferably, the method further comprises a ninth step of sequentially performing the sixth step and the seventh step along the length direction of the active fins until the end of the active fins.

The present invention also provides a semiconductor device including:

a substrate;

one or more active fins on the substrate;

a plurality of gate structures located over the active fins;

the epitaxial source and drain electrodes are positioned on at least one side of the gate structure in the active fins, and the interlayer dielectric layer covers the epitaxial source and drain electrodes;

a cap layer covering the top of the gate structure;

a contact hole, a metal silicide layer, a wire pattern and a contact plug are formed above the epitaxial source drain electrode;

a first contact spanning the gate structure and located above the epitaxial source drain;

and the second contact piece stretches across the epitaxial source drain and is positioned above the grid structure.

Preferably, the first contact is formed by completely etching the contact plug above the epitaxial source drain of the spacer gate structure and partially etching the interlayer dielectric layer above the gate structure; the second contact is formed by completely etching the cap layer above the interval epitaxial source/drain gate structure and partially etching the contact plug above the epitaxial source/drain.

Preferably, the first contact and the second contact are sequentially arranged along a length direction of the active fin.

According to the semiconductor device and the forming method, after the contact plug is formed above the epitaxial source drain, the contact plug above the epitaxial source drain of the interval grid structure is completely etched, the interlayer dielectric layer above the grid structure is partially etched, the cap layer above the grid structure of the interval epitaxial source drain is completely etched, and the contact plug above the epitaxial source drain is partially etched, so that the space between active fins is effectively reduced, and the purpose of further reducing the area of a standard unit is achieved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a FinFET-based rail cell;

FIG. 2 is a flow chart illustrating a method of forming a semiconductor device according to an embodiment of the present invention;

fig. 3-10 are schematic structural diagrams illustrating steps in a method for forming a semiconductor device according to an embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless the context clearly requires otherwise, throughout this specification, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Cell scaling is critical to the continued improvement of complementary metal-oxide-semiconductor (CMOS) technology. Although transistor scaling has provided a key driver by contact gate pitch (CPP) and metal layer (MX) pitch scaling, fundamental layout limitations begin to fundamentally limit cell scaling in highly scaled geometries. New layout concepts are also needed for standard cell designs to have higher device currents.

Fig. 1 shows a schematic diagram of a FinFET-based rail cell. As shown in fig. 1, the cell is terminated with power and ground up and down, and includes an n-type active fin 11, a p-type active fin 12, and 2 dummy fins (dummy fins) 13 present as spaces. The figure shows that it also includes a gate 14, a diffusion contact 15 and a gate contact 16.

Self-aligned gate contact (self-aligned gate contact) technology and COAG (contact over active gate) technology are commonly used in the prior art. Wherein self-aligning the gate contact it allows the gate contact to be placed directly on top of the active device. The gate access is more flexible, the whole contact area is reduced, the distance between two transistor gates can be effectively reduced, and the density of devices is increased. The COAG technology is an evolution version of the SAC (self-Aligned-Contact) technology, and a gate Contact is directly placed above an active area of a transistor, namely, a Contact hole at a source end and a drain end of a device is directly opened to the center of the device, so that the area of a part with an exposed head can be saved. Of course, the standard cell area can also be reduced by reducing the fin width and adopting a Single Diffusion Break (SDB) structure.

In view of the prior art, the present invention is based on the problem that in a FinFET architecture, a pitch of 2 dummy fins (dummy fins) must be provided between an N-type fin and a P-type fin in a standard cell to prevent bridging of a gate contact and a diffusion contact, which results in that the pitch between the N-type fin and the P-type fin cannot be made smaller. The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.

Fig. 2 is a flow chart illustrating a method of forming a semiconductor device according to an embodiment of the present invention. As shown in fig. 2, the method comprises the following steps:

step one, a substrate structure is provided.

As shown in fig. 3, the substrate structure includes a substrate, an active fin 1 located on the substrate, a gate structure 3 located on the active fin, an epitaxial source/drain 2 located in the active fin and located at two sides of the gate structure, and a bottom interlayer dielectric layer 4 covering the epitaxial source/drain.

In the embodiment of the invention, the substrate is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the fin is the same as that of the substrate. In the embodiment of the invention, the fin is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

Specifically, the process steps for forming the substrate and the fins include: providing an initial substrate; forming a graphical hard mask layer on the surface of the initial substrate; and etching the initial substrate by taking the hard mask layer as a mask, taking the etched initial substrate as a substrate, and taking the protrusion positioned on the surface of the substrate as a fin. In the embodiment of the present invention, the number of the gate structures 3 is 3 as an example.

And step two, forming a cap layer covering the top of the gate structure.

A cap 5 is formed atop the gate structure as shown in fig. 3. In the embodiment of the present invention, the material of the cap layer 5 is silicon nitride, silicon oxynitride, silicon carbide nitride, or silicon carbide, and is used for protecting the top of the gate structure.

And step three, forming an interlayer dielectric layer covering the cap layer and the bottom interlayer dielectric layer and flattening the interlayer dielectric layer.

As shown in fig. 4, an interlayer dielectric layer 6 is formed to cover the cap layer 5 and the bottom interlayer dielectric layer 4, and a chemical mechanical polishing process is used to perform planarization treatment. In the embodiment of the present invention, the material of the interlayer dielectric layer 6 includes silicon oxide, silicon oxynitride, or silicon oxycarbide. The process for forming the interlayer dielectric layer 6 is a deposition process, such as a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process or a sub-atmospheric sub-chemical vapor deposition process.

And fourthly, patterning the interlayer dielectric layer to form a contact opening, and exposing the epitaxial source and drain electrodes.

Specifically, the process steps of forming the contact opening include: forming a graphical photoresist layer on the top of the interlayer dielectric layer 6; and etching the interlayer dielectric layer 6 and the bottom interlayer dielectric layer 4 by taking the patterned photoresist layer as a mask until the surface of the epitaxial source drain electrode 2 is exposed.

And step five, forming a contact plug in the contact opening and flattening.

The contact hole plug 7 is used for realizing electrical connection in the semiconductor device and also used for realizing electrical connection between devices. In the embodiment of the present invention, the contact hole plug 7 is made of tungsten. The contact hole plug 7 may be formed using a chemical vapor deposition process, a sputtering process, or an electroplating process. In other embodiments, the material of the contact hole plug may also be a metal material such as Al, Cu, Ag, or Au.

Specifically, the step of forming the contact hole plug 7 includes: forming contact openings in the interlayer dielectric layer 6 and the bottom interlayer dielectric layer 4, wherein the contact openings expose the epitaxial source and drain electrodes 2; and forming a contact plug 7 for filling the contact opening, wherein the contact plug 7 is in contact with the epitaxial source drain electrode 2.

And sixthly, performing full etching on the contact plug above the source and drain of the interval grid structure, and performing partial etching on the interlayer dielectric layer above the grid structure.

And seventhly, performing full etching on the cap layer above the interval source-drain gate structure, and performing partial etching on the contact plug above the source-drain.

And step eight, depositing metal in the grooves formed by etching in the step six and the step seven and flattening.

In the embodiment of the invention, a self-aligned contact (SAC) etching process is adopted to carry out full etching on a contact plug above a source/drain electrode of a spaced gate structure and partial etching on an interlayer dielectric layer above the gate structure to form a groove, metal is deposited in the groove to form a first contact element 8, and the first contact element 8 crosses the gate structure to be formed above an epitaxial source/drain electrode; and completely etching the cap layer above the interval epitaxial source/drain gate structure, partially etching the contact plug above the source/drain to form a groove, depositing metal in the groove to form a second contact element 9, wherein the second contact element 9 crosses the epitaxial source/drain 2 to be formed above the gate structure.

In the embodiment of the invention, the filling metal is tungsten or cobalt, and has good filling capacity.

In addition, in the embodiment of the present invention, after the fourth step, before the fifth step, a metal silicide is formed at the contact opening.

Specifically, a metal is deposited and then annealed to form a metal silicide. The forming of the metal silicide includes forming a conformal metal layer in the contact opening, wherein the conformal metal layer is deposited on a surface of the source drain. Deposition can be achieved using a conformal deposition method (e.g., ALD). The metal layer may comprise titanium, nickel, cobalt, etc. According to some embodiments, the metal silicide may be formed using hot dipping, spike annealing, rapid annealing, laser annealing, or the like.

And step five, forming a conducting wire pattern contacting the contact plug in the contact opening, wherein the conducting wire pattern is a power supply conducting wire.

The embodiment of the invention also comprises a ninth step, wherein the sixth step and the seventh step are sequentially executed along the length direction of the active fins until the tail of the active fins.

That is, etching is performed continuously along the length direction of the active fin until the end etching of the active fin is completed.

According to the semiconductor device forming method, the double self-aligned contact process is adopted, after the contact plug is formed above the epitaxial source drain, the contact plug above the epitaxial source drain of the interval grid structure is completely etched, the interlayer dielectric layer above the grid structure is partially etched, the cap layer above the grid structure of the interval epitaxial source drain is completely etched, and the contact plug above the epitaxial source drain is partially etched, so that the space between active fins is effectively reduced, and the purpose of further reducing the area of a standard unit is achieved.

Fig. 10 is a schematic structural view of a semiconductor device according to an embodiment of the present invention. As shown in fig. 10, the semiconductor device includes a substrate, an active fin 1 on the substrate, a plurality of gate structures 3 on the active fin, an epitaxial source/drain 2 on at least one side of the gate structure in the active fin, a bottom interlayer dielectric layer 4 covering the epitaxial source/drain, a cap layer 5 covering the top of the gate structure, an interlayer dielectric layer 6 covering the cap layer 5 and the bottom interlayer dielectric layer 4, a contact plug 7 formed above the epitaxial source/drain, a first contact 8 crossing the gate structure and located above the epitaxial source/drain, and a second contact 9 crossing the epitaxial source/drain and located above the gate structure.

In the embodiment of the present invention, the first contact 8 is formed by performing full etching on the contact plug above the epitaxial source/drain of the spacer gate structure and performing partial etching on the interlayer dielectric layer above the gate structure. The second contact 9 is formed by performing full etching on the cap layer above the spaced epitaxial source/drain gate structure and performing partial etching on the contact plug above the epitaxial source/drain. The first contact member 8 and the second contact member 9 are arranged in sequence along the length direction of the fin.

Of course, in the embodiment of the present invention, 3 gate structures are taken as an example, a first contact 8 and a second contact 9 are formed along the length direction of the active fin, and in other embodiments with more than 3 gate structures, a plurality of spaced first contacts 8 and second contacts 9 are formed in sequence until the end of the active fin.

According to the semiconductor device, after the contact plug is formed above the epitaxial source drain electrode, the self-aligned contact etching process is adopted to form the first contact element 8 crossing the gate structure and located above the epitaxial source drain electrode and the second contact element 9 crossing the epitaxial source drain electrode and located above the gate structure, so that the space between active fins is effectively reduced, and the purpose of further shrinking the standard unit area is achieved.

It should be understood that many other layers may be present, such as spacers, sidewalls, spacer elements and/or other suitable components, which are omitted from the illustration for simplicity.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.