阅读说明：本技术 一种降低米勒电容的mosfet制造方法 (MOSFET manufacturing method for reducing Miller capacitance ) 是由 潘光燃 胡瞳腾 于 2021-09-30 设计创作，主要内容包括：本发明公开了一种降低米勒电容的MOSFET制造方法,采用本方法制造的MOSFET,第二多晶硅(多晶硅栅)下方与外延层(漏端)之间的介质层包括第一氧化层、氮化硅和第二氧化层,而传统方法中多晶硅栅下方与漏端之间的介质层为单一的栅氧化层,显而易见,本方法制造的MOSFET的介质层厚度大于现有技术中的栅氧化层,介质层厚度越大对应的电容值越小,因此本发明的MOSFET的多晶硅栅底部与漏端之间的寄生电容比传统方法较小,降低了作为开关电路时的开关损耗,可适用于高频领域,具有更广的适用范围。(The invention discloses a MOSFET manufacturing method for reducing Miller capacitance, wherein a dielectric layer between the lower part of a second polysilicon (polysilicon gate) and an epitaxial layer (drain end) comprises a first oxide layer, silicon nitride and a second oxide layer, and the dielectric layer between the lower part of the polysilicon gate and the drain end is a single gate oxide layer in the traditional method.)

1. A MOSFET manufacturing method for reducing Miller capacitance is characterized by comprising the following steps:

step S1: growing an epitaxial layer on the surface of the substrate, forming a groove in the epitaxial layer, and forming a first oxidation layer on the surface of the groove;

step S2: generating silicon nitride on the surface of the first oxide layer, depositing first polysilicon on the silicon nitride, etching the first polysilicon in the groove, and reserving part of the first polysilicon at the bottom of the groove;

step S3: oxidizing the first polysilicon to generate a second oxide layer;

step S4: etching the silicon nitride to make the height of the silicon nitride be flush with that of the second oxide layer;

step S5: etching the first oxide layer to make the first oxide layer and the silicon nitride have the same height;

step S6: growing a third oxide layer on the side wall of the trench, wherein the third oxide layer extends to one end of the first oxide layer;

step S7: a second polysilicon is deposited within the trench and etched such that the height of the second polysilicon is less than the height of the trench.

2. The method of claim 1 wherein said step of forming a MOSFET further comprises the steps of: the depth of the groove is 1.0-3.0 microns.

3. The method of claim 1 wherein said step of forming a MOSFET further comprises the steps of: the first polysilicon is N-type doped polysilicon or P-type doped polysilicon or undoped polysilicon.

4. The method of claim 1 wherein said step of forming a MOSFET further comprises the steps of: in step S2, the thickness of the portion of the first polysilicon remaining at the bottom of the trench is 0.2-0.5 μm.

5. The method of claim 1 wherein said step of forming a MOSFET further comprises the steps of: the thickness of the first oxide layer is 30-300 nanometers, and the thickness of the silicon nitride is 30-200 nanometers.

6. The method of claim 1 wherein said step of forming a MOSFET further comprises the steps of: in the step S3, the first polysilicon is completely oxidized to form a second oxide layer by an oxidation process at 800-;

the second oxide layer 7 has a longitudinal thickness of 0.4-1.0 μm.

7. The method as claimed in claim 1, wherein the step S4 includes:

step S41: corroding the silicon nitride on the top of the second oxide layer by adopting an over-corrosion process method to enable the silicon nitride to be flush with the second oxide layer in height;

step S42: based on isotropy of the etching process, the silicon nitride forms first concave regions on two sides of the second oxide layer;

the step S5 specifically includes:

step S51: corroding the first oxide layer on the top of the silicon nitride by adopting an over-corrosion process method to enable the first oxide layer to be flush with the silicon nitride in height;

step S52: based on isotropy of the etching process, the first oxide layer forms second recessed regions on two sides of the silicon nitride.

8. The method of claim 1 wherein said step of forming a MOSFET further comprises the steps of: in step S6, an oxidation process at 800-;

the thickness of the third oxide layer is 15-80 nanometers.

9. The method of claim 1 wherein said step of forming a MOSFET further comprises the steps of: the type of the MOSFET is the same as the doping type of the second polysilicon.

10. The method of claim 1, wherein step S7 is further followed by the steps of:

step S8: sequentially forming a body region and a source region in the epitaxial layer;

the tail end of the body region close to the bottom of the groove is higher than the tail end of the second polysilicon close to the bottom of the groove, and the difference between the tail ends of the body region and the second polysilicon at the bottom of the corresponding groove is 0.1-0.3 micrometer.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an MOSFET (metal-oxide-semiconductor field effect transistor) for reducing Miller capacitance.

Background

The MOSFET chip is a discrete device, belongs to the field of semiconductor power devices, and belongs to the field of semiconductor chips with integrated circuits, wherein the integrated circuits integrate thousands of transistors in one chip through a process method, and the MOSFET is a single transistor formed by paralleling thousands of cells with the same structure.

The key dynamic parameters of the MOSFET include parasitic capacitance, switching time, gate parasitic resistance, etc., where the parasitic capacitance includes gate-source parasitic capacitance Cgs, gate-drain parasitic capacitance Cgd, and drain-source parasitic capacitance Cds, and from an application point of view, the parasitic capacitance of the MOSFET is summarized as input capacitance Ciss + Cgd, output capacitance Coss + Cdg, and reverse transfer capacitance Crss + Cdg, where the reverse transfer capacitance Crss is also called miller capacitance. The miller capacitance plays a dominant role in the switching losses of the MOSFET, reducing the miller capacitance as much as possible, and is the responsibility of the chip engineer.

In the trench MOSFET in the prior art, a dielectric layer between a gate and a drain is a gate oxide layer covering the bottom of a trench and the side wall of the trench, and the gate oxide layer is thin and has a large area, so that the parasitic capacitance Cgd of the gate and the drain of the MOSFET, namely the miller capacitance Crss, is large.

Disclosure of Invention

The invention provides a manufacturing method of an MOSFET (metal-oxide-semiconductor field effect transistor) for reducing Miller capacitance, and aims to solve the problem of large switching loss caused by a thin dielectric layer and a large area between a grid and a drain in the conventional trench MOSFET.

According to an embodiment of the present application, there is provided a method for manufacturing a MOSFET with reduced miller capacitance, including the steps of:

step S1: growing an epitaxial layer on the surface of the substrate, forming a groove in the epitaxial layer, and forming a first oxidation layer on the surface of the groove;

step S2: generating silicon nitride on the surface of the first oxide layer, depositing first polysilicon on the silicon nitride, etching the first polysilicon in the groove, and reserving part of the first polysilicon at the bottom of the groove;

step S3: oxidizing the first polysilicon to generate a second oxide layer;

step S4: etching the silicon nitride to make the height of the silicon nitride be flush with that of the second oxide layer;

step S5: etching the first oxide layer to make the first oxide layer and the silicon nitride have the same height;

step S6: growing a third oxide layer on the side wall of the trench, wherein the third oxide layer extends to one end of the first oxide layer;

step S7: a second polysilicon is deposited within the trench and etched such that the height of the second polysilicon is less than the height of the trench.

Preferably, the depth of the trench is 1.0-3.0 microns.

Preferably, the first polysilicon is N-type doped polysilicon or P-type doped polysilicon or undoped polysilicon.

Preferably, in step S2, the thickness of the portion of the first polysilicon remaining at the bottom of the trench is 0.2-0.5 μm.

Preferably, the thickness of the first oxide layer is 30-300 nm, and the thickness of the silicon nitride is 30-200 nm.

Preferably, in the step S3, the first polysilicon is completely oxidized by an oxidation process at 800-;

the second oxide layer 7 has a longitudinal thickness of 0.4-1.0 μm.

Preferably, the step S4 specifically includes:

step S41: corroding the silicon nitride on the top of the second oxide layer by adopting an over-corrosion process method to enable the silicon nitride to be flush with the second oxide layer in height;

step S42: based on isotropy of the etching process, the silicon nitride forms first concave regions on two sides of the second oxide layer;

the step S5 specifically includes:

step S51: corroding the first oxide layer on the top of the silicon nitride by adopting an over-corrosion process method to enable the first oxide layer to be flush with the silicon nitride in height;

step S52: based on isotropy of the etching process, the first oxide layer forms second recessed regions on two sides of the silicon nitride.

Preferably, in step S6, an oxidation process at 800-;

the thickness of the third oxide layer is 15-80 nanometers.

Preferably, the type of MOSFET is the same as the doping type of the second polysilicon.

Preferably, the step S7 further includes:

step S8: sequentially forming a body region and a source region in the epitaxial layer;

the tail end of the body region close to the bottom of the groove is higher than the tail end of the second polysilicon close to the bottom of the groove, and the difference between the tail ends of the body region and the second polysilicon at the bottom of the corresponding groove is 0.1-0.3 micrometer.

Compared with the prior art, the manufacturing method of the MOSFET for reducing the Miller capacitance has the following beneficial effects:

1. in the MOSFET manufactured by the method, the dielectric layer between the lower part of the second polysilicon (polysilicon gate) and the epitaxial layer (drain end) comprises the first oxide layer, the silicon nitride and the second oxide layer, while the dielectric layer between the lower part of the polysilicon gate and the drain end is a single gate oxide layer in the traditional method.

2. In the MOSFET manufactured by the method, the dielectric layer between the side surface of the second polysilicon (polysilicon gate) and the epitaxial layer (drain terminal) is the third oxide layer (gate oxide layer), but the longitudinal width of the third oxide layer is only 0.1-0.3 micrometer, while the width of the gate oxide layer is usually 0.3-0.9 micrometer in the traditional method, and as is known, the smaller the area (the smaller the width means the smaller the parasitic capacitance area) is, the smaller the corresponding capacitance value is, so the parasitic capacitance between the side surface of the polysilicon gate and the drain terminal of the MOSFET is much smaller than that of the traditional method.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of a method for manufacturing a MOSFET with reduced miller capacitance according to a first embodiment of the present invention.

Fig. 2 is a flowchart of step S4 in the method for manufacturing a MOSFET with reduced miller capacitance according to the first embodiment of the present invention.

Fig. 3 is a flowchart of step S5 in the method for manufacturing a MOSFET with reduced miller capacitance according to the first embodiment of the present invention.

Fig. 4 is a schematic structural diagram of growing an epitaxial layer on the surface of a substrate and forming a trench.

Fig. 5 is a schematic structural diagram of forming a first oxide layer and silicon nitride.

Figure 6 is a schematic diagram of a structure for depositing a first polysilicon over silicon nitride.

Fig. 7 is a schematic view of the structure after etching the first polysilicon.

Fig. 8 is a schematic structural view of oxidizing the first polysilicon to form a second oxide layer.

Fig. 9 is a schematic diagram of a structure for etching silicon nitride.

FIG. 10 is a schematic diagram of a structure for etching a first oxide layer.

Fig. 11 is a schematic structural diagram of growing a third oxide layer.

Fig. 12 is a schematic diagram of the structure for depositing the second polysilicon.

Fig. 13 is a schematic diagram of a structure in which a portion of the second polysilicon is removed.

Fig. 14 is a schematic structural view of forming a body region and a source region.

Description of reference numerals:

1. a substrate; 2. an epitaxial layer; 3. a trench, 4, a first oxide layer; 5. silicon nitride; 6. a first polycrystalline silicon; 7. a second oxide layer; 8. a third oxide layer; 9. a second polycrystalline silicon; 10. a body region; 11. a source region.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to fig. 1, a first embodiment of the present invention discloses a method for manufacturing a MOSFET with reduced miller capacitance, which specifically includes the following steps:

step S1: an epitaxial layer 2 is grown on the surface of a substrate 1, trenches 3 are formed in the epitaxial layer 2, and a first oxide layer 4 is formed on the surfaces of the trenches 3. As shown in particular in fig. 4-5.

Step S2: and generating silicon nitride 5 on the surface of the first oxide layer 4, depositing first polysilicon 6 on the silicon nitride 5, and etching the first polysilicon 6 in the trench 3 to reserve part of the first polysilicon 6 at the bottom of the trench 3. As shown in particular in fig. 5-7.

Step S3: the first polysilicon 6 is oxidized to produce a second oxide layer 7. As shown in particular in fig. 8.

Step S4: the silicon nitride 5 is etched such that the silicon nitride 5 is level with the height of the second oxide layer 7. As shown in particular in fig. 9.

Step S5: the first oxide layer 4 is etched such that the first oxide layer 4 is level with the height of the silicon nitride 5. As shown in particular in fig. 10.

Step S6: and growing a third oxide layer 8 on the side wall of the trench 3, wherein the third oxide layer 8 extends to one end of the first oxide layer 4. As shown in particular in fig. 11.

Step S7: a second polysilicon 9 is deposited within the trench 3 and the second polysilicon 9 is etched such that the height of the second polysilicon 9 is lower than the height of the trench 3. As shown particularly in fig. 12-13.

It is understood that, in step S1, the depth of the trench 3 is 1.0 to 3.0 μm.

It is understood that in step S2, silicon nitride 5 is grown on the surface of the first oxide layer 4, and then first polysilicon 6 is deposited to fill the trench 3, and the first polysilicon 6 is N-doped polysilicon or P-doped polysilicon or undoped polysilicon. And etching the first polysilicon 6 to remove the first polysilicon 6 outside the trench 3, and simultaneously, further etching the first polysilicon 6 in the trench 3 to reserve the first polysilicon 6 at the bottom of the trench 3, wherein the thickness of the reserved first polysilicon 6 in the depth direction of the trench 3 is 0.2-0.5 microns.

It can be understood that, in step S3, the first polysilicon 6 is completely oxidized by the oxidation process at 800-. It should be noted that in step S3, during the reaction of the oxygen atoms with the silicon atoms of the first polysilicon 6 to form the second oxide layer 7, the top plane of the second oxide layer 7 gradually moves upward.

It is understood that in step S4, the silicon nitride 5 above the height of the second oxide layer 7 is removed so that the silicon nitride 5 is flush with the height of the second oxide layer 7.

It is understood that in step S5, the first oxide layer 4 above the height of the silicon nitride 5 is removed so that the first oxide layer 4 is flush with the height of the silicon nitride 5, and after etching the first oxide layer 4, a portion of the sidewall of the trench 3 is exposed.

It can be understood that, in step S6, an oxidation process at 800-.

It is to be understood that in step S7, the second polysilicon 9 is deposited in the trench 3 to fill the vacant areas in the trench 3, and the deposited second polysilicon 9 is etched down so that the height of the second polysilicon 9 is lower than the height of the trench 3, and specifically, the height of the second polysilicon 9 is not higher than the height of the upper surface of the epitaxial layer 2. And the type of MOSFET is the same as the doping type of the second polysilicon 9, for example: the doping type of the second polysilicon 9 is N-type when the MOSFET is an N-type MOSFET, or P-type when the MOSFET is a P-type MOSFET. The second polysilicon 9 obtained is the polysilicon gate of the MOSFET.

It is understood that the trench MOSFET is obtained in which the first oxide layer 4 has a thickness of 30-300 nm and the silicon nitride 5 has a thickness of 30-200 nm.

Referring to fig. 1, the step S7 is followed by:

step S8: a body region 10 and a source region 11 are formed in the epitaxial layer in sequence. As shown in particular in fig. 14.

In step S8, the body region 10 ends closer to the bottom of the trench 3 higher than the second polysilicon 9 ends closer to the bottom of the trench 3 by a difference of 0.1-0.3 μm.

It can be understood that after step S8, the main structure of the MOSFET chip is completed, and the subsequent processes of contact hole, metal wire, passivation layer and backside processing of the MOSFET are conventional and will not be described herein.

It is understood that after step S8, during the contact hole, metal line, passivation layer and backside processing processes, the second polysilicon 9 is connected to the gate terminal, the body region 10 and the source region 11 are connected to the source terminal, and the substrate 1 is connected to the drain terminal (i.e. the substrate 1 and the epitaxial layer 2 are the drain terminal of the MOSFET).

Optionally, referring to fig. 2, as an embodiment, the step S4 specifically includes the following steps:

step S41: and etching the silicon nitride 5 on the top of the second oxide layer 7 by adopting an over-etching process, so that the silicon nitride 5 is flush with the second oxide layer 7 in height.

Step S42: the silicon nitride 5 forms first recessed regions on both sides of the second oxide layer 7 based on the isotropy of the etching process.

Correspondingly, referring to fig. 3, as an embodiment, the step S5 specifically includes:

step S51: and (3) corroding the first oxide layer 4 on the top of the silicon nitride 5 by adopting an over-corrosion process method so that the first oxide layer 4 is flush with the height of the silicon nitride 5.

Step S52: the first oxide layer 4 forms second recessed regions on both sides of the silicon nitride 5 based on isotropy of the etching process.

It is understood that in steps S41 and S51, in order to ensure that the silicon nitride 5 and the first oxide layer 4 in the removed region are completely etched away, 10 to 30% of over-etching margin is set, and in addition, the isotropy of the etching process is added, so that recessed regions are formed on both sides of the second oxide layer 7.

During the process of etching the first oxide layer 4, the second oxide layer 7 is also etched away in part at the same time, resulting in a reduction in the longitudinal thickness of the second oxide layer 7.

Compared with the prior art, the manufacturing method of the MOSFET for reducing the Miller capacitance has the following beneficial effects:

1. in the MOSFET manufactured by the method, the dielectric layer between the lower part of the second polysilicon (polysilicon gate) and the epitaxial layer (drain end) comprises the first oxide layer, the silicon nitride and the second oxide layer, while the dielectric layer between the lower part of the polysilicon gate and the drain end is a single gate oxide layer in the traditional method.

2. In the MOSFET manufactured by the method, the dielectric layer between the side surface of the second polysilicon (polysilicon gate) and the epitaxial layer (drain terminal) is the third oxide layer (gate oxide layer), but the longitudinal width of the third oxide layer is only 0.1-0.3 micrometer, while the width of the gate oxide layer is usually 0.3-0.9 micrometer in the traditional method, and as is known, the smaller the area (the smaller the width means the smaller the parasitic capacitance area) is, the smaller the corresponding capacitance value is, so the parasitic capacitance between the side surface of the polysilicon gate and the drain terminal of the MOSFET is much smaller than that of the traditional method.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.