阅读说明：本技术 半导体器件的制造方法 (Method for manufacturing semiconductor device ) 是由 胡良斌 朱红波 于 2021-11-11 设计创作，主要内容包括：本发明提供一种半导体器件的制造方法,包括：提供衬底,所述衬底上依次形成有衬垫氧化层和硬掩模层；刻蚀所述衬垫氧化层和所述硬掩模层形成暴露所述衬底的开口,并在所述开口的侧壁形成具有一设定厚度的保护层；以所述硬掩模层和所述保护层为掩模刻蚀所述开口暴露的衬底,在所述衬底内形成沟槽,并在所述沟槽的侧壁及底部形成第一氧化层；去除所述第一氧化层；在所述沟槽及所述开口内填充绝缘氧化层。本发明在开口的侧壁上形成具有设定厚度的保护层,减少或避免衬垫氧化层在所述第一氧化层的去除过程中发生回刻,从而确保所述绝缘氧化层填满所述沟槽及所述开口,避免绝缘氧化层和衬垫氧化层之间出现空洞。(The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a liner oxide layer and a hard mask layer are sequentially formed on the substrate; etching the pad oxide layer and the hard mask layer to form an opening exposing the substrate, and forming a protective layer with a set thickness on the side wall of the opening; etching the substrate exposed by the opening by taking the hard mask layer and the protective layer as masks, forming a groove in the substrate, and forming a first oxidation layer on the side wall and the bottom of the groove; removing the first oxide layer; and filling an insulating oxide layer in the groove and the opening. According to the invention, the protective layer with a set thickness is formed on the side wall of the opening, so that the back etching of the liner oxide layer in the removing process of the first oxide layer is reduced or avoided, the insulating oxide layer is ensured to fill the groove and the opening, and a cavity is avoided between the insulating oxide layer and the liner oxide layer.)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a liner oxide layer and a hard mask layer are sequentially formed on the substrate;

etching the pad oxide layer and the hard mask layer to form an opening exposing the substrate, and forming a protective layer with a set thickness on the side wall of the opening;

etching the substrate exposed by the opening by taking the hard mask layer and the protective layer as masks, forming a groove in the substrate, and forming a first oxidation layer on the side wall and the bottom of the groove;

removing the first oxide layer; and the number of the first and second groups,

and filling an insulating oxide layer in the groove and the opening.

2. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the protective layer is the same as a material of the first oxide layer.

3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the set thickness is 100A-1000A.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein a material of the protective layer includes silicon oxide.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the protective layer is formed by a low pressure chemical vapor deposition process.

6. The method according to claim 1, wherein the insulating oxide layer is filled in the trench and the opening by an HDP process.

7. The method for manufacturing a semiconductor device according to claim 6, further comprising, after removing the first oxide layer and before filling the insulating oxide layer:

and forming a second oxide layer on the side wall and the bottom of the groove.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the process of forming the protective layer comprises:

forming a protective material layer on the side wall and the bottom of the opening, and extending to cover the hard mask layer on two sides of the opening;

and etching and removing the surface of the hard mask layer and the protective material layer at the bottom of the opening to form the protective layer.

9. The method for manufacturing a semiconductor device according to claim 1, wherein an anti-reflection layer is further formed on the hard mask layer, and the protective layer covers sidewalls of the pad oxide layer, the hard mask layer, and the anti-reflection layer.

10. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the pad oxide layer is in a range of 400A-800A.

Technical Field

The invention relates to the technical field of integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device.

Background

In a process for manufacturing a high-voltage device, the thickness of a Pad oxide layer (Pad oxide) is usually 400A-800A so as to be directly reserved as a gate oxide layer in a subsequent process, and process steps are simplified. However, referring to fig. 1 and 2, during the STI (Shallow Trench Isolation) etching process of the Isolation Trench 101, the SiN pull back process of the silicon nitride layer 120, and the precleaning of the first oxide layer 130 (the first oxide layer 130 is formed on the sidewall and the bottom of the Isolation Trench 101), the Pad oxide layer 110 (i.e., Pad oxide) may undercut under the action of the etching selectivity and WET Etching (WET), and a profile defect similar to "necking" occurs (as in the case of a in fig. 1). Meanwhile, since the liner oxide layer 110 is thick, the "neck" feature cannot be completely repaired in the subsequent process, and thus a void (as indicated by B in fig. 2) is left at the "neck" after the insulating oxide layer 140 is filled and formed in the isolation trench 101 (i.e., after the STI-HDP deposition process).

Accordingly, a solution to the above problem is needed to avoid the formation of voids in the oxide layer.

Disclosure of Invention

The invention aims to provide a method for manufacturing a semiconductor device, which is characterized in that a protective layer is formed on the side wall of an opening, so that the occurrence of back etching of a liner oxide layer in the subsequent process of removing other oxide layers is reduced or avoided, and further, the formation of a cavity is avoided.

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a liner oxide layer and a hard mask layer are sequentially formed on the substrate;

etching the pad oxide layer and the hard mask layer to form an opening exposing the substrate, and forming a protective layer with a set thickness on the side wall of the opening;

etching the substrate exposed by the opening by taking the hard mask layer and the protective layer as masks, forming a groove in the substrate, and forming a first oxidation layer on the side wall and the bottom of the groove;

removing the first oxide layer; and the number of the first and second groups,

and filling an insulating oxide layer in the groove and the opening.

Optionally, the material of the protective layer is the same as the material of the first oxide layer.

Optionally, the thickness is set to be 100-1000A.

Optionally, the material of the protective layer includes silicon oxide.

Optionally, the protective layer is formed by a low pressure chemical vapor deposition process.

Optionally, the trench and the opening are filled with the insulating oxide layer by using an HDP process.

Optionally, after removing the first oxide layer and before filling the insulating oxide layer, the method further includes:

and forming a second oxide layer on the side wall and the bottom of the groove.

Optionally, the process of forming the protective layer includes:

forming a protective material layer on the side wall and the bottom of the opening, and extending to cover the hard mask layer on two sides of the opening;

and etching and removing the protective material layer on the surface of the hard mask layer and at the bottom of the opening to form the protective layer.

Optionally, an anti-reflection layer is further formed on the hard mask layer, and the protective layer covers sidewalls of the pad oxide layer, the hard mask layer, and the anti-reflection layer.

Optionally, the thickness range of the pad oxide layer is 400A-800A.

In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a liner oxide layer and a hard mask layer are sequentially formed on the substrate; etching the pad oxide layer and the hard mask layer to form an opening exposing the substrate, and forming a protective layer with a set thickness on the side wall of the opening; etching the substrate exposed by the opening by taking the hard mask layer and the protective layer as masks, forming a groove in the substrate, and forming a first oxidation layer on the side wall and the bottom of the groove; removing the first oxide layer; and filling an insulating oxide layer in the groove and the opening. According to the invention, the protective layer with the set thickness is formed on the side wall of the opening, so that the back etching of the liner oxide layer in the removing process of the first oxide layer is reduced or avoided, the insulating oxide layer is ensured to fill the groove and the opening, and a cavity is avoided between the insulating oxide layer and the liner oxide layer.

Drawings

It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.

Fig. 1 and 2 are schematic structural diagrams corresponding to different steps in the manufacturing process of a high-voltage device.

Fig. 3 is a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 4 to fig. 13 are schematic structural diagrams corresponding to respective steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Wherein the reference numbers are as follows:

100-a substrate; 101-an isolation trench; 110-pad oxide layer; a 120-silicon nitride layer; 130-a first oxide layer; 140-insulating oxide layer;

200-a substrate; 201-opening; 202-a trench; 210-a liner oxide layer; 220-a hard mask layer; 221-an anti-reflection layer; 230-a patterned photoresist layer; 240-a layer of protective material; 241-a protective layer; 250-a first oxide layer; 260-a second oxide layer; 270-insulating oxide layer.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 3 is a method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 3, the method for manufacturing a semiconductor device according to the present embodiment includes:

step S01: providing a substrate, wherein a liner oxide layer and a hard mask layer are sequentially formed on the substrate;

step S02: etching the pad oxide layer and the hard mask layer to form an opening exposing the substrate, and forming a protective layer with a set thickness on the side wall of the opening;

step S03: etching the substrate exposed by the opening by taking the hard mask layer and the protective layer as masks, forming a groove in the substrate, and forming a first oxidation layer on the side wall and the bottom of the groove;

step S04: removing the first oxide layer; and the number of the first and second groups,

step S05: and filling an insulating oxide layer in the groove and the opening.

Fig. 4 to fig. 13 are schematic structural diagrams corresponding to respective steps in a manufacturing method of a semiconductor device according to an embodiment of the present invention, and the manufacturing method of the semiconductor device according to the embodiment is described in detail below with reference to fig. 4 to fig. 13.

First, referring to fig. 4, step S01 is performed to provide a substrate 200, wherein a pad oxide layer 210 and a hard mask layer 220 are sequentially formed on the substrate 200. In this embodiment, the substrate 200 is a silicon substrate, the material of the pad oxide layer 210 includes silicon oxide, and the material of the hard mask layer 220 includes silicon nitride, in other embodiments of the present invention, the material of the substrate 200 may also be a silicon germanium substrate, a group iii-v element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or may also be a diamond substrate or other semiconductor material substrates known to those skilled in the art, and the materials of the pad oxide layer 210 and the hard mask layer 220 may also be selected according to actual needs, which is not limited in the present invention. Optionally, the thickness range of the pad oxide layer 210 is 400A-800A.

Next, referring to fig. 4-8, step S02 is performed, in which the pad oxide layer 210 and the hard mask layer 220 are etched to form an opening 201 exposing the substrate 200, and a protection layer 241 having a predetermined thickness is formed on a sidewall of the opening 201. Specifically, the process of forming the opening 201 includes: a patterned photoresist layer 230 is formed on the surface of the hard mask layer 220, and the hard mask layer 220 and the pad oxide layer 210 are etched using the patterned photoresist layer 230 as a mask to form the opening 201. In other embodiments of the present invention, the opening 201 may be formed by other methods, which is not limited by the present invention. Optionally, after forming the opening 201, the method further includes: the patterned photoresist layer 230 is removed using an ashing process and a wet etching process. Optionally, an anti-reflection layer 221 is further formed between the hard mask layer 220 and the patterned photoresist layer 230, and the protection layer 241 covers sidewalls of the pad oxide layer 210, the hard mask layer 220, and the anti-reflection layer 221.

In this embodiment, the process of forming the protection layer 241 includes: forming a protective material layer 240 on the sidewall and the bottom of the opening 201, and extending to cover the hard mask layer 220 on both sides of the opening 201; and etching to remove the surface of the hard mask layer 220 and the protective material layer 240 at the bottom of the opening 201 to form the protective layer 241. Alternatively, the protective material layer 240 is formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process. Optionally, the thickness is set to be 100-1000A.

Subsequently, referring to fig. 9 and 10, step S03 is performed, the substrate 200 exposed by the opening 201 is etched by using the hard mask layer 220 and the protection layer 241 as masks, a trench 202 is formed in the substrate 200, and a first oxide layer 250 is formed on the sidewall and the bottom of the trench 202. Since the protection layer 241 covers the sidewall of the pad oxide layer 210, the pad oxide layer 210 is not damaged under the protection of the protection layer 241 during the formation of the trench 202. Optionally, the trench 202 is formed by dry etching.

In this embodiment, the first oxide layer 250 is formed on the sidewall and the bottom of the trench 202 by a thermal oxidation growth process, and the material of the protection layer 241 is the same as that of the first oxide layer 250.

Next, referring to fig. 11, step S04 is performed to remove the first oxide layer 250. In this embodiment, the wet cleaning is used to remove the first oxide layer 250, so that the bottom of the trench 202 is smoother, and in the wet cleaning process of the first oxide layer 250, the protection layer 241 and the first oxide layer 250 are removed together, and the pad oxide layer 210 is not damaged or is slightly damaged under the protection of the protection layer 241, thereby reducing or avoiding appearance defects similar to "neck shrinkage".

Subsequently, referring to fig. 12 and 13, step S05 is performed to fill the trench 202 and the opening 201 with an insulating oxide layer 270. In this embodiment, an HDP process is adopted to fill the insulating oxide layer 270, and meanwhile, in order to ensure that the substrate 200 is not damaged in the HDP process, after removing the first oxide layer 250 and before forming the insulating oxide layer 270, the method further includes: a second oxide layer 260 is formed on the sidewalls and bottom of the trench 202. Optionally, the second oxide layer 260 is formed by thermal oxidation growth. In other embodiments of the present invention, the method for forming the insulating oxide layer 270 may be adjusted according to actual needs, which is not limited in the present invention.

Referring to fig. 13, in steps S03 and S04, the pad oxide layer 210 is not damaged or is damaged very little under the protection of the passivation layer 241, so that the appearance of a "necking" like defect is reduced or avoided, and therefore, the insulating oxide layer 270 formed subsequently can fill the trench 202 and the opening 201, thereby reducing or avoiding the possibility of voids in the oxide layers (i.e., between the pad oxide layer 210, the insulating oxide layer 270, and the second oxide layer 260).

In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a liner oxide layer and a hard mask layer are sequentially formed on the substrate; etching the pad oxide layer and the hard mask layer to form an opening exposing the substrate, and forming a protective layer with a set thickness on the side wall of the opening; etching the substrate exposed by the opening by taking the hard mask layer and the protective layer as masks, forming a groove in the substrate, and forming a first oxidation layer on the side wall and the bottom of the groove; removing the first oxide layer; and filling an insulating oxide layer in the groove and the opening. According to the invention, the protective layer with the set thickness is formed on the side wall of the opening, so that the back etching of the liner oxide layer in the removing process of the first oxide layer is reduced or avoided, the insulating oxide layer is ensured to fill the groove and the opening, and a cavity is avoided between the insulating oxide layer and the liner oxide layer.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.