阅读说明：本技术 带有屏蔽栅结构mosfet器件及其制造方法 (MOSFET device with shielded gate structure and method of manufacturing the same ) 是由 颜树范 刘须电 于 2021-08-05 设计创作，主要内容包括：本申请涉及半导体集成电路制造技术领域,具体涉及一种带有屏蔽栅结构MOSFET器件及其制造方法。其中方法包括：刻蚀带有第一介质层的基底层,使得基底层中形成在纵向上延伸的沟槽；制作第二介质层,使得第二介质层至少覆盖在沟槽的表面；在得带有第二介质层的沟槽中填充有第一多晶硅,使得位于隔离区位置处的沟槽中形成沟槽屏蔽栅结构；进行第一光刻,刻蚀去除位于器件有源区位置处沟槽中的第一多晶硅上部；填充第三介质层,使得第三介质层至少填充满剩余第一多晶硅上方的沟槽空间；进行第二光刻,通过干法刻蚀去除有源区位置处沟槽中的介质层上部,形成控制栅容置空间；在控制栅容置空间中填充第二多晶硅；制作正面金属层和背面金属层。(The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a MOSFET device with a shielding grid structure and a manufacturing method thereof. The method comprises the following steps: etching the substrate layer with the first dielectric layer to form a groove extending in the longitudinal direction in the substrate layer; manufacturing a second dielectric layer to enable the second dielectric layer to at least cover the surface of the groove; filling first polysilicon in the obtained groove with the second dielectric layer, so as to form a groove shielding gate structure in the groove at the position of the isolation region; carrying out first photoetching, and etching to remove the upper part of the first polysilicon in the groove at the position of the active region of the device; filling the third dielectric layer to at least fill the groove space above the residual first polysilicon; performing second photoetching, and removing the upper part of the dielectric layer in the groove at the position of the active region through dry etching to form a control gate accommodating space; filling second polysilicon in the control gate accommodating space; and manufacturing a front metal layer and a back metal layer.)

1. A manufacturing method of a MOSFET device with a shielding gate structure is characterized by comprising the following steps:

providing a substrate layer with a first medium layer formed on the front surface;

etching the substrate layer with the first dielectric layer to form a groove extending in the longitudinal direction in the substrate layer;

manufacturing a second dielectric layer to enable the second dielectric layer to at least cover the surface of the groove;

filling first polysilicon in the groove with the second dielectric layer, so as to form a groove shielding gate structure in the groove at the position of the isolation region;

carrying out first photoetching, and etching to remove the upper part of the first polysilicon in the groove at the position of the active region of the device;

filling a third dielectric layer to ensure that the third dielectric layer at least fills the groove space above the rest first polysilicon;

performing second photoetching, and removing the upper part of the dielectric layer in the groove at the position of the active region through dry etching to form a control gate accommodating space, so that a third dielectric layer is isolated between the first polysilicon remaining in the groove at the position of the active region and the control gate accommodating space;

filling second polysilicon in the control gate accommodating space;

and manufacturing a front metal layer and a back metal layer, wherein the front metal layer comprises an active region metal layer and an isolation region metal layer which are spaced, and the isolation region metal layer is electrically communicated with the first polysilicon of the trench shielding gate structure.

2. The method of manufacturing a MOSFET device with a shielded gate structure of claim 1, wherein the first photolithography process and the second photolithography process each comprise:

coating a photoresist layer on the surface of the device;

exposing the photoresist layer through a first mask plate, so that the first mask plate shields the isolation region of the device and exposes the active region of the device;

and developing and removing the photoresist layer at the position of the active region, so that the photoresist layer at the position of the isolation region is remained.

3. The method of manufacturing a MOSFET device with a shielded gate structure of claim 2, wherein said performing a first photolithography process comprises:

coating a first photoresist layer on the upper surface of the device after the step of filling the groove with the second dielectric layer with the first polysilicon is finished;

exposing the first photoresist layer through a first mask plate, so that the first mask plate covers an isolation region of the device and exposes an active region of the device;

and developing and removing the first photoresist layer at the position of the active region, so that the first photoresist layer at the position of the isolation region is remained.

4. The method of fabricating a MOSFET device with a shielded gate structure as claimed in claim 3 wherein said step of etching away the upper portion of the first polysilicon in the trench at the location of the active area of said device comprises:

and etching the first polysilicon to reserve the first polysilicon in the groove at the position of the isolation region under the protection of the first photoresist layer and remove the upper part of the first polysilicon in the groove at the position of the active region.

5. The method of manufacturing a MOSFET device with a shielded gate structure of claim 2, wherein said performing a second photolithography process comprises:

coating a second photoresist layer on the upper surface of the device after the step of filling the third dielectric layer so that the third dielectric layer at least fills the groove space above the residual first polysilicon;

exposing the second photoresist layer through a first mask plate, so that the first mask plate covers an isolation region of the device and exposes an active region of the device;

and developing and removing the second photoresist layer at the position of the active region, so that the second photoresist layer at the position of the isolation region is remained.

6. The method of manufacturing a MOSFET device with a shielded gate structure as recited in claim 5,

the step of removing the upper part of the third dielectric layer in the groove at the position of the active region of the device by dry etching to form a control gate accommodating space comprises the following steps:

and performing dry etching on the third dielectric layer, so that the third dielectric layer in the groove at the position of the isolation region is reserved under the protection of the second photoresist layer, and the upper part of the third dielectric layer in the groove at the position of the active region is removed, so that a control gate accommodating space is formed at the upper part of the groove at the position of the active region.

7. The method of claim 1, wherein the active region metal layer overlies the active region and the isolation region metal layer overlies the isolation region.

8. The method of claim 1, wherein the trench shield gate structure closest to the active region is a first trench shield gate, and all trench shield gate structures including the first trench shield gate are in electrical communication with the isolation region metal layer.

9. The method of fabricating a MOSFET device with a shielded gate structure of claim 8, wherein the first trench shielded gate is located at an edge of the active region.

10. A MOSFET device with a shielded gate structure, characterized in that it is manufactured by a method of manufacturing a MOSFET device with a shielded gate structure according to any of claims 1 to 9.

Technical Field

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a MOSFET device with a shielding grid structure and a manufacturing method thereof.

Background

For the power device, an isolation region is formed on the periphery of an active region of the power device so as to isolate the power device from other power devices. Usually, a plurality of annular trench shielding gate structures are formed in the isolation region to perform the isolation function.

However, in the manufacturing process of the MOSFET device with the shielded gate structure, wet etching is usually used to form the control gate filling space of the gate structure of the device, and since lateral etching occurs during the wet etching process while longitudinal etching occurs, the oxide layer on the upper portion of the first trench shielded gate near the active region is damaged. Therefore, the related art typically floats, i.e., does not connect to a potential, the first trench shield gate near the active region.

Fig. 1 shows a MOSFET device with a shielded gate structure formed by a related art manufacturing method, as can be seen from fig. 1, the MOSFET device includes an active area 101 and an isolation area 102, the active area 101 is covered with an active metal layer 131, the isolation area 102 is covered with an isolation metal layer 132, a gate structure 12 of the active device is formed in the active area 101, and a plurality of trench shielded gates 11 are formed in the isolation area 102. The first trench shield gate 11A is the trench shield gate closest to the active region 101. For the above reasons, the upper oxide layer of the first trench shield gate 11A may be damaged to form a pocket recess, and the pocket recess may be filled with a polysilicon layer during the subsequent fabrication process of the gate structure 12. In order to prevent the upper and lower polysilicon in the first trench shielding gate 11A from being shorted at the terminals, the isolation metal layer 132 is electrically connected to the other trench shielding gates 11 except the first trench shielding gate 11A, so that the first trench shielding gate 11A is floated.

However, the floating of the first trench shield gate 11A results in that the device epitaxy at this position cannot be depleted, the shielding performance is reduced, and even the device may break down in advance.

Disclosure of Invention

The application provides a MOSFET device with a shielding grid structure and a manufacturing method thereof, which can solve the problem of early breakdown of the device caused by floating of a groove shielding grid in the related technology.

To solve the technical problems described in the background, a first aspect of the present application provides a method for manufacturing a MOSFET device with a shielded gate structure, the method comprising the steps of:

providing a substrate layer with a first medium layer formed on the front surface;

etching the substrate layer with the first dielectric layer to form a groove extending in the longitudinal direction in the substrate layer;

manufacturing a second dielectric layer to enable the second dielectric layer to at least cover the surface of the groove;

filling first polysilicon in the groove with the second dielectric layer, so as to form a groove shielding gate structure in the groove at the position of the isolation region;

carrying out first photoetching, and etching to remove the upper part of the first polysilicon in the groove at the position of the active region of the device;

filling a third dielectric layer to ensure that the third dielectric layer at least fills the groove space above the rest first polysilicon;

performing second photoetching, and removing the upper part of the dielectric layer in the groove at the position of the active region through dry etching to form a control gate accommodating space, so that a third dielectric layer is isolated between the first polysilicon remaining in the groove at the position of the active region and the control gate accommodating space;

filling second polysilicon in the control gate accommodating space;

and manufacturing a front metal layer and a back metal layer, wherein the front metal layer comprises an active region metal layer and an isolation region metal layer which are spaced, and the isolation region metal layer is electrically communicated with the first polysilicon of the trench shielding gate structure.

Optionally, the first lithography process and the second lithography process each include:

coating a photoresist layer on the surface of the device;

exposing the photoresist layer through a first mask plate, so that the first mask plate shields the isolation region of the device and exposes the active region of the device;

and developing and removing the photoresist layer at the position of the active region, so that the photoresist layer at the position of the isolation region is remained.

Optionally, the performing the first lithography includes:

coating a first photoresist layer on the upper surface of the device after the step of filling the groove with the second dielectric layer with the first polysilicon is finished;

exposing the first photoresist layer through a first mask plate, so that the first mask plate covers an isolation region of the device and exposes an active region of the device;

and developing and removing the first photoresist layer at the position of the active region, so that the first photoresist layer at the position of the isolation region is remained.

Optionally, the step of removing, by etching, an upper portion of the first polysilicon in the trench at the position of the active region of the device includes:

and etching the first polysilicon to reserve the first polysilicon in the groove at the position of the isolation region under the protection of the first photoresist layer and remove the upper part of the first polysilicon in the groove at the position of the active region.

Optionally, the performing the second lithography process includes:

coating a second photoresist layer on the upper surface of the device after the step of filling the third dielectric layer so that the third dielectric layer at least fills the groove space above the residual first polysilicon;

exposing the second photoresist layer through a first mask plate, so that the first mask plate covers an isolation region of the device and exposes an active region of the device;

and developing and removing the second photoresist layer at the position of the active region, so that the second photoresist layer at the position of the isolation region is remained.

Optionally, the step of removing, by dry etching, the upper portion of the third dielectric layer in the trench at the position of the active region of the device to form the control gate accommodating space includes:

and performing dry etching on the third dielectric layer, so that the third dielectric layer in the groove at the position of the isolation region is reserved under the protection of the second photoresist layer, and the upper part of the third dielectric layer in the groove at the position of the active region is removed, so that a control gate accommodating space is formed at the upper part of the groove at the position of the active region.

Optionally, the active region metal layer covers the active region, and the isolation region metal layer covers the isolation region.

Optionally, the trench shielding gate structure closest to the active region is a first trench shielding gate, and all trench shielding gate structures including the first trench shielding gate are electrically connected to the isolation region metal layer.

Optionally, the first trench shielding gate is located at an edge of the active region.

A second aspect of the present application provides a MOSFET device with a shielded gate structure, which is manufactured by the method for manufacturing a MOSFET device with a shielded gate structure according to the first aspect of the present application.

The technical scheme at least comprises the following advantages: the dielectric layer of the device on the upper portion of the groove at the position of the active region is removed through dry etching, so that a transverse effect cannot occur on a photoresist layer during etching, etching damage of the first groove shielding grid close to the active region is avoided, the first groove shielding grid close to the active region can be connected with an isolation region metal layer, and a potential is applied to the first groove shielding grid through the isolation region metal layer, so that the groove shielding grid can be exhausted to an epitaxial layer, breakdown voltage of the device is guaranteed, and the device is prevented from being broken in advance.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic cross-sectional diagram of a MOSFET device with a shielded gate structure formed in a related art fabrication;

fig. 2 is a flow chart illustrating a method for manufacturing a MOSFET device with a shielded gate structure according to an embodiment of the present application;

FIG. 2a is a schematic cross-sectional diagram illustrating the device after step S22 is completed according to an embodiment;

FIG. 2b is a schematic cross-sectional view of the device after step S23 is completed;

FIG. 2c is a schematic cross-sectional view of the trench with the second dielectric layer filled with the first polysilicon;

FIG. 2d is a schematic cross-sectional diagram illustrating the device after step S25 is completed according to an embodiment;

FIG. 2e is a schematic cross-sectional diagram illustrating the device after step S26 is completed according to an embodiment;

FIG. 2f is a schematic cross-sectional diagram illustrating the device after step SS27 is completed according to one embodiment;

FIG. 2g is a schematic cross-sectional view of the device after step S28 is completed;

fig. 2h shows a schematic cross-sectional structural diagram of the device after step S29 is completed.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Fig. 2 is a flowchart illustrating a method for manufacturing a MOSFET device with a shielded gate structure according to an embodiment of the present application, and as can be seen from fig. 2, the method for manufacturing a MOSFET device with a shielded gate structure includes the following steps S21 to S29, which are performed in sequence, wherein:

step S21: a base layer is provided having a first dielectric layer formed on a front side.

Step S22: the base layer with the first dielectric layer is etched such that trenches extending in a longitudinal direction are formed in the base layer.

Fig. 2a shows a schematic cross-sectional structure of the device after step S22 is completed, and as can be seen from fig. 2a, a first dielectric layer 211 is formed on the front side of the base layer 200, the base layer 200 includes an active region 201 for forming an active structure of the device and an isolation region 202 for forming an isolation structure of the device, and the isolation region 202 surrounds the periphery of the active region 201. The trenches 220 are formed to extend downwardly from the front side of the substrate layer 200, with the trenches 220 being spaced apart from one another. Wherein, the trench 220 closest to the active region 201 in the isolation region 202 is located at the edge of the active region 201.

The trenches 220 located in the active region 201 are used to form the gate structure of the active structure of the device, and the trenches 220 located in the isolation region 202 are used to form the trench shield gate structure.

Step S23: and manufacturing a second dielectric layer so that the second dielectric layer at least covers the surface of the groove.

Referring to fig. 2b, which shows a schematic cross-sectional structural view of the device after step S23 is completed, it can be seen from fig. 2b that step S23 forms a second dielectric layer 212 on the structure shown in fig. 2a according to the topography of the structure shown in fig. 2a, and the second dielectric layer 212 covers the front surface of the remaining first dielectric layer 211 and the bottom and side surfaces of the trench 220.

Step S24: and filling first polysilicon in the trench with the second dielectric layer, so as to form a trench shielding gate structure in the trench at the position of the isolation region.

Referring to fig. 2c, a schematic cross-sectional view of the trench with the second dielectric layer filled with the first polysilicon is shown. The device structure shown in fig. 2c can be formed by first depositing the first polysilicon 231 on the front surface of the device structure shown in fig. 2b, so that the trench 220 with the second dielectric layer 212 is filled with the first polysilicon 231, then etching back the device deposited with the first polysilicon 231, removing the first polysilicon 231 at a position outside the trench 220, and retaining the first polysilicon 231 in the trench 220. A trench shield gate structure is formed in the trench 220 at the location of the isolation region 202 and comprises a second dielectric layer 212 and a first polysilicon 231 in the trench 220 at the location of the isolation region 202.

Step S25: and carrying out first photoetching, and etching to remove the upper part of the first polysilicon in the groove at the position of the active region of the device.

Referring to fig. 2d, which shows a schematic cross-sectional structure of the device after step S25 is completed, as can be seen from fig. 2d, the device structure shown in fig. 2c is subjected to step S25, the upper portion of the first polysilicon 231 in the trench 220 at the location of the active region 201 is etched and removed, and the first polysilicon 231 in the trench 220 at the location of the isolation region 202 is not etched and remains, so as to form the device structure shown in fig. 2 d.

Step S26: and filling a third dielectric layer to at least fill the groove space above the residual first polysilicon.

Referring to fig. 2e, a schematic cross-sectional structure diagram of the device after step S26 is completed according to an embodiment. Step S26 is to fabricate the third dielectric layer 213 on the basis of the device structure shown in fig. 2d, such that the third dielectric layer 213 covers the upper surface of the second dielectric layer 212 and fills the trench space above the remaining first polysilicon 231. Wherein the trench space above the remaining first polysilicon 231 includes a trench space at the location of the active region 201 and a trench space at the location of the isolation region 202. A planarization of the third dielectric layer 213 is then performed so that the device structure shown in fig. 2e is formed.

Step S27: and carrying out second photoetching, and removing the upper part of the dielectric layer in the groove at the position of the active region through dry etching to form a control gate accommodating space, so that a third dielectric layer is isolated between the first polysilicon remaining in the groove at the position of the active region and the control gate accommodating space.

Wherein the dry etching adopts a menu with high selection ratio. The high selection ratio menu means that the substrate layer 200 is not damaged or the substrate layer 200 is hardly damaged when the surface second dielectric layer 212 and the third dielectric layer 213 filled in the trench are removed. According to practical requirements, the high selection ratio menu requires that the etching rate of the dielectric layer 212/213 is at least 10 times faster than the etching rate of the substrate layer 200.

Referring to fig. 2f, which shows a schematic cross-sectional structure of the device after step SS27 is completed, it can be seen from fig. 2f that, in the trench 220 at the position of the active region 201, the upper portion of the third dielectric layer 213 is etched away, and the portion of the second dielectric layer 212 corresponding to the etched away portion of the third dielectric layer 213 is also etched away, so as to form a control gate accommodating space 240 above the trench 22 in the active region 201. In the trench 22 of the active region 201, the third dielectric layer 213 that is not removed by etching is isolated between the remaining first polysilicon 231 and the control gate accommodating space 240, and the first polysilicon 231 is isolated from the side surface and the bottom surface of the trench 220 of the active region 201 by the remaining second dielectric layer 212. The trench 220 of the isolation region 202 is filled with a first polysilicon layer 231, and the first polysilicon layer 231 is isolated from the side surface and the bottom surface of the trench 220 of the isolation region 202 by a second dielectric layer 212, so that a trench shield gate structure is formed in the trench 220 of the isolation region 202.

Because the third dielectric layer 213 and the second dielectric layer 212 of the device on the upper portion of the trench 220 at the position of the active region 202 are removed by dry etching, a lateral effect is not generated, and the first trench shielding gate close to the active region 201 is prevented from being damaged by etching.

Step S28: and filling the control gate accommodating space with second polysilicon.

Referring to fig. 2g, which shows a schematic cross-sectional structure of the device after step S28 is completed, it can be seen from fig. 2g that, on the basis of the structure shown in fig. 2f, a fourth dielectric layer 214 is deposited first, so that the fourth dielectric layer 214 covers the surface of the device structure shown in fig. 2f, and thus the bottom surface and the side surfaces of the control gate accommodating space 240 are covered by the fourth dielectric layer 214. Then, a second polysilicon 232 is deposited, so that the control gate accommodating space 240 with the fourth dielectric layer 214 is filled with the second polysilicon 232, thereby forming the device structure shown in fig. 2g, the device shown in fig. 2g, wherein a first polysilicon 231 and a second polysilicon 232 formed on the first polysilicon 231 are formed in the trench 220 of the active region 201.

Step S29: and manufacturing a front metal layer and a back metal layer, wherein the front metal layer comprises an active region metal layer and an isolation region metal layer which are spaced, and the isolation region metal layer is electrically communicated with the first polysilicon of the trench shielding gate structure.

Referring to fig. 2h, a schematic cross-sectional structural diagram of the device after step S29 is completed is shown. Ion implantation may be performed on the device structure shown in fig. 2g to form source and drain regions 280, where the source and drain regions 280 are located in the substrate layer 200 at two sides of the trench 220 and extend downward from the front surface of the substrate layer 200. An isolation layer 270 is then formed on the front surface of the ion implanted device such that the isolation layer 270 covers the front surface of the substrate layer 200. Contact holes are then made in this isolation layer 270 so that the contact holes at the location of the active area 201 are in contact with the second polysilicon 232 or with the source and drain regions 280 so that the contact holes at the location of the isolation region 202 are in contact with the first polysilicon 231. Forming a front metal layer on the isolation layer 270 having the contact hole, wherein the front metal layer includes: an active region metal layer 251 overlying the active region 201, and an isolation region metal layer 252 overlying the isolation region 202, the active region metal layer 251 and the isolation region metal layer 252 being spaced apart.

The trench shielding gate structure closest to the active region 201 is a first trench shielding gate 21A, and the first trench shielding gate 21A is located at the edge of the active region 201; all trench shield gate structures, including the first trench shield gate 21A, are in electrical communication with the isolation region metal layer 252.

The active region metal layer 25 is electrically connected to the source drain region 280 or the second polysilicon 232 at the position of the active region 201.

When the device is used, the isolation region metal layer is used for being connected with a specific potential, so that the second polycrystalline silicon in the isolation region groove is used up for the epitaxial layer, the breakdown voltage of the device is guaranteed, and the device is prevented from being broken down in advance.

In the embodiment, the dielectric layer on the upper part of the trench of the device at the position of the active region is removed by dry etching, so that a transverse effect cannot occur on a photoresist layer during etching, the first trench shielding gate close to the active region is prevented from being damaged by etching, the first trench shielding gate close to the active region can be connected with the isolation region metal layer, and a potential is applied to the first trench shielding gate through the isolation region metal layer, so that the trench shielding gate can be depleted on the epitaxial layer, the breakdown voltage of the device is guaranteed, and the device is prevented from being broken in advance.

When the first photolithography process in step S25 and the second photolithography process in step S27 are performed, the same mask may be used for photolithography, that is, the first mask may be used for exposure, so that the first mask shields the isolation region of the device and exposes the active region of the device. And then developing and removing the photoresist layer at the position of the active region, so that the photoresist layer at the position of the isolation region is remained.

Illustratively, the step of performing a first lithography to etch away the upper portion of the first polysilicon in the trench at the location of the active region of the device, as described in the step of performing S25, may include the following steps in sequence:

step S251: on the upper surface of the device structure shown in fig. 2c, a first photoresist layer is applied.

Step S252: and exposing the first photoresist layer through a first mask plate, so that the first mask plate covers the isolation region of the device and exposes the active region of the device.

All the grooves at the position of the isolation region are blocked by the first mask plate so as to prevent the first photoresist layer on the first mask plate from being exposed.

Step S253: and developing and removing the first photoresist layer at the position of the active region, so that the first photoresist layer at the position of the isolation region is remained.

All the grooves at the position of the isolation region are covered and protected by the second photoresist which is remained after development, so that the position is prevented from being etched by the subsequent steps.

Step S254: and etching the first polysilicon to reserve the first polysilicon in the groove at the position of the isolation region under the protection of the first photoresist layer and remove the upper part of the first polysilicon in the groove at the position of the active region.

After completion of this step S254, the device structure shown in fig. 2d is formed.

For example, the step of performing the second photolithography and removing the upper portion of the third dielectric layer in the trench at the position of the active region of the device by dry etching to form the control gate accommodating space in step S27 may include the following steps performed in sequence:

s271: on the upper surface of the device shown in fig. 2e, a second photoresist layer is applied.

S272: and exposing the second photoresist layer through a first mask plate, so that the first mask plate shields the isolation region of the device and exposes the active region of the device.

All the grooves at the position of the isolation region are blocked by the first mask plate so as to prevent the second photoresist layer on the first mask plate from being exposed.

S273: and developing and removing the second photoresist layer at the position of the active region, so that the second photoresist layer at the position of the isolation region is remained.

All the grooves at the position of the isolation region are covered and protected by the second photoresist which is remained after development, so that the position is prevented from being etched by the subsequent steps.

S274: and performing dry etching on the third dielectric layer, so that the third dielectric layer in the groove at the position of the isolation region is reserved under the protection of the second photoresist layer, and the upper part of the third dielectric layer in the groove at the position of the active region is removed, so that a control gate accommodating space is formed at the upper part of the groove at the position of the active region.

This step S274 is completed to form the device structure shown in fig. 2 f.

The present application further provides a shielded gate MOSFET device manufactured by the method of manufacturing a shielded gate MOSFET device as shown in fig. 2 or any one of fig. 2a to 2 h.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.