阅读说明：本技术 一种具有部分下沉沟道的4H-SiC金属半导体场效应晶体管 (4H-SiC metal semiconductor field effect transistor with partial sinking channel ) 是由 贾护军 董梦宇 王笑伟 朱顺威 杨银堂 于 2021-09-09 设计创作，主要内容包括：本发明涉及场效应晶体管技术领域,公开了一种具有部分下沉沟道的4H-SiC金属半导体场效应晶体管,自下而上包括4H-SiC半绝缘衬底、P型缓冲层和N型沟道层,所述N型沟道层的上方分别为源极帽层和漏极帽层,所述源极帽层和漏极帽层表面分别是源电极和漏电极,所述N型沟道层上方靠近源极的一侧形成栅电极,栅极与源极之间是轻掺杂区域,所述轻掺杂区域下方是部分下沉沟道的重掺杂区域,高栅下方与漏极之间为绝缘区域。本发明场效应晶体管具有高的击穿电压的同时还能保持高饱和电流与跨导,实现了较高的PAE。(The invention relates to the technical field of field effect transistors, and discloses a 4H-SiC metal semiconductor field effect transistor with a partial sinking channel, which comprises a 4H-SiC semi-insulating substrate, a P-type buffer layer and an N-type channel layer from bottom to top, wherein a source electrode cap layer and a drain electrode cap layer are respectively arranged above the N-type channel layer, the surfaces of the source electrode cap layer and the drain electrode cap layer are respectively a source electrode and a drain electrode, a gate electrode is formed on one side, close to the source electrode, above the N-type channel layer, a lightly doped region is arranged between the gate electrode and the source electrode, a heavily doped region of the partial sinking channel is arranged below the lightly doped region, and an insulating region is arranged between the lower part of the high gate electrode and the drain electrode. The field effect transistor has high breakdown voltage, can keep high saturation current and transconductance and realizes higher PAE.)

1. The 4H-SiC metal semiconductor field effect transistor with the partial sinking channel is characterized by comprising a 4H-SiC semi-insulating substrate (1), a P-type buffer layer (2) and an N-type channel layer (3) from bottom to top, wherein a source cap layer (4) and a drain cap layer (5) are respectively arranged above the N-type channel layer (3), the surfaces of the source cap layer (4) and the drain cap layer (5) are respectively a source electrode (6) and a drain electrode (7), a gate electrode (8) is formed on one side, close to the source electrode, above the N-type channel layer (3), a lightly doped region (9) is arranged between the gate and the source electrode, a heavily doped region (10) of the partial sinking channel is arranged below the lightly doped region, and an insulating region (11) is arranged between the high gate and the drain electrode.

2. The 4H-SiC MOSFET (metal-semiconductor field effect transistor) with a partially sinking channel as claimed in claim 1, wherein the lightly doped region (9) has a height of 0.15 μm, a width of 0.5 μm and a doping concentration of 1 x 10¹⁷cm^-3。

3. The 4H-SiC MOSFET (metal-semiconductor field effect transistor) with a partially sinking channel according to claim 1, wherein the heavily doped region (10) has a height of 0.2 μm, a width of 0.5 μm and a doping concentration of 1 x 10²⁰cm^-3。

4. The 4H-SiC MOSFET with a partially sinker channel according to claim 1, wherein the insulating region (11) has a height of 0.05 μm and a width of 1.5 μm.

5. The 4H-SiC metal semiconductor field effect transistor with the partial sinking channel of claim 1, wherein the gate electrode (8) has a gate-source pitch of 0.5 μm, a gate-drain pitch of 1.0 μm and a gate length of 0.7 μm.

6. The 4H-SiC metal semiconductor field effect transistor with the partial sinking channel according to claim 1, wherein the material adopted by the insulating region (11) is silicon nitride.

Technical Field

The invention relates to the technical field of field effect transistors, in particular to a 4H-SiC metal semiconductor field effect transistor with a partial sinking channel.

Background

The performance of the semiconductor device is greatly improved by the appearance of the SiC power device, which has great significance to the development of the power electronic industry. Compared with Si devices, SiC power devices can effectively achieve high efficiency, miniaturization, and light weight of power electronic systems. It is known that SiC power devices have half the energy consumption of Si devices, half the heat generation of Si devices, and higher current densities. At the same power level, the SiC power module is significantly smaller in volume than the Si power module. SiC is predominant in the application of microwave power devices, especially metal semiconductor field effect transistors (MESFETs). The SiCMMESFET is well suited for use in radar transmitters; the output power and the power density of the radar transmitter can be obviously improved by using the device, the working frequency and the working frequency bandwidth are improved, the environmental temperature adaptability of the radar transmitter is improved, and the radiation resistance is improved.

The structure of the conventional 4H-SiCMESFET is a double-concave gate structure, as shown in fig. 1, from bottom to top: the device comprises a 4H-SiC semi-insulating substrate, a P-type buffer layer, an N-type channel layer and an N + cap layer, and the performance of the device can be improved by changing the shape of the channel and the shape of the grid of the traditional structure. For example, CN105118867A discloses a 4H-SiC metal semiconductor field effect transistor with a partially sinking channel, wherein a gate electrode is formed above an N-type channel layer and on a side close to a source cap layer, a portion of the gate electrode close to the source cap layer is recessed downward to form a recessed gate structure, a recessed gate-drain drift region is formed between the gate electrode and the drain cap layer, a recessed gate-drain buffer layer is formed between an upper end surface of a P buffer layer close to the drain cap layer and the recessed gate-drain side, and a recessed depth of the recessed gate-drain drift region is the same as that of the recessed gate-drain buffer layer.

However, the improvement of the performance of the device is limited by the existing improvement, and many improved structures reduce the breakdown voltage of the device while improving the transconductance of the device, reduce the saturation current of the device while improving the breakdown voltage of the device, and reduce the frequency characteristic of the device while improving the saturation current of the device, namely the improvement of the performance of one aspect of the device is often accompanied with the reduction of the performance of one aspect of the device. This contradictory relationship seriously affects the improvement of device performance.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a 4H-SiC metal semiconductor field effect transistor having a partially sinker channel.

In order to achieve the purpose, the invention adopts the following technical scheme:

A4H-SiC metal semiconductor field effect transistor with a partial sinking channel comprises a 4H-SiC semi-insulating substrate, a P-type buffer layer and an N-type channel layer from bottom to top, wherein a source electrode cap layer and a drain electrode cap layer are respectively arranged above the N-type channel layer, the surfaces of the source electrode cap layer and the drain electrode cap layer are respectively a source electrode and a drain electrode, a gate electrode is formed on one side, close to a source electrode, above the N-type channel layer, a lightly doped region is arranged between the gate electrode and the source electrode, a heavily doped region of the partial sinking channel is arranged below the lightly doped region, and an insulating region is arranged between the lower side of the high gate electrode and the drain electrode.

Preferably, the lightly doped region has a height of 0.15 μm, a width of 0.5 μm, and a doping concentration of 1 × 10¹⁷cm^-3。

Preferably, the heavily doped region has a height of 0.2 μm, a width of 0.5 μm, and a doping concentration of 1 × 10²⁰cm^-3。

Preferably, the insulating region has a height of 0.05 μm and a width of 1.5 μm.

Preferably, the gate electrode has a gate-source pitch of 0.5 μm, a gate-drain pitch of 1.0 μm, and a gate length of 0.7 μm.

Preferably, the insulating region is made of silicon nitride (Si)₃N₄)。

Compared with the prior art, the invention has the following beneficial effects:

the field effect transistor has very high breakdown voltage, can keep high saturation current and transconductance and realizes higher PAE. Specifically, the method comprises the following steps:

(1) according to the field effect transistor, due to the existence of the insulating region, the distribution of an electric field in a channel is improved, so that the electric field edge effect is weakened, the right side of the grid is protected, and the breakdown voltage is obviously improved;

(2) according to the field effect transistor, the insulating region narrows part of channels, the heavy doping region with part of channels sinking is introduced, heavy doping is carried out on the sinking region, the phenomenon that the grid source capacitance is enlarged due to the fact that the heavy doping region in the channels is too large is effectively reduced, the saturation current of the device is greatly improved due to the heavy doping region, the improvement of the saturation current brings the improvement of the transconductance of the device, and the device can obtain higher power additional efficiency;

(3) according to the field effect transistor, due to the existence of the lightly doped region between the heavy doped region with a part of sunken channels and the gate source, the transconductance of the device is improved, meanwhile, the increase of the gate source capacitance is restrained, the PAE of the device is obviously improved, and meanwhile, the good frequency characteristic can be kept.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a dual recessed gate structure of a conventional 4H-SiCMMESFET;

FIG. 2 is a schematic diagram of a 4H-SiC metal semiconductor field effect transistor with a partial sinking channel according to the present invention;

reference numbers in the figures: the structure of the semiconductor device comprises a 4H-SiC semi-insulating substrate 1, a P-type buffer layer 2, an N-type channel layer 3, a source cap layer 4, a drain cap layer 5, a source electrode 6, a drain electrode 7, a gate electrode 8, a lightly doped region 9, a heavily doped region with a sunk part of a channel 10 and an insulating region 11.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications can be made by persons skilled in the art without departing from the spirit of the invention. All falling within the scope of the present invention.

Example 1

As shown in FIG. 2, a 4H-SiC metal semiconductor field effect transistor with a partial sinking channel has a structure comprising a 4H-SiC semi-insulating substrate 1 from bottom to top, with a width of 0.5 μm and a doping concentration of 1.4 × 10¹⁵cm^-3The P-type buffer layer 2 has a width of 0.25 μm and a doping concentration of 3X 10¹⁷cm^-3The N-type channel layer 3, a source electrode cap layer 4 and a drain electrode cap layer 5 are respectively arranged above the N-type channel layer 3, a source electrode 6 and a drain electrode 7 are respectively arranged on the surfaces of the source electrode cap layer 4 and the drain electrode cap layer 5, a gate electrode 8 is formed on one side, close to the source electrode, above the N-type channel layer 3, wherein the gate-source interval is 0.5 mu m, the gate-drain interval is 1.0 mu m, the gate length is 0.7 mu m, a lightly doped region 9 is arranged between the gate and the source electrode, a heavily doped region 10 of a partial sinking channel is arranged below the lightly doped region, and a piece of silicon nitride (Si) is arranged between the lower part of the high gate and the drain electrode₃N₄) An insulating region 11 of material.

In this embodiment, the lightly doped region 9 has a height of 0.15 μm, a width of 0.5 μm, and a doping concentration of 1 × 10¹⁷cm^-3(ii) a The heavily doped region 10 of the partial sinking channel has a height of 0.2 μm, a width of 0.5 μm and a doping concentration of 1 × 10²⁰cm^-3(ii) a The height of the insulating region 11 is 0.05 μm, and the width is 1.5 μm.

Under the same simulation environment and the same simulation condition (V)_gs＝0V，V_ds40V), 4H-SiC mosfet with partial sinking channel, conventional double-recessed gate structure (L) for example 1_GS＝0.5μm，L＝0.7μm，L_ds1.0 μm, L0 ═ 0.35 μm, H1 ═ 0.3 μm, H2 ═ 0.25 μm, and H3 ═ 0.20 μm), and CN105118867A disclose 4H-SiC metal-semiconductor field effect transistors having a partially sinking channel, the simulation results are shown in the following table:

	double-concave grid structure	CN105118867A	Example 1
				Saturation current	449.5mA/mm	525.6mA/mm	603.6mA/mm
Breakdown voltage	110.8V	130.6V	162.2V
				Transconductance	61.1mS/mm	59.7mS/mm	66.5mS/mm

As can be seen from the data in the above table, CN105118867A sinks the whole channel from the gate to the drain on the basis of the double-recessed gate structure, so that the saturation current and the breakdown voltage of the device are improved to a certain extent, but some adverse effects are brought to the transconductance of the device, and the transconductance of the device is slightly reduced; the structure of the invention further improves the saturation current and breakdown voltage of the device, and eliminates the adverse effect on transconductance, so that the transconductance of the device is improved, and higher power added efficiency is obtained.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.