阅读说明：本技术 一种peci总线扩展方法及系统 (PECI bus expansion method and system ) 是由 张帆 李传宝 于 2020-04-30 设计创作，主要内容包括：本发明公开了一种PECI总线扩展方法及系统,涉及PECI总线扩展领域,该方法包括第一转换设备将PECI芯片的GTL信号转换为LVDS信号。将所述LVDS信号传输至远端的第二转换设备,并在第二转换设备将所述LVDS信号转化为所述GTL信号,并提供给各个远端被管理器件。所述被管理器件发出GTL信号至第二转换设备,所述第二转换设备将该GTL信号转化为LVDS信号。将所述LVDS信号传输至第一转换设备,由第一转换设备将所述LVDS信号转化为GTL信号并提供给PECI芯片。本发明能够满足PECI线路远距离、复杂环境的应用场景需求。(The invention discloses a PECI bus expansion method and system, and relates to the field of PECI bus expansion. And transmitting the LVDS signals to a second conversion device at a far end, converting the LVDS signals into GTL signals at the second conversion device, and providing the GTL signals to each far-end managed device. The managed device sends a GTL signal to a second conversion device, and the second conversion device converts the GTL signal into an LVDS signal. And transmitting the LVDS signals to a first conversion device, converting the LVDS signals into GTL signals by the first conversion device and supplying the GTL signals to a PECI chip. The invention can meet the application scene requirements of the PECI circuit in a long distance and complex environment.)

1. A PECI bus expansion method, comprising:

the first conversion equipment converts the GTL signal of the PECI chip into an LVDS signal;

transmitting the LVDS signals to a second conversion device at a far end, converting the LVDS signals into GTL signals at the second conversion device, and providing the GTL signals to each far-end managed device;

the managed device sends a GTL signal to a second conversion device, and the second conversion device converts the GTL signal into an LVDS signal;

and transmitting the LVDS signals to a first conversion device, converting the LVDS signals into GTL signals by the first conversion device and supplying the GTL signals to a PECI chip.

2. The PECI bus expansion method of claim 1,

the converting the GTL signal into an LVDS signal specifically includes:

acquiring a GTL signal of the PECI chip, and inputting the GTL signal into a GTL-TTL conversion circuit to obtain a TTL signal;

and inputting the TTL signal into a TTL-LVDS conversion circuit to obtain an LVDS signal.

3. A PECI bus extension method according to claim 1 or 2, characterized in that:

the first conversion equipment and the second conversion equipment have the same circuit structure.

4. A PECI bus expansion circuit, characterized in that: comprising a first conversion device and a second conversion device,

the first conversion equipment converts the GTL signal of the PECI chip into an LVDS signal;

the second conversion equipment receives LVDS signals at a far end, converts the LVDS signals into GTL signals and provides the GTL signals to each far-end managed device;

the managed device sends a GTL signal to a second conversion device, and the second conversion device converts the GTL signal into an LVDS signal;

the first conversion device receives an LVDS signal, converts the LVDS signal into a GTL signal and provides the GTL signal to the PECI chip.

5. The PECI bus extension method of claim 4, wherein: a first conversion device including a GTL-TLL conversion circuit and a TTL-LVDS conversion circuit,

the GTL-TLL conversion circuit is used for acquiring a GTL signal of the PECI chip and converting the GTL signal into a TTL signal;

the TTL-LVDS conversion circuit is used for obtaining TTL signals and converting the TTL signals into LVDS signals.

6. The PECI bus extension method of claim 4 or 5, wherein: the first conversion equipment and the second conversion equipment are identical in structure.

7. The PECI bus expansion circuit of claim 5, wherein:

the GTL-TLL conversion circuit comprises a first mos tube M1, a second mos tube M2 and a third mos tube M3;

the source stage of M1 is used as an SREF interface, the drain stage is used as a DREF interface, the gate stage is connected with the gate of M2 and the gate of M3 to be used as a GREF interface, the source stage of M2 is used as an S1 interface, the drain stage is used as a D1 interface, the source stage of M3 is used as an S2 interface, the drain stage is used as a D2 interface, the SREF interface is connected with a GLT signal, the DREF and the GREF are connected with the 3.3V reference level of TTL, the returned TTL signals are received by D1 and D2, and GTL signals are sent to a PECI chip through S1 and S2;

when TTL signals are accessed to the D1 interface and the D2 interface, the S1 interface is an output interface for outputting signals by the PECI;

when the interface S2 is connected to the PECI input signal, the interface D1 and the interface D2 are TTL level output ends.

8. The PECI bus expansion circuit of claim 5 or 7, wherein:

the TLL-LVDS conversion circuit includes: the device comprises a single-ended signal to differential signal device and a differential signal to single-ended signal device;

the input end of the single-ended signal to differential signal conversion device is used as the first end of the TLL-LVDS conversion circuit, the output end of the differential signal to single-ended signal conversion device is used as the second end of the TLL-LVDS conversion circuit, and the output end of the single-ended signal to differential signal conversion device is connected with the output end of the differential signal to single-ended signal conversion device to be used as the third end;

the first end and the second end are input and output ends of TTL signals, and the third end is an input and output end of LVDS signals.

9. The PECI bus expansion circuit of claim 8, wherein:

the PECI neutral line extension circuit specifically comprises:

the input end of the PECI chip is connected with the SREF interface of the GTL-TLL conversion circuit, the output end of the PECI chip is connected with the S1 and S2 interfaces of the GTL-TLL conversion circuit, the DREF interface, the GREF interface, the other end of the grounding capacitor and one end of the first resistor are connected, the other end of the first resistor is connected with one end of the second resistor, one end of the third resistor and the 3.3v power supply, the other end of the second resistor is connected with the first end of the TLL-LVDS conversion circuit and the D1 interface of the GTL-TLL conversion circuit, and the other end of the third resistor is connected with the second end of the TLL-LVDS conversion circuit and the D2 interface of the GTL-TLL conversion circuit.

10. The PECI bus expansion circuit of claim 1, wherein: and each remote managed device is connected in parallel and is respectively connected with a second conversion device.

Technical Field

The invention relates to the field of PECI bus expansion, in particular to a PECI bus expansion method and system.

Background

The rack server is a high-performance general-purpose computer, which is used as an important node of a network to store and process data or information on the network. With the rapid development of cloud computing, big data, mobile internet and internet of things, the challenges of massive data, diversification and information service and complex data aggregation and interaction capacity are brought, and under the driving of a fusion architecture of 'hardware reconstruction + software definition + network function virtualization', the demands on servers are more urgent and diversified no matter in an internet data center, an enterprise-level data center or a telecommunication network infrastructure.

The PECI bus is an important management bus in the server, and connects the management chip in the server with the CPU, PCH or other peripherals, so as to implement the functions of temperature management, power consumption management, system error monitoring, regulation and diagnosis, etc. of these chips.

With the increasing complexity of server design, the size of the server motherboard increases, resulting in the increase of the wiring length of the PECI. And the number of modules and chips to be monitored in the server is continuously increasing, resulting in an increase in the number of devices on which the PECI bus is hung. Meanwhile, in high density, a multi-node server needs to introduce cross-board connection and a split board connector. These all have an impact on the stability and transmission reliability of the PECI bus. Due to the limitation of the PECI line, the transmission of PECI signals in a complex environment cannot be carried out, so that the design of the server is limited. The requirements of complex application scenes cannot be met.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a PECI bus expansion method and system, which can meet the application scene requirements of a PECI line in a long distance and a complex environment.

To achieve the above object, in a first aspect, an embodiment of the present invention provides a PECI bus extension method, which includes:

the first conversion equipment converts the GTL signal of the PECI chip into an LVDS signal;

transmitting the LVDS signals to a second conversion device at a far end, converting the LVDS signals into GTL signals at the second conversion device, and providing the GTL signals to each far-end managed device;

the managed device sends a GTL signal to a second conversion device, and the second conversion device converts the GTL signal into an LVDS signal;

and transmitting the LVDS signals to a first conversion device, converting the LVDS signals into GTL signals by the first conversion device and supplying the GTL signals to a PECI chip.

As a preferred embodiment, the converting the GTL signal into the LVDS signal includes:

acquiring a GTL signal of the PECI chip, and inputting the GTL signal into a GTL-TTL conversion circuit to obtain a TTL signal;

and inputting the TTL signal into a TTL-LVDS conversion circuit to obtain an LVDS signal.

As a preferred embodiment, the first conversion device and the second conversion device have the same circuit structure.

In a second aspect, an embodiment of the present invention further provides a PECI bus extension circuit, which includes a first conversion device and a second conversion device,

the first conversion equipment converts the GTL signal of the PECI chip into an LVDS signal;

the second conversion equipment receives LVDS signals at a far end, converts the LVDS signals into GTL signals and provides the GTL signals to each far-end managed device;

the managed device sends a GTL signal to a second conversion device, and the second conversion device converts the GTL signal into an LVDS signal;

the first conversion device receives an LVDS signal, converts the LVDS signal into a GTL signal and provides the GTL signal to the PECI chip.

In a preferred embodiment, the first conversion device comprises a GTL-TLL conversion circuit and a TTL-LVDS conversion circuit,

the GTL-TLL conversion circuit is used for acquiring a GTL signal of the PECI chip and converting the GTL signal into a TTL signal;

the TTL-LVDS conversion circuit is used for obtaining TTL signals and converting the TTL signals into LVDS signals.

As a preferred embodiment, the first converting device is identical in structure to the second converting device.

As a preferred embodiment, the GTL-TLL conversion circuit includes a first mos transistor M1, a second mos transistor M2, and a third mos transistor M3;

the source stage of M1 is used as an SREF interface, the drain stage is used as a DREF interface, the gate stage is explained with the gate of M2 and the gate of M3 in detail and is used as a GREF interface, the source stage of M2 is used as an S1 interface, the drain stage is used as a D1 interface, the source stage of M3 is used as an S2 interface, the drain stage is used as a D2 interface, the SREF interface is connected with a GLT signal, the DREF and GREF are connected with a 3.3V reference level of TTL, the D1 and D2 receive returned TTL signals, and GTL signals are sent to a PECI chip through S1 and S2;

when TTL signals are accessed to the D1 interface and the D2 interface, the S1 interface is an output interface for outputting signals by the PECI;

when the interface S2 is connected to the PECI input signal, the interface D1 and the interface D2 are TTL level output ends.

As a preferred embodiment, the TLL-LVDS conversion circuit includes: the device comprises a single-ended signal to differential signal device and a differential signal to single-ended signal device;

the input end of the single-ended signal to differential signal conversion device is used as the first end of the TLL-LVDS conversion circuit, the output end of the differential signal to single-ended signal conversion device is used as the second end of the TLL-LVDS conversion circuit, and the output end of the single-ended signal to differential signal conversion device is connected with the output end of the differential signal to single-ended signal conversion device to be used as the third end;

the first end and the second end are input and output ends of TTL signals, and the third end is an input and output end of LVDS signals.

As a preferred embodiment, the PECI neutral line extension circuit specifically includes:

the input end of the PECI chip is connected with the SREF interface of the GTL-TLL conversion circuit, the output end of the PECI chip is connected with the S1 and S2 interfaces of the GTL-TLL conversion circuit, the DREF interface, the GREF interface, the other end of the grounding capacitor and one end of the first resistor are connected, the other end of the first resistor is connected with one end of the second resistor, one end of the third resistor and the 3.3v power supply, the other end of the second resistor is connected with the first end of the TLL-LVDS conversion circuit and the D1 interface of the GTL-TLL conversion circuit, and the other end of the third resistor is connected with the second end of the TLL-LVDS conversion circuit and the D2 interface of the GTL-TLL conversion circuit.

In a preferred embodiment, each of the remote managed devices is connected in parallel and is connected to a second switching device.

Compared with the prior art, the invention has the advantages that:

according to the PECI bus expansion method and system, the first conversion equipment is used for converting the GTL signal into the LVDS signal, so that information sent by the PECI bus can be transmitted to a far place to reach a far managed device position depending on the characteristics of the LVDS signal. Further, the second conversion device further converts the transmitted LVDS signal into a GTL signal, so that the information sent by the PECI is sent to the managed device in a form understandable by the managed device. Furthermore, the PECI signal returned by the managed device passes through the second conversion device again to become an LVDS signal, and is transmitted to the first conversion device to be converted into a PEIC signal, and the PEIC signal is provided to the PECI chip, so that the communication of the PECI chip to the remote managed device is realized. This communication has many advantages: the transmission distance is long, the power consumption is low, the error rate is low, the crosstalk is less, and the radiation is low.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings corresponding to the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a flowchart illustrating steps of a PECI bus expansion method according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of an embodiment of a PCI bus expansion system according to the present invention;

FIG. 3 is a schematic diagram of a GTL-TLL conversion circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a GTL-LVDS conversion circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an embodiment of a PECI bus extension system according to the present invention.

Detailed Description

Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

The embodiment of the invention provides a PECI bus expansion method and system, which can realize stable, safe and efficient communication between a PECI chip and a device at a far position through the conversion of a PECI signal and an LVDS signal.

In order to achieve the technical effects, the general idea of the application is as follows:

the first conversion equipment converts the GTL signal of the PECI chip into an LVDS signal;

transmitting the LVDS signals to a second conversion device at a far end, converting the LVDS signals into GTL signals at the second conversion device, and providing the GTL signals to each far-end managed device;

the managed device sends a GTL signal to a second conversion device, and the second conversion device converts the GTL signal into an LVDS signal;

and transmitting the LVDS signals to a first conversion device, converting the LVDS signals into GTL signals by the first conversion device and supplying the GTL signals to a PECI chip.

In summary, the invention converts the GTL signal which cannot be transmitted remotely into the LVDS signal which can be transmitted remotely through the first conversion device, thereby implementing remote transmission of information sent by the PECI chip; in order to enable the remote managed device to understand the information, the second conversion device further speaks an LVDS signal to convert into a GTL signal and provides the GTL signal to the managed device, and the inquiry from the PECI chip to the remote managed device is realized; further, the remote managed device feeds back the information, converts the information from the GTL signal to the LVDS signal by the second conversion device, and transmits the LVDS signal to the first conversion device, and the first conversion device converts the LVDS signal into the GTL signal and transmits the GTL signal to the PECI chip, thereby finally completing the communication of the PECI chip to the remote managed device.

In order to better understand the technical solution, the following detailed description is made with reference to specific embodiments.

Referring to fig. 1, an embodiment of the present invention provides a PECI bus expansion method, which includes:

s1: the first conversion device converts the GTL signal of the PECI chip into an LVDS signal.

The GTL signal of PECI is an important management signal in the server, which communicates the management chip in the server with the CPU, PCH or other peripherals to implement the functions of temperature management, power consumption management, system error monitoring, regulation and diagnosis, etc. of these chips. However, the PECI requires a large number of devices to be mounted, and has high density, and GTL signals are very vulnerable to transmission in a remote environment. Therefore, the GTL signal needs to be converted into an LVDS signal before transmission.

S2: and transmitting the LVDS signals to a second conversion device at a far end, converting the LVDS signals into GTL signals at the second conversion device, and providing the GTL signals to each far-end managed device.

The LVDS signal is a low-amplitude differential signal. It uses a very low amplitude signal (about 350mV) to transmit data through a pair of differential PCB traces or balanced cables. It can transfer serial data at speeds up to thousands of Mbps. Because the voltage signal amplitude is lower and the constant current source mode is adopted for driving, only extremely low noise is generated, very small power is consumed, and even the power consumption is almost unchanged no matter the frequency is high or low. Furthermore, since LVDS transmits data in a differential manner, it is less susceptible to common mode noise

Therefore, after the GTL signal is converted into the LVDS signal, the GTL signal is transmitted through the LVDS, so that the influence of the transmission process is avoided, and since the signal required by the remote managed device is the GTL signal, the second conversion device is arranged in front of the remote managed device, and the transmitted LVDS signal is converted into the GTL signal and then provided to the remote managed device.

As a preferred embodiment, the converting the GTL signal into the LVDS signal includes:

acquiring a GTL signal of the PECI chip, and inputting the GTL signal into a GTL-TTL conversion circuit to obtain a TTL signal;

and inputting the TTL signal into a TTL-LVDS conversion circuit to obtain an LVDS signal.

According to the invention, the TTL signal is arranged between the GTL signal and the LVDS signal, so that the conversion from the GTL signal to the LVDS signal is realized. Firstly, GLT is converted into TTL and then TTL is converted into LVDS.

S3: the managed device sends a GTL signal to a second conversion device, and the second conversion device converts the GTL signal into an LVDS signal.

After receiving the management signal of the PECI, the remote managed device needs to perform feedback, so the invention preferably selects that the remote managed signal passes through the second conversion device again to convert the GTL signal fed back by the remote managed device into the LVDS signal.

S4: and transmitting the LVDS signals to a first conversion device, converting the LVDS signals into GTL signals by the first conversion device and supplying the GTL signals to a PECI chip.

Therefore, the LVDS signal sent from the remote managed device via the second conversion device is preferably converted into a GTL signal by the first conversion device, and then provided to the PECI chip.

Preferably, the first conversion device and the second conversion device have the same circuit structure. The first conversion device and the second conversion device realize the mutual conversion between the LVDS and the GTL, and therefore, the same circuit structures can be respectively arranged in front of the PECI chip and the remote managed device to serve as the first conversion device and the second conversion device.

As shown in fig. 2, an embodiment of the present invention further provides a PECI bus expansion circuit, which includes a first conversion device and a second conversion device:

the first conversion equipment converts the GTL signal of the PECI chip into an LVDS signal;

the second conversion equipment receives LVDS signals at a far end, converts the LVDS signals into GTL signals and provides the GTL signals to each far-end managed device;

the managed device sends a GTL signal to a second conversion device, and the second conversion device converts the GTL signal into an LVDS signal;

the first conversion device receives an LVDS signal, converts the LVDS signal into a GTL signal and provides the GTL signal to the PECI chip.

The first conversion device is responsible for the conversion of the PECI chip receiving and sending signals, the PECI is guaranteed to ensure that the chip only receives and sends GTL signals, and the signals transmitted or received by the first conversion device are LVDS signals, so that the anti-interference performance and the safety of information are guaranteed.

The second conversion device is responsible for the conversion of the remote managed device transmitting and receiving signals, so as to ensure that the remote managed device can receive the GTL signal and send the GTL signal to receive the management of the PECI chip. And the second switching device is responsible for completing the conversion of the GTL signal and the LVDS signal and communicating with the first conversion through the LVDS.

Since the first conversion device and the second conversion device complete the conversion from the GTL signal to the LVDS signal and from the LVDS signal to the GLT signal, the first conversion device and the second conversion device are preferably identical in structure.

Preferably, the first conversion device comprises a GTL-TLL conversion circuit and a TTL-LVDS conversion circuit,

the GTL-TLL conversion circuit is used for acquiring a GTL signal of the PECI chip and converting the GTL signal into a TTL signal;

the TTL-LVDS conversion circuit is used for obtaining TTL signals and converting the TTL signals into LVDS signals.

And the conversion from the GTL signal to the TLL signal and then to the LVDS signal and the conversion from the LVDS signal to the TLL signal and then to the GTL signal are completed by taking the TLL signal as an intermediate signal.

For example, as shown in fig. 3, the GTL-TLL conversion circuit includes a first mos transistor M1, a second mos transistor M2, and a third mos transistor M3;

the source stage of M1 is used as an SREF interface, the drain stage is used as a DREF interface, the gate stage is explained with the gate of M2 and the gate of M3 in detail and is used as a GREF interface, the source stage of M2 is used as an S1 interface, the drain stage is used as a D1 interface, the source stage of M3 is used as an S2 interface, the drain stage is used as a D2 interface, the SREF interface is connected with a GLT signal, the DREF and GREF are connected with a 3.3V reference level of TTL, the D1 and D2 receive returned TTL signals, and GTL signals are sent to a PECI chip through S1 and S2;

when TTL signals are accessed to the D1 interface and the D2 interface, the S1 interface is an output interface for outputting signals by the PECI;

when the interface S2 is connected to the PECI input signal, the interface D1 and the interface D2 are TTL level output ends.

When the GTL-TTL conversion circuit works, SREF, GREF and DREF are respectively used as reference voltage input pins, the SREF is connected with a 1V reference level of GTL, and the DREF and the GREF are connected with a 3.3V reference level of TTL. When S1 is 1V, the corresponding level of D1 is 3.3V, and when S1 is 0V, the corresponding level of D1 is 0V. In the same way, when the D1 level is 3.3V, the S1 corresponding level is 1V, and when the D1 level is 0V, the S1 corresponding level is 0V. And the conversion function of the S1, D11V level and the 3.3V level on two sides of the circuit is realized.

The invention divides the original single path of bidirectional communication into two paths of unidirectional communication, simultaneously realizes the conversion of GTL level and differential TTL level, solves the problems of poor anti-interference capability and poor expansion performance of GTL in the transmission process, and further enables PECI communication among a plurality of devices to be possible.

Further, the TLL-LVDS conversion circuit includes: the device comprises a single-ended signal to differential signal device and a differential signal to single-ended signal device;

the input end of the single-ended signal to differential signal conversion device is used as the first end of the TLL-LVDS conversion circuit, the output end of the differential signal to single-ended signal conversion device is used as the second end of the TLL-LVDS conversion circuit, and the output end of the single-ended signal to differential signal conversion device is connected with the output end of the differential signal to single-ended signal conversion device to be used as the third end;

the first end and the second end are input and output ends of TTL signals, and the third end is an input and output end of LVDS signals.

Combining the above examples, a first/second switching device as described in fig. 4 can be obtained:

the PECI neutral line extension circuit specifically comprises:

the input end of the PECI chip is connected with the SREF interface of the GTL-TLL conversion circuit, the output end of the PECI chip is connected with the S1 and S2 interfaces of the GTL-TLL conversion circuit, the DREF interface, the GREF interface, the other end of the grounding capacitor and one end of the first resistor are connected, the other end of the first resistor is connected with one end of the second resistor, one end of the third resistor and the 3.3v power supply, the other end of the second resistor is connected with the first end of the TLL-LVDS conversion circuit and the D1 interface of the GTL-TLL conversion circuit, and the other end of the third resistor is connected with the second end of the TLL-LVDS conversion circuit and the D2 interface of the GTL-TLL conversion circuit.

The original bidirectional communication bus is divided into two unidirectional communication lines, S1 is a PECI output signal, and S2 is a PECI input signal pin. And after M1 level conversion, converting the 2-path GTL level into the 2-path TTL level, wherein G is the output level of TTL, and H is the input level of TTL. G is converted into differential signals A and B through single-end to differential circuits D and R to be output. Meanwhile, the output differential signals A and B can be converted into single-ended signals R to be used as D2 input of the GTL-TTL level conversion module M1. D2 is level-converted to the S2 input of M2, thereby implementing GTL to LVDS bi-directional conversion.

Further, as shown in fig. 5, each of the remote managed devices is connected in parallel and is connected to a second switching device.

The parallel connection realizes the PECI bus communication among a plurality of devices and realizes the long-distance transmission of PECI signals across connectors. Support is provided for internal communication of high-end complex servers. For example, in the gateway, a plurality of devices on a plurality of boards are communicated and managed through LVDS signals.

Generally, the method and the system for expanding the PECI bus provided by the embodiment of the invention can meet the application scene requirements of the PECI line in a long distance and complex environment.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.