阅读说明：本技术 一种用于物联网安全芯片中非挥发性存储器的低功耗电荷泵电路及工作方法 (Low-power-consumption charge pump circuit for non-volatile memory in Internet of things security chip and working method ) 是由 高彬 王丹 李向宏 徐灿 李自强 朱兰 尚方建 于 2021-09-28 设计创作，主要内容包括：一种用于物联网安全芯片中非挥发性存储器的低功耗电荷泵电路,通过加入电压检测电路,可以使得物联网安全芯片中使用的非挥发性存储器电荷泵电路在生成编程所需电压之后,通过改变控制信号Vdet的逻辑,使得升压电荷泵Charge Pump的输入时钟频率从振荡器OSC输出clk的频率,降低为原来的1/N；由于占非挥发性存储器电荷泵电路主要功耗的升压电荷泵Charge Pump的动态功耗正比于CfV～(2),降低频率f即可以实现降低非挥发性存储器电荷泵电路的动态功耗,由此可实现在VPP端编程电压达到设定值后,升压电荷泵Charge Pump的动态功耗降低为原来的1/N。(A low-power-consumption Charge Pump circuit for a nonvolatile memory in an Internet of things security chip is characterized in that a voltage detection circuit is added, so that after the nonvolatile memory Charge Pump circuit used in the Internet of things security chip generates a voltage required by programming, the logic of a control signal Vset is changed, the frequency of an input clock of a boost Charge Pump is reduced to 1/N of the original frequency of clk output from an oscillator OSC; the dynamic power consumption of the boosted Charge Pump Charge Pump, which dominates the power consumption of the non-volatile memory Charge Pump Circuit, is proportional to CfV 2 And the dynamic power consumption of the Charge Pump circuit of the nonvolatile memory can be reduced by reducing the frequency f, so that the dynamic power consumption of the Charge Pump can be reduced to 1/N after the VPP end programming voltage reaches a set value.)

1. A low-power-consumption charge pump circuit for a non-volatile memory in a security chip of the Internet of things comprises: the low power consumption Charge Pump circuit comprises an oscillator OSC, a Non-overlapping clock generator Non Overlap, a boost Charge Pump, a voltage stabilizing Diode Zener Diode and a voltage stabilizing capacitor, and is characterized by further comprising: a Voltage Detector is arranged in parallel at the output end of the boost Charge Pump, and a frequency division circuit DIV is additionally arranged between an oscillator OSC and a Non-overlapping clock generator Non Overlap;

the Voltage Detector is used for: detecting that a programming voltage generated by a charge pump circuit, namely a VPP terminal voltage reaches a voltage required by programming of a nonvolatile memory:

when the Voltage of the VPP terminal is lower than the Voltage required by programming the nonvolatile memory, the output end Vset of the Voltage Detector is from logic 0 to a frequency dividing circuit DIV;

when the Voltage at the VPP end is higher than the Voltage required by programming the non-volatile memory, the output end Vset of the Voltage Detector is from logic 1 to a frequency divider DIV;

the frequency divider circuit DIV is configured to: the input clock clk is divided by an integer, and a clk _ DIV signal is output after the division, and the Voltage division circuit DIV is controlled by an output signal Vdet of a Voltage Detector.

2. The charge pump circuit with low power consumption for the non-volatile memory in the security chip of the internet of things of claim 1, wherein the frequency dividing circuit DIV divides the input clock clk by an integer, the dividing ratio in the default state is 1, that is, the frequency division is not performed, and the frequency of the output clk _ DIV clock signal is the same as that of the input clk clock signal; the frequency division of 2 is that the frequency of the output clk _ div clock signal is half of the frequency of the input clk clock signal; the N-division outputs a clk _ div clock signal at 1/N of the input clk clock signal.

3. The operation method of the low power consumption charge pump circuit according to claim 1 or 2, characterized in that: in the programming process of a non-volatile memory in a security chip of the internet of things, in the process of generating programming Voltage by a charge pump circuit, when the Voltage of a VPP end does not reach the Voltage required by the programming of the non-volatile memory in the climbing process, the output Vset of a Voltage Detector of a Voltage detection circuit is logic 0, the frequency dividing ratio of a frequency dividing circuit DIV is 1, namely the frequency of an output clk _ DIV clock signal is the same as the frequency of an input clk clock signal;

when the Voltage at the VPP terminal reaches the Voltage required by programming the nonvolatile memory, the Voltage Detector of the Voltage detection circuit outputs Vset to be logic 1, the frequency division circuit DIV is controlled by the Vset signal, and the clk _ DIV clock signal output by the frequency division circuit DIV is reduced to 1/N of the clk clock signal output by the oscillator.

Technical Field

The invention relates to a low-power-consumption charge pump circuit for a non-volatile memory in an Internet of things security chip and a working method, and belongs to the technical field of Internet of things security chips.

Background

With the development of the application of the Internet of things in China, the safety of the Internet of things receives more and more attention. The internet of things security chip is used as an important component for protecting information acquisition, storage and transmission security in the application of the internet of things, and is also rapidly developed and applied. An important application field of the internet of things security chip is a Radio Frequency Identification (RFID) system, which performs non-contact bidirectional data communication in a radio frequency manner, and reads and writes a recording medium (a radio frequency tag or a radio frequency card, etc.) in the radio frequency manner, so as to achieve the purposes of identifying a target and exchanging data. The low power consumption design and the non-volatile memory design for storing data are important design links of the Internet of things security chip.

The complete RFID system is shown in figure 1 and consists of an RFID card reader, an RFID chip and a background software system. The working principle is that the background software system controls the RFID card reader to transmit a radio signal with a certain frequency to the RFID chip so as to read data stored in the electronic tag. After receiving the signal sent by the RFID card reader, the RFID chip reads out the stored data of the RFID chip and returns the data to the RFID card reader by generating a radio signal with the same frequency. And the RFID card reader puts the data into a background software system for processing after obtaining the returned data so as to identify the correctness of the label.

The structure of the radio frequency identification tag is shown in figure 2, and mainly comprises a coupling coil 01, an RF circuit 02, a rectifying circuit 03, an encryption module 04, a random access memory RAM05, a read-only memory ROM06, an electrically programmable read-only memory EEPROM07 and a central processing unit CPU 08. Wherein:

the coupling coil 01 has a function of receiving a radio signal transmitted from an RFID reader or transmitting a radio signal to the RFID reader.

The RF circuit 02 functions to convert a radio signal received by the coupling coil into a digital signal recognizable by the cpu or convert a digital signal sent from the cpu into a radio signal and send the radio signal to the coupling coil for transmission.

The rectifier circuit 03 has a function of converting a received radio signal into a power supply for the RFID chip through rectification and supplying power to the entire tag.

The encryption module 04 has the functions of encrypting and decrypting data and ensuring the security of processed information, and is called by the central processing unit CPU 08.

The RAM05 is the system memory used by the CPU 08.

The fixed data written by the tag according to the customer requirement before leaving the factory is placed in the read-only memory ROM06, and can only be read by the central processing unit CPU08, and the data content cannot be changed.

The data stored in the non-volatile memory 07 is data written or modified by the user according to the user's needs, wherein the data can be erased or written according to the instructions, and the central processing unit CPU08 can read or modify the data stored therein.

The central processing unit CPU08 is responsible for scheduling the use and operation of each module in the RFID chip, which is the brain of the entire RFID chip.

The non-volatile memory used in the RFID chip is a programmable memory which can be modified by electric signals, and mainly comprises: the electrically programmable read-only memory EEPROM and Flash memory Flash can keep data from losing after power failure, and has the characteristics of high programming speed, strong reliability, long service life and the like.

The non-volatile memory used in the RFID chip stores electrons in the floating gate of the MOS tube, and the electrons on the floating gate in the MOS tube can be kept after the chip is powered off, so that the storage and the storage of data are realized. The attraction of electrons to the floating gate of the MOS transistor or the elimination of electrons from the floating gate of the MOS transistor needs a high voltage, that is, the EEPROM needs 15.5V voltage, and the Flash needs 10V voltage. However, in order to realize low power consumption, the voltage of the RFID tag is generally only 1.8V, even 1.2V or 1V, and therefore, the implementation of this high voltage needs to be realized by using a boost charge pump circuit, Chargepump.

The basic principle of the boost charge pump circuit is shown in fig. 3: the circuit comprises a charging and discharging capacitor C, switches S1, S2, S3 and S4. When the phi 1 is a high level phi 2 and a low level phi 2, the voltage at two ends of the charge and discharge capacitor is VDD, that is, V + is VDD, and V ═ 0V; when Φ 2 is high Φ 1 is low, V-is connected to the VDD terminal, V + is connected to the output terminal Vout, and at this time, the voltage V-is VDD, and since the charge at both ends of the capacitor cannot change abruptly, the difference between the voltages of V + and V-is not VDD, the voltage of V + is 2 times VDD at this time, thereby boosting the voltage. Continued boosting of the voltage can be achieved using a series connection of a plurality of boost charge pump circuits as shown in fig. 3.

The charge pump circuit for generating the programming voltage by the non-volatile memory used in the internet of things security chip is shown in fig. 4: including an oscillator 10(OSC), a Non-Overlap clock generator 20(Non Overlap), a boost Charge Pump 30(Charge Pump), a Zener Diode 40(Zener Diode) and a Zener capacitor 50, the basic principles are as follows: the oscillator 10 outputs a clock signal clk with a certain frequency, the non-overlapping clock generator 20 converts the input clk signal into two non-overlapping clock signals clka and clkb, the boost charge pump circuit 30 raises the power supply voltage VDD to a voltage higher than the programming high voltage VPP of the non-volatile memory under the control of the non-overlapping clock signals clka and clkb, the programming high voltage VPP is limited within a voltage range (15.5V or 10V) required for programming the non-volatile memory by the zener diode 40, and the programming voltage is stabilized during the programming process of the zener capacitor 50. The voltage stabilizing diode is a semiconductor device with high resistance until the critical reverse breakdown voltage, when the voltage applied to the two ends of the voltage stabilizing diode is higher than the conducting voltage of the voltage stabilizing diode, the voltage stabilizing diode is conducted, redundant charges can be discharged through the voltage stabilizing diode, and therefore the voltage at the two ends of the voltage stabilizing diode is kept at a certain voltage.

Fig. 5 shows a working waveform diagram of a nonvolatile memory charge pump circuit used in the internet-of-things security chip shown in fig. 4 for generating a programming voltage, after the charge pump circuit starts to work, a boost charge pump 30 gradually raises a VPP terminal voltage under the control of a non-overlapping clock, after a boost time T1, the VPP terminal voltage of the charge pump circuit reaches a voltage required for programming the nonvolatile memory, at this time, the VPP terminal voltage is stabilized by a voltage stabilizing capacitor 50 of a voltage stabilizing diode 40, excessive charges of the VPP terminal are discharged through the voltage stabilizing diode 40, the VPP terminal voltage is stabilized at a voltage (15.5V or 10V) required for programming the nonvolatile memory, the time T2 required for programming is kept, after the programming of the nonvolatile memory is finished, the charge pump circuit is turned off, and the VPP terminal programming voltage is discharged. Generally, the time T2 required for programming is much longer than the boosting time T1 and the drain time of the VPP programming voltage, which is the main generation time of the programming power consumption of the non-volatile memory.

Because the application environment of the internet of things security chip is mainly portable and miniaturized, the internet of things security chip is usually powered by a battery or remotely wirelessly coupled, and belongs to a low-power-consumption application environment, the low-power-consumption design of the internet of things security chip is one of the most important links. When the non-volatile memory of the internet-of-things security chip is programmed, a boost circuit is required to generate high voltage required by programming, so that large power consumption is generated, and the part of power consumption comprises dynamic power consumption of a clock generated by the oscillator 10, dynamic power consumption of the non-overlapping clock circuit 20, dynamic power consumption of the boost charge pump and the like.

Therefore, how to optimize the dynamic power consumption of the boost charge pump in the nonvolatile memory during the operation is an urgent technical problem to be solved for reducing the low power consumption of the nonvolatile memory.

Disclosure of Invention

Aiming at the defects of the prior art, the invention discloses a low-power-consumption charge pump circuit for a non-volatile memory in a security chip of the Internet of things.

The invention also discloses a working method of the low-power-consumption charge pump circuit.

Summary of the invention:

due to the fact that the booster circuit willThe VPP terminal voltage is increased by charging step by step, and when the voltage generated by the VPP terminal of the boosting charge pump 30 exceeds the voltage 15.5V or 10V required by the non-volatile memory for programming, the redundant charge is discharged through the voltage stabilizing diode 40, so that the main power consumption of the non-volatile memory programming process is from the dynamic power consumption of the boosting charge pump 30, including the redundant charge discharged by the voltage stabilizing diode 40 and generated by the boosting charge pump 30. The boost charge pump 30 dynamic power consumption is about CfV²Where C is the sum of the capacitances of each stage in the boost charge pump, f is the clock frequency at which the boost charge pump 30 operates, and V is the supply voltage for the charge pump circuit 30.

The detailed technical scheme of the invention is as follows:

a low-power-consumption charge pump circuit for a non-volatile memory in a security chip of the Internet of things comprises: the low power consumption Charge Pump circuit comprises an oscillator OSC, a Non-overlapping clock generator Non Overlap, a boost Charge Pump, a voltage stabilizing Diode Zener Diode and a voltage stabilizing capacitor, and is characterized by further comprising: a Voltage Detector is arranged in parallel at the output end of the boost Charge Pump, and a frequency division circuit DIV is additionally arranged between an oscillator OSC and a Non-overlapping clock generator Non Overlap;

the Voltage Detector is used for: detecting whether a programming voltage generated by the charge pump circuit, namely a VPP terminal voltage reaches 15.5V or 10V required by the programming of the nonvolatile memory:

when the Voltage of the VPP terminal is lower than the Voltage required by programming the nonvolatile memory, the output end Vset of the Voltage Detector is from logic 0 to a frequency dividing circuit DIV;

when the Voltage at the VPP end is higher than the Voltage required by programming the non-volatile memory, the output end Vset of the Voltage Detector is from logic 1 to a frequency divider DIV;

the frequency divider circuit DIV is configured to: the input clock clk is divided by an integer, and a clk _ DIV signal is output after the division, and the Voltage division circuit DIV is controlled by an output signal Vdet of a Voltage Detector.

According to the present invention, preferably, the frequency dividing circuit DIV divides the input clock clk by an integer, the frequency dividing ratio in the default state is 1, that is, the frequency division is not performed, and the frequency of the output clk _ DIV clock signal is the same as the frequency of the input clk clock signal; the frequency division of 2 is that the frequency of the output clk _ div clock signal is half of the frequency of the input clk clock signal; the N-division outputs a clk _ div clock signal at 1/N of the input clk clock signal. The frequency dividing ratio of the frequency dividing circuit DIV is controlled by the output signal Vdet of the Voltage Detector:

when Vdet is logic 0, the frequency dividing ratio of the frequency dividing circuit DIV is 1, that is, the frequency of the output clk _ DIV clock signal is the same as the frequency of the input clk clock signal;

when Vdet is logic 1, the frequency dividing ratio of the frequency dividing circuit DIV is N, the value of N is set to be an integer greater than 1 according to the specific situation of the circuit, that is, the output clk _ DIV clock signal frequency is 1/N of the input clk clock signal frequency.

The working method of the low-power-consumption charge pump circuit is characterized in that: in the programming process of the non-volatile memory in the Internet of things security chip, in the process of generating programming voltage by the charge pump circuit,

when the Voltage at the VPP end is in the climbing process and does not reach the Voltage required by programming of the nonvolatile memory, the output Vset of the Voltage Detector is logic 0, the frequency dividing ratio of the frequency dividing circuit DIV is 1, namely the frequency of the output clk _ DIV clock signal is the same as the frequency of the input clk clock signal;

when the Voltage at the VPP terminal reaches the Voltage (15.5V or 10V) required by programming of the nonvolatile memory, the Voltage Detector outputs Vset to be logic 1, the frequency dividing circuit DIV is controlled by the Vset signal, and the clk _ DIV clock signal output by the frequency dividing circuit DIV is reduced to 1/N of the clk clock signal output by the oscillator.

The input clock frequency of the Charge Pump is reduced to 1/N of the original frequency; the charging frequency of the Charge Pump is slowed down, so that the Charge Pump can be prevented from continuously generating redundant charges at the VPP end and discharging the redundant charges through a Zener Diode Zener Diode to realize the voltage stabilization of the VPP, and the voltage at the VPP end is kept at the voltage required by the programming of the nonvolatile memory under the action of a voltage stabilizing capacitor. When the non-volatile memory finishes programming, in the process of VPP programming Voltage discharge, the control signal Vset output by the Voltage detection circuit Voltage Detector can be changed into 0 again, and because the oscillator OSC is closed by the programming control signal at the moment and does not output a clock any more, the Voltage detection circuit Voltage Detector and the frequency division circuit DIV cannot influence the discharge process of the VPP terminal Voltage.

The technical advantages of the invention are as follows:

by adding the voltage detection circuit, after the nonvolatile memory Charge Pump circuit used in the Internet of things security chip generates the voltage (15.5V or 10V) required by programming, the logic of the control signal Vdet is changed, so that the input clock frequency of the boost Charge Pump outputs the frequency of clk from the oscillator OSC, and the frequency is reduced to 1/N of the original frequency; the dynamic power consumption of the boosted Charge Pump Charge Pump, which dominates the power consumption of the non-volatile memory Charge Pump Circuit, is proportional to CfV²And the dynamic power consumption of the Charge Pump circuit of the nonvolatile memory can be reduced by reducing the frequency f, so that the dynamic power consumption of the Charge Pump can be reduced to 1/N after the VPP end programming voltage reaches a set value.

Drawings

FIG. 1 is a schematic circuit diagram of a prior art RFID system;

FIG. 2 is a schematic diagram of an internal circuit configuration of a prior art passive RFID chip;

FIG. 3 is a schematic diagram of a charge pump circuit;

FIG. 4 is a schematic circuit diagram of a charge pump circuit for generating a programming voltage for a nonvolatile memory used in an Internet of things security chip;

FIG. 5 is a schematic diagram of a low power consumption charge pump circuit for generating a programming voltage for a non-volatile memory used in an Internet of things security chip according to the present invention;

in fig. 4, 5, 10, an oscillator OSC; 20. a Non-Overlap clock generator Non Overlap; 30. a boost Charge Pump; 40. a Zener Diode; 50. a voltage stabilizing capacitor; 60. a Voltage Detector circuit; 70. a frequency divider circuit DIV;

FIG. 6 is a waveform diagram of programming voltages generated by the operation of a charge pump circuit in a nonvolatile memory used in an Internet of things security chip of the circuit shown in FIG. 4;

FIG. 7 is a waveform diagram of a programming voltage generated by the low power consumption charge pump circuit in the nonvolatile memory used in the Internet of things security chip.

Detailed Description

The invention is described in detail below with reference to the following examples and the accompanying drawings of the specification, but is not limited thereto.

Examples 1,

As shown in fig. 5, a low power consumption charge pump circuit for a non-volatile memory in a security chip of an internet of things includes: the low power consumption Charge Pump circuit comprises an oscillator OSC 10, a Non-overlapping clock generator Non Overlap 20, a boost Charge Pump 30, a voltage stabilizing Diode Zener Diode 40 and a voltage stabilizing capacitor 50, and further comprises: a Voltage Detector 60 is arranged in parallel at the output end of the boost Charge Pump 30, and a frequency dividing circuit DIV70 is additionally arranged between an oscillator OSC 10 and a Non-overlapping clock generator Non Overlap 20;

the Voltage Detector 60 is configured to: detecting whether a programming voltage generated by the charge pump circuit, namely a VPP terminal voltage reaches 15.5V or 10V required by the programming of the nonvolatile memory:

when the Voltage of the VPP terminal is lower than the Voltage required by programming the nonvolatile memory, the output end Vset of the Voltage Detector is from logic 0 to a frequency dividing circuit DIV;

when the Voltage at the VPP end is higher than the Voltage required by programming the non-volatile memory, the output end Vset of the Voltage Detector is from logic 1 to a frequency divider DIV;

the frequency dividing circuit DIV70 is configured to: the input clock clk is divided by an integer to output a clk _ DIV signal, and the divider circuit DIV70 is controlled by an output signal Vdet of the Voltage Detector 60.

The frequency dividing circuit DIV70 divides the integer of the input clock clk, the frequency dividing ratio is 1 in the default state, namely, the frequency division is not carried out, and the frequency of the output clk _ DIV clock signal is the same as that of the input clk clock signal; the frequency division of 2 is that the frequency of the output clk _ div clock signal is half of the frequency of the input clk clock signal; the N-division outputs a clk _ div clock signal at 1/N of the input clk clock signal.

Examples 2,

In the working method of the low power consumption charge pump circuit according to embodiment 1, during the programming of the nonvolatile memory in the security chip of the internet of things, during the generation of the programming voltage by the charge pump circuit,

when the Voltage at the VPP end does not reach the Voltage required by programming the nonvolatile memory in the climbing process, the output Vset of the Voltage Detector 60 is logic 0, the frequency dividing ratio of the frequency dividing circuit DIV70 is 1, namely the frequency of the output clk _ DIV clock signal is the same as the frequency of the input clk clock signal;

when the Voltage across the VPP terminal reaches the Voltage (15.5V or 10V) required for programming the non-volatile memory, the Voltage Detector 60 outputs Vdet to be logic 1, the divider DIV70 is controlled by the Vdet signal, and the clk _ DIV clock signal output by the divider DIV70 is reduced to 1/N of the clk clock signal output by the oscillator OSC.

Fig. 5 is a waveform diagram of programming Voltage generated by a low-power Charge Pump circuit for a non-volatile memory in an internet-of-things security chip, as shown in fig. 7, after the Charge Pump circuit starts to operate, a boosted Charge Pump 30 gradually raises a VPP terminal Voltage under the control of a non-overlapping clock, after a boosting time T1 elapses, the Voltage generated at the VPP terminal of the Charge Pump circuit reaches a Voltage required for programming the non-volatile memory, at this time, the VPP terminal Voltage is stabilized by a Zener Diode 40 and a Voltage stabilizing capacitor 50, a Voltage Detector 60 detects that the programming Voltage meets a requirement, a control signal Vdet is output to change a frequency dividing ratio of a frequency divider circuit DIV70, the frequency divider DIV70 outputs clk _ DIV clock frequency reduced to 1/N of the oscillator OSC 10 output frequency, because the programming Voltage has no power consumption during programming, the VPP voltage stabilizes at the voltage (15.5V or 10V) required for programming the non-volatile memory. Due to the fact that the time T2 needed by the programming process is long, the low-power-consumption charge pump circuit for the non-volatile memory in the Internet of things security chip, which is provided by the invention, can be used for reducing the power consumption when the low-power-consumption charge pump circuit for the non-volatile memory in the Internet of things security chip works (generates a programming voltage), and particularly the power consumption in a voltage period (within the time T2) when the voltage of the VPP terminal is stabilized at the voltage needed by the non-volatile memory for programming.