阅读说明：本技术 一种低功耗的频率综合器 (Low-power-consumption frequency synthesizer ) 是由 韩怀宇 赵伟兵 邵要华 于 2021-09-29 设计创作，主要内容包括：本发明公开了一种低功耗的频率综合器,包括：前置分频器,用于接收外部电路输入的时钟信号,并对时钟信号进行分频以使得频率综合器输出的时钟信号的步长等于预设步长；锁相环电路,用于接收前置分频器分频后的时钟信号,并输出相位依次变化的N个时钟信号；占空比校正电路,用于接收锁相环电路输出的N个时钟信号,并对N个时钟信号的占空比进行校正,使得N个时钟信号的占空比被校正为预设占空比；N倍频电路,用于接收占空比校正电路输出的占空比被校正后的N个时钟信号,并将占空比被校正后的N个时钟信号进行倍频,输出一个N倍频的最终时钟信号作为频率综合器输出的时钟信号。本发明的频率综合器在确保高频输出的同时实现大幅度降低功耗。(The invention discloses a low-power consumption frequency synthesizer, which comprises: the pre-frequency divider is used for receiving a clock signal input by an external circuit and dividing the frequency of the clock signal so as to enable the step length of the clock signal output by the frequency synthesizer to be equal to a preset step length; the phase-locked loop circuit is used for receiving the clock signals after frequency division of the pre-frequency divider and outputting N clock signals with sequentially changed phases; the duty ratio correction circuit is used for receiving the N clock signals output by the phase-locked loop circuit and correcting the duty ratios of the N clock signals so that the duty ratios of the N clock signals are corrected to be preset duty ratios; and the N frequency multiplication circuit is used for receiving the N clock signals with the corrected duty ratios output by the duty ratio correction circuit, multiplying the frequency of the N clock signals with the corrected duty ratios, and outputting a final N-frequency-multiplied clock signal as the clock signal output by the frequency synthesizer. The frequency synthesizer of the invention can ensure high-frequency output and simultaneously realize great reduction of power consumption.)

1. A frequency synthesizer with low power consumption is characterized in that the frequency synthesizer comprises a pre-frequency divider, a phase-locked loop circuit, a duty ratio correction circuit and an N frequency multiplication circuit;

the pre-frequency divider is used for receiving a clock signal input by an external circuit and dividing the frequency of the clock signal;

the phase-locked loop circuit is used for receiving the frequency-divided clock signals output by the pre-frequency divider and outputting N clock signals with sequentially changed phases;

the duty ratio correction circuit is used for receiving the N clock signals with the sequentially changed phases output by the phase-locked loop circuit and correcting the duty ratios of the N clock signals with the sequentially changed phases so that the duty ratios of the N clock signals with the sequentially changed phases are corrected to be preset duty ratios;

the N frequency multiplication circuit is used for receiving the N clock signals with the corrected duty ratios and sequentially changing phases output by the duty ratio correction circuit, multiplying the N clock signals with the corrected duty ratios and sequentially changing phases, and outputting a final N-frequency-multiplied clock signal as the clock signal output by the frequency synthesizer;

wherein N is an integer multiple of 2.

2. The frequency synthesizer of claim 1, wherein the prescaler comprises an input terminal and an output terminal, the input terminal of the prescaler is used as the input terminal of the frequency synthesizer and is used for receiving the clock signal input by the external circuit, and the output terminal of the prescaler is used for outputting the divided clock signal to the phase-locked loop circuit.

3. The frequency synthesizer of claim 2, wherein the phase-locked loop circuit comprises an input terminal and an output terminal, the input terminal of the phase-locked loop circuit is connected to the output terminal of the prescaler for receiving the frequency-divided clock signal outputted from the prescaler, and the output terminal of the phase-locked loop circuit is used for outputting N clock signals with sequentially changed phases to the duty ratio correction circuit.

4. The low-power frequency synthesizer according to claim 3, wherein the phase-locked loop circuit comprises: the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the loop frequency divider;

the phase frequency detector comprises a first input end, a second input end and an output end, wherein the first input end of the phase frequency detector is used as the input end of the phase-locked loop circuit, and the first input end of the phase frequency detector is connected with the output end of the pre-frequency divider and used for receiving a clock signal output by the pre-frequency divider after frequency division;

the charge pump comprises an input end and an output end, and the input end of the charge pump is connected with the output end of the phase frequency detector;

the low-pass filter comprises an input end and an output end, and the input end of the low-pass filter is connected with the output end of the charge pump;

the voltage-controlled oscillator comprises an input end, and the input end of the voltage-controlled oscillator is connected with the output end of the low-pass filter;

the loop frequency divider comprises an input end and an output end, and the output end of the loop frequency divider is connected with the second input end of the phase frequency detector and is used for dividing the frequency of the clock signal to generate a feedback clock signal and outputting the feedback clock signal.

5. The low power consumption frequency synthesizer according to claim 4, wherein the voltage controlled oscillator further comprises N outputs, and the N outputs of the voltage controlled oscillator are used as the outputs of the phase locked loop circuit for outputting N clock signals with sequentially changing phases to the duty ratio correction circuit.

6. The low-power-consumption frequency synthesizer according to claim 5, wherein the duty cycle correction circuit comprises N input terminals and N output terminals, the N input terminals of the duty cycle correction circuit are connected to the N output terminals of the voltage-controlled oscillator in a one-to-one correspondence, and configured to receive the N clock signals with sequentially changed phases output by the voltage-controlled oscillator, and the N output terminals of the duty cycle correction circuit are configured to output the N clock signals with sequentially changed phases after the duty cycle is corrected.

7. The low power consumption frequency synthesizer of claim 6, wherein there is one output from the N outputs of the voltage controlled oscillator that is coupled to both an input of the duty cycle correction circuit and an input of the loop divider.

8. The low power consumption frequency synthesizer according to claim 6, wherein the N-multiplier circuit comprises an output terminal and N input terminals, the N input terminals of the N-multiplier circuit are connected to the N output terminals of the duty correction circuit in a one-to-one correspondence for receiving N clock signals with sequentially changed phases after the duty ratio output by the duty correction circuit is corrected, and the output terminal of the N-multiplier circuit serves as the output terminal of the frequency synthesizer for outputting an N-multiplied final clock signal.

9. The low power consumption frequency synthesizer according to claim 4, wherein the voltage controlled oscillator is a ring oscillator with a differential structure, and the number of differential inverters of the ring oscillator is N.

10. The frequency synthesizer with low power consumption of claim 1, wherein the N-fold frequency circuit is formed by N-1 exclusive or gates, or wherein the N-fold frequency circuit is formed by N-1 exclusive or gates.

11. The low-power-consumption frequency synthesizer according to claim 1, wherein the preset duty ratio is 50%, and the duty ratio correction circuit corrects the duty ratios of the N clock signals with sequentially changing phases output by the phase-locked loop circuit to 50%.

Technical Field

The invention relates to the field of circuit design, in particular to a low-power-consumption frequency synthesizer.

Background

The frequency synthesizer is a key device commonly used in modern communication systems, radars and test equipment, and can provide high-precision and high-stability frequency. Currently, there are mainly 3 frequency synthesis methods: firstly, direct frequency synthesis; secondly, phase-locked frequency synthesis; direct digital frequency synthesis; the direct frequency synthesis method has better phase noise performance, is generally applied to ground radars and radio frequency microwave test equipment, and mainly adopts a clock phase-locked frequency synthesis method or a direct digital frequency synthesis method in other fields. Then, in order to output a clock signal of a target frequency, a frequency synthesizer adopting a phase-locked frequency synthesis method generally outputs a high-frequency clock signal by increasing a current, and the higher the target frequency is, the higher the power consumption of the frequency synthesizer is, and the current frequency synthesizer has a defect that the high power consumption is required for outputting the high-frequency clock signal.

Disclosure of Invention

In order to solve the above problems, the present invention provides a frequency synthesizer with low power consumption, which can greatly reduce the power consumption of the frequency synthesizer while realizing the output of high frequency clock signals. The specific technical scheme of the invention is as follows:

a frequency synthesizer with low power consumption comprises a pre-frequency divider, a phase-locked loop circuit, a duty ratio correction circuit and an N frequency multiplication circuit; the pre-frequency divider is used for receiving a clock signal input by an external circuit, dividing the frequency of the clock signal and combining the frequency multiplication times of the N frequency multiplication circuits so as to enable the step length of the clock signal finally output by the frequency synthesizer to be equal to the preset step length; the phase-locked loop circuit is used for receiving the clock signals after frequency division of the pre-frequency divider and outputting N clock signals with sequentially changed phases; the duty ratio correction circuit is used for receiving the N clock signals with the sequentially changed phases output by the phase-locked loop circuit and correcting the duty ratios of the N clock signals with the sequentially changed phases so that the duty ratios of the N clock signals with the sequentially changed phases are corrected to be preset duty ratios; the N frequency multiplication circuit is used for receiving the N clock signals with the corrected duty ratios and sequentially changing phases output by the duty ratio correction circuit, multiplying the N clock signals with the corrected duty ratios and sequentially changing phases, and outputting a final N-frequency-multiplied clock signal as the clock signal output by the frequency synthesizer; wherein N is an exponential multiple of 2.

Compared with the prior art, the technical scheme is that N frequency multiplication is carried out on N clock signals which are output by the phase-locked loop circuit and sequentially change in phase based on the N frequency multiplication circuit, so that the phase-locked loop circuit only needs to output N clock signals which sequentially change in phase and have low frequency, and the phase difference between every two adjacent clock signals is pi/N, so that the clock signals output by the frequency synthesizer can also reach target high frequency, and the purpose that the frequency synthesizer outputs high-frequency clock signals in low power consumption is achieved.

Furthermore, the prescaler includes an input terminal and an output terminal, the input terminal of the prescaler is used as the input terminal of the frequency synthesizer and is used for receiving a clock signal input by an external circuit, and the output terminal of the prescaler is used for outputting the divided clock signal to the phase-locked loop circuit. Compared with the prior art, the pre-frequency divider arranged in the technical scheme regulates and controls the frequency dividing number of the pre-frequency divider according to the frequency multiplying factor of the N frequency multiplying circuit of the frequency synthesizer, the frequency of the clock signal input by the external circuit and the preset step length, so that the step length of the clock signal output by the frequency synthesizer is equal to the preset step length.

Furthermore, the phase-locked loop circuit comprises an input end and an output end, the input end of the phase-locked loop circuit is connected with the output end of the pre-frequency divider and used for receiving the frequency-divided clock signal output by the pre-frequency divider, and the output end of the phase-locked loop circuit is used for outputting N clock signals with sequentially changed phases to the duty ratio correction circuit. The phase-locked loop circuit of the technical scheme is connected with the pre-frequency divider, receives the clock signal after frequency division adjustment, and achieves step length pre-adjustment of the clock signal output by the frequency synthesizer.

Further, the phase-locked loop circuit specifically includes: the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the loop frequency divider; the phase frequency detector comprises a first input end, a second input end and an output end, wherein the first input end of the phase frequency detector is used as the input end of the phase-locked loop circuit, and the first input end of the phase frequency detector is connected with the output end of the pre-frequency divider and used for receiving a clock signal output by the pre-frequency divider after frequency division; the charge pump comprises an input end and an output end, and the input end of the charge pump is connected with the output end of the phase frequency detector; the low-pass filter comprises an input end and an output end, and the input end of the low-pass filter is connected with the output end of the charge pump; the voltage-controlled oscillator comprises an input end, and the input end of the voltage-controlled oscillator is connected with the output end of the low-pass filter; the loop frequency divider comprises an input end and an output end, and the output end of the loop frequency divider is connected with the second input end of the phase frequency detector and is used for dividing the frequency of the clock signal to generate a feedback clock signal and outputting the feedback clock signal. According to the technical scheme, the loop frequency divider is arranged in the phase-locked loop circuit, so that the loop frequency divider divides the frequency of the clock signal output by the voltage-controlled oscillator to obtain a feedback clock signal which is used for being compared with the clock signal input into the phase frequency detector by the pre-frequency divider, and whether the phase-locked loop circuit needs to perform feedback adjustment currently is determined according to the comparison result, so that the clock signal output by the phase-locked loop circuit can be output according to the target frequency.

Furthermore, the voltage-controlled oscillator further includes N output terminals, configured to output N clock signals with sequentially changing phases to the duty ratio correction circuit. According to the voltage-controlled oscillator, N clock signals with sequentially changed phases are respectively transmitted to the duty ratio correction circuit, so that duty ratio correction of the N clock signals with sequentially changed phases output by the voltage-controlled oscillator is achieved, and the situation that the duty ratio of the clock signals output by the voltage-controlled oscillator deviates from the preset duty ratio, which causes abnormal fluctuation of the duty ratio of the final N-frequency-multiplied clock signal output by the N-frequency multiplication circuit, even the situation that the final N-frequency-multiplied clock signal output by the N-frequency multiplication circuit is mistakenly lost is avoided.

Furthermore, the duty cycle correction circuit includes N input terminals and N output terminals, where the N input terminals of the duty cycle correction circuit are connected to the N output terminals of the voltage-controlled oscillator in a one-to-one correspondence manner, and are configured to receive N clock signals with sequentially changing phases output by the voltage-controlled oscillator, and the N output terminals of the duty cycle correction circuit are configured to output N clock signals with sequentially changing phases with corrected duty cycle. In the technical scheme, the number of the output ends of the voltage-controlled oscillator and the number of the input ends and the output ends of the duty ratio correction circuits are set to be the same as the number of the frequency multiplication stages of the N frequency multiplication circuits, so that the clock signals output by the voltage-controlled oscillator can be subjected to frequency multiplication by the N frequency multiplication circuits in one-to-one correspondence after being corrected by the duty ratio correction circuits.

Further, there is an output terminal among the N output terminals of the voltage-controlled oscillator, and the output terminal is simultaneously connected to an input terminal of the duty ratio correction circuit and an input terminal of the loop frequency divider. In the technical scheme, one of N output ends of the voltage-controlled oscillator is selected to be connected with one input end of the duty ratio correction circuit and the input end of the loop frequency divider, so that frequency multiplication of a clock signal after duty ratio correction can be realized, frequency division of the clock signal output by the voltage-controlled oscillator can be realized to be used as a feedback clock signal to perform feedback adjustment of the phase-locked loop circuit, and the stability of the phase-locked loop circuit is ensured.

Further, the N-fold frequency circuit includes an output end and N input ends, the N input ends of the N-fold frequency circuit are connected to the N output ends of the duty ratio correction circuit in a one-to-one correspondence manner, and are configured to receive N clock signals whose duty ratios output by the duty ratio correction circuit are corrected and whose phases sequentially change, and the output end of the N-fold frequency circuit serves as the output end of the frequency synthesizer and is configured to output an N-fold frequency final clock signal. The N frequency doubling circuit in the technical scheme is provided with N input ends and an output end, so that the N frequency doubling circuit doubles the frequency of N input clock signals which sequentially change in phase into an N frequency doubled final clock signal for output, the phase-locked loop circuit outputs the low-frequency clock signal, the N frequency doubling circuit is utilized for carrying out the N frequency doubling, and the effect of low-power-consumption high-frequency output of the frequency synthesizer is achieved.

Further, the voltage-controlled oscillator is a ring oscillator with a differential structure. In the technical scheme, the voltage-controlled oscillator in the phase-locked loop circuit is designed into the ring oscillator with the differential structure, so that the voltage-controlled oscillator can output multi-phase clock signals, and the multi-phase clock signals can be subjected to N frequency multiplication by combining with an N frequency multiplication circuit better.

Further, the N frequency multiplication circuit is composed of N-1 exclusive or logic gates, or the N frequency multiplication circuit is composed of N-1 exclusive or logic gates. In the technical scheme, the N frequency multiplier circuit is set to be N-1 exclusive-OR logic gate circuits or N-1 exclusive-OR logic gates, the frequency multiplier circuit structure formed by the exclusive-OR logic gates or the exclusive-OR logic gates consumes lower power consumption when frequency multiplication is realized, and the frequency synthesizer is combined with the low-power-consumption output low-frequency clock signal of the phase-locked loop circuit, so that the purpose of outputting the high-frequency clock signal with low power consumption is better achieved.

Further, the duty ratio correction circuit is configured to correct the duty ratios of the N clock signals whose phases sequentially change to 50%. In the technical scheme, the preset duty ratio of the duty ratio correction circuit is set to be 50%, so that the duty ratio correction circuit corrects the duty ratio of the received N clock signals with sequentially changed phases to be 50%, and the condition that the duty ratio of the clock signals transmitted to the N frequency doubling circuits by the duty ratio correction circuit deviates from 50% to cause abnormal fluctuation of the duty ratio of the clock signals and even cause error loss of the output clock signals is avoided.

Drawings

Fig. 1 is a schematic structural diagram of a frequency synthesizer according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a frequency synthesizer according to another embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an 8-stage frequency multiplier circuit according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a 16-stage frequency multiplier circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clear, the present invention will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the following specific examples are illustrative only and are not intended to limit the invention. Moreover, it should be understood that the technical disclosure of the present invention may be modified by those skilled in the art by a conventional method, and it should not be understood that the technical disclosure of the present invention is not limited thereto.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to the words "a," "an," "the," and "the" in this application are not to be construed as limiting in number, and may mean singular or plural. The use of the terms "including," "comprising," "having," and any variations thereof herein, is intended to cover non-exclusive inclusions, such as: a process, method, system product or apparatus that comprises a list of steps or modules is not limited to the listed steps or elements but may include additional steps or elements not listed or inherent to such process, method, product or apparatus. Reference throughout this application to the terms "first," "second," "third," and the like are only used for distinguishing between similar references and not intended to imply a particular ordering for the objects.

In an embodiment of the present invention, a low power consumption frequency synthesizer is provided, as shown in fig. 1, the low power consumption frequency synthesizer includes: the frequency synthesizer comprises a pre-frequency divider, a phase-locked loop circuit, a duty cycle correction circuit and an N frequency multiplication circuit, wherein the input end of the pre-frequency divider is used as the input end of the frequency synthesizer, the output end of the pre-frequency divider is connected with the input end of the phase-locked loop circuit, the output end of the phase-locked loop circuit is connected with the input end of the duty cycle correction circuit, the output end of the duty cycle correction circuit is connected with the input end of the N frequency multiplication circuit, and the output end of the N frequency multiplication circuit is used as the output end of the frequency synthesizer.

Specifically, the prescaler is configured to receive a clock signal input by an external circuit, divide the frequency of the clock signal, and combine with N times of frequency multiplication by the N frequency multiplication circuit to enable a step length of the clock signal output by the frequency synthesizer to be equal to a preset step length; the frequency dividing number of the pre-frequency divider is set based on the frequency of a clock signal input by the external circuit, the frequency multiplying number of the N frequency multiplying circuit and a preset step length; it should be noted that the frequency division number of the prescaler is adjustable; the phase-locked loop circuit is used for receiving the clock signal after frequency division of the pre-frequency divider and outputting N clock signals with certain frequency and sequentially changed phases; the duty ratio correction circuit is used for receiving N clock signals with a certain frequency and sequentially changing phases output by the phase-locked loop circuit and correcting the duty ratios of the N clock signals with sequentially changing phases, so that the duty ratios of the N clock signals with sequentially changing phases are corrected to be preset duty ratios; and the N frequency multiplication circuit is used for receiving the N clock signals with the sequentially changed phases after the duty ratio correction output by the duty ratio correction circuit, multiplying the N clock signals with the sequentially changed phases after the duty ratio correction, and outputting an N frequency-multiplied final clock signal as the clock signal output by the frequency synthesizer. It should be noted that, the frequency of the final clock signal of N-fold frequency output by the clock signal of a certain frequency output by the phase-locked loop circuit after passing through the N-fold frequency circuit is equal to the target frequency of the frequency synthesizer; where N is an integer multiple of 2, it is understood that N can be, but is not limited to, 2, 4, 8, or 16, etc. which is an integer multiple of 2; the preset duty ratio is a duty ratio preset in the duty ratio correction circuit according to actual duty ratio requirements and is used as a correction standard to correct the duty ratios of N clock signals which are output by the phase-locked loop circuit and change in sequence.

Based on the foregoing embodiments, another embodiment of the present invention provides a frequency synthesizer with low power consumption, where the frequency synthesizer includes: the frequency-division circuit comprises a pre-frequency divider, a phase-locked loop circuit, a duty ratio correction circuit and an N frequency multiplication circuit, wherein the phase-locked loop circuit adopts a charge pump phase-locked loop circuit. Charge pump phase locked loop circuits are a typical representation of digital-to-analog hybrid phase locked loop circuits, which have irreplaceable advantages: in theory, the static phase error of the charge pump phase-locked loop structure can be proved to be zero, and in practice, the charge pump phase-locked loop structure has the characteristics of high height, low power consumption and low jitter.

Specifically, the phase-locked loop circuit specifically includes: the phase frequency detector, the charge pump, the low pass filter, the voltage controlled oscillator and the loop frequency divider. The phase frequency detector includes first input, second input and output, the first input of phase frequency detector does phase-locked loop circuit's input with leading frequency divider's output is connected, the charge pump includes input and output, phase frequency detector's output with charge pump's input is connected, low pass filter includes input and output, the output of charge pump with low pass filter's input is connected, voltage controlled oscillator includes input and a N output, low pass filter's output with voltage controlled oscillator's input is connected, a N output of voltage controlled oscillator does phase-locked loop circuit's output is used for with N phase place that phase-locked loop circuit output changes in proper order clock signal transmits to duty ratio correction circuit.

The loop frequency divider comprises an input end and an output end, the output end of the loop frequency divider is connected with the second input end of the phase frequency detector, and the input end of the loop frequency divider is connected with one output end of the N output ends of the voltage-controlled oscillator. The loop frequency divider is used for receiving a clock signal transmitted by the voltage-controlled oscillator, dividing the frequency of the clock signal, transmitting the divided clock signal to the second input end of the phase frequency detector as a feedback clock signal, comparing the divided clock signal with a frequency-divided clock signal transmitted by a pre-frequency divider and input by the first input end of the phase frequency detector, performing feedback adjustment on the phase-locked loop circuit according to a comparison result until the output frequency of the voltage-controlled oscillator is stabilized to be the clock signal of a target frequency, and determining the stability of the phase-locked loop circuit, wherein the feedback clock signal is equal to the frequency-divided clock signal transmitted to the phase frequency detector by the pre-frequency divider. It should be noted that, when the phase-locked loop circuit is stabilized, the frequency of the clock signal output by the voltage-controlled oscillator of the phase-locked loop circuit is equal to the product of the frequency of the clock signal input by the prescaler after frequency division and the frequency division number of the loop frequency divider, so that the frequency of the clock signal output by the frequency synthesizer is equal to the product of the frequency of the clock signal input by the external circuit divided by the frequency division number of the prescaler and multiplied by the frequency division number of the loop frequency divider, and multiplied by the multiple of the frequency multiplication number of the frequency multiplication circuit, that is: the frequency of the clock signal output by the frequency synthesizer = (frequency of the clock signal input by the external circuit/frequency division number of the prescaler) × (frequency division number of the loop frequency divider) × (multiple times of the N-fold circuit).

Preferably, an output end of the N output ends of the voltage-controlled oscillator is connected to both the input end of the loop frequency divider and an input end of the duty ratio correction circuit, so that frequency multiplication of N clock signals with sequentially changing phases after duty ratio correction can be realized, and frequency division of one clock signal output by the voltage-controlled oscillator can be realized to serve as a feedback clock signal for self-adjustment of the phase-locked loop circuit, thereby ensuring stability of the phase-locked loop circuit. It should be noted that, N clock signals with sequentially changing phases output by N output terminals of the voltage-controlled oscillator have the same frequency and different phases, and specifically, the phase difference between two adjacent clock signals is pi/N.

Preferably, the duty cycle correction circuit includes N input terminals and N output terminals, and the N input terminals of the duty cycle correction circuit are connected to the N output terminals of the voltage-controlled oscillator, and are configured to receive N clock signals output by the voltage-controlled oscillator and whose phases are sequentially changed; the N-frequency multiplier circuit comprises an output end and N input ends, the N input ends of the N-frequency multiplier circuit are connected with the N output ends of the duty ratio correction circuit and used for receiving the clock signals which are output by the duty ratio correction circuit and have N corrected duty ratios, and the output end of the N-frequency multiplier circuit is used as the output end of the frequency synthesizer and used for outputting a final N-frequency multiplied clock signal as the clock signal output by the frequency synthesizer. The duty ratio correction circuit is arranged between the phase-locked loop circuit and the N frequency multiplication circuit to ensure that the duty ratio of N clock signals output by the phase-locked loop circuit and sequentially changed in phase is corrected to be a preset duty ratio, so that the condition that the duty ratio fluctuation of the final clock signal of the N frequency multiplication output by the N frequency multiplication circuit is abnormal due to the deviation of the duty ratio of the N clock signals output by the phase-locked loop circuit and the N frequency multiplication is even wrong and the clock is lost is avoided.

Based on the foregoing embodiments, in another embodiment of the present invention, a low-power-consumption frequency synthesizer is provided, in this embodiment, the voltage-controlled oscillator adopts a ring oscillator with a differential structure, the number of stages of a differential inverter of the ring oscillator is set to be N stages that is the same as the number of stages of the N frequency doubling circuit, each stage adopts a dual-input dual-output structure, and a phase difference between two adjacent clock signals in N clock signals whose phases are sequentially changed output by the ring oscillator with the differential structure is pi/N.

Preferably, the voltage-controlled oscillator may also be, but is not limited to, a ring oscillator adopting a differential structure, a ring oscillator adopting a non-differential structure, or the like. In the present invention, the voltage-controlled oscillator may be an oscillator capable of outputting N clock signals having the same frequency and different phases.

As a preferred embodiment of the present invention, a voltage-controlled oscillator module of a phase-locked loop circuit in a frequency synthesizer is designed as a ring oscillator with a differential structure, and the number of stages of a differential inverter of the ring oscillator is set to be one of 4, 8, 16, 32 or 64 stages, and the ring oscillator outputs a general clock signal in which phases of all outputable signals are sequentially and continuously changed, such as: 4. 8, 16, 32 or 64 clock signals, and the phase difference of two adjacent clock signals corresponds to pi/4, pi/8, pi/16, pi/32 or pi/64. Meanwhile, in the frequency synthesizer provided in this embodiment, the number of frequency multiplication stages of the N frequency multiplication circuit is set to a value equal to the number of stages of the differential inverters of the ring oscillator, and the number of output terminals of the ring oscillator, the number of input terminals and the number of output terminals of the duty ratio correction circuit are all equal to the number of stages of the differential inverters of the ring oscillator.

Based on the foregoing embodiments, an embodiment of the present invention provides an N-ary frequency multiplier circuit, where the N-ary frequency multiplier circuit is composed of N-1 xor gates, the N-1 xor gates are distributed in N rows, a 1 st row includes N/2 xor gates, a 2 nd row includes N/2^2 xor gates, a 3 rd row includes N/2^3 xor gates, and so on, the N th row includes N/2^ N xor gates; wherein N is equal to 2^ N, N is a positive integer, understandably, the nth column includes 1 exclusive or gate, the output end of the exclusive or gate of the nth column is used as the output end of the frequency multiplication circuit to output the final clock signal of the frequency multiplication, each exclusive or gate includes two input ends and one output end, and the phase difference of the two clock signals input into the same exclusive or gate is pi/2. It should be noted that, the power consumption of the frequency multiplier N provided by this embodiment is very small, but the power consumption of the frequency multiplier N is also multiplied with the increase of the frequency multiplication number of the frequency multiplier N, so in the practical application of the frequency synthesizer, the frequency multiplication number of the frequency multiplier N is generally designed to be a relatively moderate value, such as: 8. 16, 32, etc., the description herein does not intend to limit the number of frequency multiplication stages of the frequency-multiplying circuit of the present invention, and the number of frequency multiplication stages of the frequency-multiplying circuit may be other numerical values satisfying an integer multiple of 2.

As a preferred embodiment of the present invention, the frequency synthesizer provided in this embodiment adopts an 8-stage frequency multiplier circuit, and as shown in fig. 3, the 8-stage frequency multiplier circuit is composed of 7 xor logic gates, the 7 xor logic gates are distributed into 3 columns, the 1 st column includes 4 xor logic gates, the 2 nd column includes 2 xor logic gates, the 3 rd column includes 1 xor logic gate, each xor logic gate includes 2 input terminals and 1 output terminal, a total of 8 input terminals of the 4 xor logic gates in the 1 st column are used as the 8 input terminals of the 8-stage frequency multiplier circuit, and an output terminal of the 1 xor logic gate in the 3 rd column is used as an output terminal of the 8-stage frequency multiplier circuit to output a final clock signal of 8-stage frequency multiplication. Since the 8 frequency doubling circuits are adopted in this embodiment, the number of stages of the voltage-controlled oscillator is also set to 8 stages, 16 time signals are provided in total, the voltage-controlled oscillator outputs 8 clock signals with sequentially changed phases, the phase difference between every two adjacent clock signals of the 8 clock signals with sequentially changed phases output by the voltage-controlled oscillator is pi/8, 8 output ends of the voltage-controlled oscillator are correspondingly connected with 8 input ends of the duty ratio correction circuit, and 8 output ends of the duty ratio correction circuit are correspondingly connected with 8 input ends of the 1 st column of xor logic gates of the 8 frequency doubling circuits, so that the phase difference between the two clock signals input by each xor logic gate is pi/2.

Preferably, the N-multiplier circuit of the present invention may be, but is not limited to, formed by a plurality of exclusive or logic gates, or formed by a plurality of exclusive or logic gates and a plurality of exclusive or logic gates, and specific components of the N-multiplier circuit may be designed according to actual requirements, and only one final N-multiplied clock signal needs to be output.

Based on the foregoing embodiment, the low-power-consumption frequency synthesizer according to an embodiment of the present invention adopts a duty ratio correction circuit with a low-power-consumption structure, and sets a preset duty ratio of the duty ratio correction circuit to a 50% duty ratio, so that the duty ratio correction circuit corrects the duty ratios of N clock signals output by the voltage-controlled oscillator and sequentially changed in phase to 50%. Because N clock signals output by the voltage-controlled oscillator and sequentially changed in phase finally need to be input into the N-ary frequency circuit, if the duty ratio of the N clock signals input into the N-ary frequency circuit and sequentially changed in phase deviates by more than 50%, the condition that the duty ratio of the clock signals output by the N-ary frequency circuit fluctuates abnormally may be caused, and in severe cases, the clock signals output by the N-ary frequency circuit may be lost incorrectly.

Based on the foregoing embodiment, the low-power-consumption frequency synthesizer provided in an embodiment of the present invention employs a pre-divider with an adjustable division number, where the division number of the pre-divider is adjusted according to an actual user requirement, so that the frequency synthesizer can output an N-times multiplied clock signal with a preset step size, and the division number of the pre-divider, the preset step size, a frequency of the clock signal input by the external circuit, and a number of multiplication stages of an N-times circuit of the frequency synthesizer satisfy: the ratio of the product of the frequency of the clock signal input by the external circuit and the frequency multiplication series of the N frequency multiplication circuit of the frequency synthesizer to the frequency division number of the pre-frequency divider is equal to the preset step length.

For the current phase-locked loop circuit, when the frequency of the clock signal output by the voltage-controlled oscillator is 100MHz, the overall power consumption of the phase-locked loop circuit is only about 100 μ a to 200 μ a, but when the frequency of the clock signal output by the voltage-controlled oscillator reaches 1.6GHz, the overall power consumption of the phase-locked loop circuit can reach 1mA to 2 mA. Therefore, for the frequency synthesizer adopting the invention, only the frequency of the clock signal output by the voltage-controlled oscillator needs to be controlled to be 100MHz, and the duty ratio correction circuit and the N frequency multiplication circuit which are arranged outside the phase-locked loop circuit are combined, so that the whole power consumption of the phase-locked loop circuit can be kept to be 100 muA to 200 muA when the frequency of the clock signal output by the frequency synthesizer reaches N x 100MHz, and when N of the N frequency multiplication circuit is equal to 16, the power consumption of the N frequency multiplication circuit is only about 100 muA, thereby realizing that the frequency synthesizer outputs a high-frequency clock signal with low power consumption.

Based on the above embodiments, in a preferred embodiment of the present invention, the N frequency multiplier circuit is set as a 16-stage frequency multiplier circuit, the frequency of the clock signal output by the voltage-controlled oscillator is 100MHz, and by combining the duty cycle circuit and the 16-stage frequency multiplier circuit which are arranged outside the phase-locked loop circuit, when the clock signal output by the frequency synthesizer reaches 1.6GHz, the overall power consumption of the frequency synthesizer is only 200 μ Α -400 μ Α, which is much smaller than the overall power consumption required when the phase-locked loop circuit outputs the 1.6GHz high-frequency clock signal in the prior art.

Preferably, the duty ratio correction circuit and the N-multiplier circuit are arranged outside a loop of the phase-locked loop circuit, so that the problems that a clock signal output by the N-multiplier circuit is greatly influenced by a duty ratio at a starting stage, larger instability exists, and the output of a feedback clock signal of the loop frequency divider is possibly influenced, so that the loop of the phase-locked loop circuit is difficult to start or lock can be avoided. Because the N clock signals sequentially changed in phase, which are output by the voltage-controlled oscillator of the phase-locked loop circuit at the start-up stage, have a large difference, which may affect the accuracy of the N-multiplied final clock signal output by the N-multiplier circuit, and if the N-multiplied final clock signal output by the N-multiplier circuit is transmitted to the loop divider of the phase-locked loop circuit for frequency division, the frequency division number of the loop divider needs to be designed to a large frequency division value, which increases the complexity of the loop divider, and if an N-multiplied final clock signal output by the N-multiplier circuit is transmitted to the loop divider of the phase-locked loop circuit for frequency division, when the accuracy of an N-multiplied final clock signal output by the N-multiplier circuit is poor, the accuracy of the feedback clock signal output by the loop divider after frequency division is correspondingly reduced, the phase-locked loop circuit is difficult to start or lock, and the overall working efficiency of the frequency synthesizer is affected.

Based on the above embodiments, as a preferred embodiment of the present invention, the voltage-controlled oscillation circuit in the phase-locked loop circuit is designed as a ring oscillator structure of a 16-difference inverter, and the frequency-N multiplier circuit is designed as a 16-multiplier circuit, as shown in fig. 4, the 16-multiplier circuit is composed of 15 xor gates, the 1 st column includes 8 xor gates, the 2 nd column includes 4 xor gates, the 3 rd column includes 2 xor gates, the 4 th column includes 1 xor gate, each xor gate includes two input ends and one output end, and when the two clock signals received by the two input ends of each xor gate have the same frequency and have a phase difference of 90 °, the xor gate can output a 2-fold clock signal based on the original two clock signals, and so on, the xor gate in the last column can output a 2-fold clock signal based on the original frequency of the clock signal input to the 16-multiplier circuit Now a 16 times multiplied clock signal is output.

Each period of the ring oscillator of the 16-stage differential phase inverter has 32 phase clock signals, the phase difference between two adjacent clock signals is pi/16, the first half period clock signal of the 32 phase clock signals, that is, the first 16 phase clock signal, is selected and transmitted to the duty ratio correction circuit for duty ratio correction processing, so that the duty ratio of the 16 phase clock signal is corrected to 50%, and then the 16 duty ratio corrected clock signals output by the duty ratio correction circuit corresponding to the 16 duty ratios are input to the 16-stage frequency multiplication circuit, it should be noted that the 16 duty ratio corrected clock signals output by the duty ratio correction circuit are input to the 16 frequency multiplication circuit according to the phase sequence, so that the two clock signals received by each xor logic gate in the 16 frequency multiplication circuit have the same frequency and the phase difference of 90 degrees, and finally, the 16 frequency doubling circuit outputs a 16 frequency doubled final clock signal as the integral output of the frequency synthesizer, so that the aim of outputting a low-power-consumption high-frequency clock signal is fulfilled.

Obviously, the above-mentioned embodiments are only a part of embodiments of the present invention, not all embodiments, and the technical solutions of the embodiments may be combined with each other. In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In the embodiments provided in the present invention, it should be understood that the disclosed technical contents can be implemented in other manners. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the circuit may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed.

It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.