阅读说明：本技术 服务器解码卡下电控制方法、系统、终端及存储介质 (Server decoding card power-off control method, system, terminal and storage medium ) 是由 张涛 于 2021-06-18 设计创作，主要内容包括：本发明提供一种服务器解码卡下电控制方法、系统、终端及存储介质,包括：BMC芯片采集主板端PCIE供电接口的电压值；通过将所述电压值与下电参考阈值比对,确认PCIE供电接口处于下电状态；定期采集所述电压值,并将电压值与高电平值进行比对,若电压值低于所述高电平值则控制复杂可编程逻辑器件向电压调节器发送下电信号。本发明通过利用BMC监测主板端PCIE供电接口的电压值,实现对服务器上下电状态的判定,并在下电状态时及时向复杂可编程逻辑器件发送下电信号,可以实时监控P12V-PCIE的电压变化,使得CPLD能够精准的判定系统当前的工作状态,从而避免出现因系统放电慢而出现的CPLD仍输出EN信号的问题,继而避免后级VR电源的异常工作状态,增加系统的可靠性。(The invention provides a method, a system, a terminal and a storage medium for controlling the power-off of a server decoding card, comprising the following steps: the method comprises the steps that a BMC chip collects a voltage value of a PCIE power supply interface at a main board end; comparing the voltage value with a power-down reference threshold value to confirm that the PCIE power supply interface is in a power-down state; and regularly acquiring the voltage value, comparing the voltage value with a high level value, and controlling the complex programmable logic device to send a lower electric signal to the voltage regulator if the voltage value is lower than the high level value. According to the invention, the voltage value of the PCIE power supply interface at the mainboard end is monitored by using the BMC, the judgment of the power-on and power-off states of the server is realized, the power-off signal is timely sent to the complex programmable logic device in the power-off state, and the voltage change of the P12V _ PCIE can be monitored in real time, so that the CPLD can accurately judge the current working state of the system, the problem that the CPLD still outputs an EN signal due to slow system discharge is avoided, the abnormal working state of a rear-stage VR power supply is avoided, and the reliability of the system is improved.)

1. A server decoding card power-down control method is characterized by comprising the following steps:

the method comprises the steps that a BMC chip collects a voltage value of a PCIE power supply interface at a main board end;

comparing the voltage value with a power-down reference threshold value to confirm that the PCIE power supply interface is in a power-down state;

and regularly acquiring the voltage value, comparing the voltage value with a high level value, and controlling the complex programmable logic device to send a lower electric signal to the voltage regulator if the voltage value is lower than the high level value.

2. The method of claim 1, wherein the collecting, by the BMC chip, the voltage value of the PCIE power interface at the board side comprises:

the BMC chip collects the voltage value of the PCIE power supply interface in real time through a voltage dividing resistor middle access point connected with the PCIE power supply interface.

3. The method of claim 1, wherein confirming that the PCIE power interface is in a power-down state by comparing the voltage value with a power-down reference threshold comprises:

presetting a power-off reference threshold;

and if the voltage value of the PCIE power supply interface is lower than the power-down reference threshold value, judging that the PCIE power supply interface is in a power-down state.

4. The method of claim 1, wherein periodically collecting the voltage value and comparing the voltage value to a high level value, and controlling the complex programmable logic device to send a down signal to the voltage regulator if the voltage value is lower than the high level value comprises:

collecting a high-level value determined by a complex programmable logic device and caching the high-level value to the local BMC;

collecting the voltage value of a PCIE power supply interface every 100 ms;

and if the voltage value is lower than the high level value and lower than the high level value, sending a low level signal to the complex programmable logic device, and triggering the complex programmable logic device to send a down electric signal to the voltage regulator by the low level signal.

5. A server decoder card power-down control system is characterized by comprising:

the voltage acquisition unit is used for acquiring a voltage value of a PCIE power supply interface at the mainboard end by the BMC chip;

the state confirmation unit is used for confirming that the PCIE power supply interface is in a power-off state by comparing the voltage value with a power-off reference threshold value;

and the power-down control unit is used for periodically acquiring the voltage value, comparing the voltage value with the high level value, and controlling the complex programmable logic device to send a power-down signal to the voltage regulator if the voltage value is lower than the high level value.

6. The system of claim 5, wherein the voltage acquisition unit comprises:

and the voltage acquisition module is used for acquiring the voltage value of the PCIE power supply interface in real time by the BMC chip through the intermediate access point of the divider resistor connected with the PCIE power supply interface.

7. The system of claim 5, wherein the status confirmation unit comprises:

the reference setting module is used for presetting a power-off reference threshold;

and the state determination module is used for determining that the PCIE power supply interface is in a power-off state if the voltage value of the PCIE power supply interface is lower than a power-off reference threshold value.

8. The system of claim 5, wherein the power down control unit comprises:

the standard cache module is used for acquiring a high-level value identified by the complex programmable logic device and caching the high-level value to the local BMC;

the polling acquisition module is used for acquiring the voltage value of the PCIE power supply interface once every 100 ms;

and the signal issuing module is used for sending a low-level signal to the complex programmable logic device if the voltage value is lower than the high-level value and lower than the high-level value, and the low-level signal triggers the complex programmable logic device to send an issuing signal to the voltage regulator.

9. A terminal, comprising:

a processor;

a memory for storing instructions for execution by the processor;

wherein the processor is configured to perform the method of any one of claims 1-4.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-4.

Technical Field

The invention relates to the technical field of servers, in particular to a method, a system, a terminal and a storage medium for controlling power-off of a server decoding card.

Background

With the continuous development of multimedia cloud playing technology, the requirements of users on the audio and video playing quality are higher and higher. Especially in the server field, this requirement is more critical. When the audio and video file is played, the audio and video hard decoding chip plays a very important role, the audio and video hard decoding chip is independent of the main control CPU, the audio and video decoding work is independently completed through a special IC chip, for example, the decompression of the audio and video of VCD/DVD and the compression of the audio and video, and the independent audio and video hard decoding chip is basically adopted.

Usually, the decoding chip is designed on the PCIE card, and the user may select the decoding chip and the PCIE card with different configurations according to the requirement. Since the configuration of the decoding chips is gradually improved, the power consumption and the number of the decoding chips are also increased, which makes the power supply of the PCIE board particularly critical. Under normal conditions, the server can design a PCIE daughter card, and power supply from the mainboard to the PCIE card is realized through a golden finger. If the board card does not support hot plug, the front end of the board card will not design an EFUSE (electrical programming fuse), at this time, the CPLD can only determine whether to push subsequent electricity by detecting the P12V _ PCIE from the end of the main board, and if the P12V _ PCIE outputs a high level, the normal power-on sequence is performed. If P12V _ PCIE outputs a low level, then the normal power down sequence is performed.

Since there are inevitably many capacitors on the decoding card, the discharging of P12V _ PCIE is slow in the power-down process, and the control strategy of the CPLD is to determine whether to execute the normal power-down sequence by detecting the voltage value of P12V _ PCIE. If the P12V _ PCIE discharges too slowly, the CPLD may be misjudged, so that the CPLD still executes a control strategy for normal POWER-on in the POWER-off state, and problems such as nonmonotonous signals of output of the post-stage VR, POWER GOOD, and the like may occur, thereby affecting the reliability of the system.

Disclosure of Invention

In view of the above defects in the prior art, the present invention provides a method, a system, a terminal and a storage medium for controlling power-down of a server decoding card, so as to solve the technical problem that erroneous judgment may occur in the power-down process of the server.

In a first aspect, the present invention provides a method for controlling power down of a server decoding card, including:

the method comprises the steps that a BMC chip collects a voltage value of a PCIE power supply interface at a main board end;

comparing the voltage value with a power-down reference threshold value to confirm that the PCIE power supply interface is in a power-down state;

and regularly acquiring the voltage value, comparing the voltage value with a high level value, and controlling the complex programmable logic device to send a lower electric signal to the voltage regulator if the voltage value is lower than the high level value.

Further, the voltage value of mainboard end PCIE power supply interface is gathered to the BMC chip, includes:

the BMC chip collects the voltage value of the PCIE power supply interface in real time through a voltage dividing resistor middle access point connected with the PCIE power supply interface.

Further, by comparing the voltage value with a power-down reference threshold value, it is determined that the PCIE power supply interface is in a power-down state, including:

presetting a power-off reference threshold;

and if the voltage value of the PCIE power supply interface is lower than the power-down reference threshold value, judging that the PCIE power supply interface is in a power-down state.

Further, the step of periodically collecting the voltage value, comparing the voltage value with a high level value, and if the voltage value is lower than the high level value, controlling the complex programmable logic device to send a down-going electrical signal to the voltage regulator includes:

collecting a high-level value determined by a complex programmable logic device and caching the high-level value to the local BMC;

collecting the voltage value of a PCIE power supply interface every 100 ms;

and if the voltage value is lower than the high level value and lower than the high level value, sending a low level signal to the complex programmable logic device, and triggering the complex programmable logic device to send a down electric signal to the voltage regulator by the low level signal.

In a second aspect, the present invention provides a server decoding card power-down control system, including:

the voltage acquisition unit is used for acquiring a voltage value of a PCIE power supply interface at the mainboard end by the BMC chip;

the state confirmation unit is used for confirming that the PCIE power supply interface is in a power-off state by comparing the voltage value with a power-off reference threshold value;

and the power-down control unit is used for periodically acquiring the voltage value, comparing the voltage value with the high level value, and controlling the complex programmable logic device to send a power-down signal to the voltage regulator if the voltage value is lower than the high level value.

Further, the voltage acquisition unit includes:

and the voltage acquisition module is used for acquiring the voltage value of the PCIE power supply interface in real time by the BMC chip through the intermediate access point of the divider resistor connected with the PCIE power supply interface.

Further, the state confirmation unit includes:

the reference setting module is used for presetting a power-off reference threshold;

and the state determination module is used for determining that the PCIE power supply interface is in a power-off state if the voltage value of the PCIE power supply interface is lower than a power-off reference threshold value.

Further, the power-off control unit includes:

the standard cache module is used for acquiring a high-level value identified by the complex programmable logic device and caching the high-level value to the local BMC;

the polling acquisition module is used for acquiring the voltage value of the PCIE power supply interface once every 100 ms;

and the signal issuing module is used for sending a low-level signal to the complex programmable logic device if the voltage value is lower than the high-level value and lower than the high-level value, and the low-level signal triggers the complex programmable logic device to send an issuing signal to the voltage regulator.

In a third aspect, a terminal is provided, including:

a processor, a memory, wherein,

the memory is used for storing a computer program which,

the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.

In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.

The beneficial effect of the invention is that,

according to the power-off control method for the server decoder card, the voltage value of a PCIE power supply interface at the mainboard end is monitored by using the BMC, the power-on and power-off states of the server are judged, the power-off signal is sent to the complex programmable logic device in time when the power-off state is achieved, the voltage change of the P12V _ PCIE can be monitored in real time, the real-time voltage change state of the P12V _ PCIE can be detected in real time according to an internal control strategy, the power-off state or the normal power-on state of the system is judged at the moment, the current working state of the system can be accurately judged by the CPLD through adding a reliable voltage detection and control strategy, the problem that the CPLD still outputs an EN signal due to slow system discharge in the power-off process of the system is solved, the abnormal working state of a rear-stage VR power supply is avoided, and the reliability of the system is improved.

The server decoder card power-off control system provided by the invention monitors the voltage value of the PCIE power supply interface at the end of the main board through the voltage acquisition unit to realize the judgment of the power-on and power-off states of the server by the state confirmation unit, and the power-off control unit sends power-off signals to the complex programmable logic device in time when in the power-off state, the voltage change of the P12V _ PCIE can be monitored in real time, and the real-time voltage change state of the P12V _ PCIE can be detected in real time according to an internal control strategy to judge whether the system is in a power-off state or a normal power-on state at the moment, by adding reliable voltage detection and control strategies, the CPLD can accurately judge the current working state of the system, therefore, the problem that the CPLD still outputs the EN signal due to slow discharge of the system in the power-off process of the system is avoided, the abnormal working state of the rear-stage VR power supply is avoided, and the reliability of the system is improved.

The terminal provided by the invention executes the power-off control method of the server decoder card, realizes the judgment of the power-on and power-off states of the server by monitoring the voltage value of the PCIE power supply interface at the mainboard end by using the BMC, sends a power-off signal to the complex programmable logic device in time when the power-off state is in the power-off state, can monitor the voltage change of the P12V _ PCIE in real time, and can detect the real-time voltage change state of the P12V _ PCIE in real time according to an internal control strategy to judge whether the system is in the power-off state or the normal power-on state at the moment.

The storage medium of the invention stores the program for executing the power-off control method of the server decoding card, the voltage value of the PCIE power supply interface at the mainboard end is monitored by the BMC, the power-on and power-off state of the server is judged, a power-off signal is sent to the complex programmable logic device in time when the power-on state is started, the voltage change of the P12V _ PCIE can be monitored in real time, and the real-time voltage change state of the P12V _ PCIE can be detected in real time according to an internal control strategy to judge whether the system is in a power-off state or a normal power-on state at the moment, by adding reliable voltage detection and control strategies, the CPLD can accurately judge the current working state of the system, therefore, the problem that the CPLD still outputs the EN signal due to slow discharge of the system in the power-off process of the system is avoided, the abnormal working state of the rear-stage VR power supply is avoided, and the reliability of the system is improved.

In addition, the invention has reliable design principle, simple structure and very wide application prospect.

Drawings

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.

Fig. 2 is a schematic and schematic diagram of a method of one embodiment of the present invention.

FIG. 3 is another schematic flow diagram of a method of one embodiment of the invention.

FIG. 4 is a schematic block diagram of a system of one embodiment of the present invention.

Fig. 5 is a schematic structural diagram of a terminal according to an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The following explains key terms appearing in the present invention.

A P12V _ PCIE board-side PCIE power supply interface;

the BMC chip executes a server remote Management controller, and is called a Baseboard Management controller in English. The BMC belongs to a part of IPMI, and the IPMI is used for remotely managing a physical server, such as remote startup, shutdown, mounting of an iso image installation system and the like.

There are three common implementations of video and audio coding and decoding: the first one is to adopt a dedicated audio chip to collect and process the voice signal, and the audio codec algorithm is integrated inside the hardware, such as an MP3 codec chip, a speech synthesis analysis chip, and the like. The advantage of using this scheme is that the processing speed is high, the design period is short; the defects are that the limitation is large, the flexibility is not good, and the system upgrading is difficult to carry out. The second scheme is that an A/D acquisition card and a computer are used to form a hardware platform, and the audio encoding and decoding algorithm is realized by software on the computer. The advantages of using this solution are low price, flexible development and easy system upgrade; the defects are that the processing speed is slow and the development difficulty is large. The third scheme is to use a high-precision and high-speed A/D acquisition chip to complete the acquisition of voice signals, use a programmable chip with strong data processing capability to realize an algorithm for processing the voice signals, and then use an ARM to control. The scheme has the advantages that the system has strong upgrading capability, can be compatible with various audio compression formats and even future audio compression formats, and has lower system cost; the disadvantage is that the development difficulty is large, and designers need to transplant the decoding algorithm of the audio into the corresponding ARM chip.

A PCIE card is a network card having a PCIE interface, and is used as an expansion port in a motherboard-level connection. Specifically, PCIe-based expansion cards can be inserted into PCIe slots in device motherboards such as hosts, servers, and network switches. The computer motherboard has a dedicated PCIe slot corresponding to the PCIe card, and generally, the width of the slot is equal to or even wider than the width of the card.

The CPLD adopts programming technologies such as CMOS EPROM, EEPROM, flash memory, SRAM and the like, thereby forming a programmable logic device with high density, high speed and low power consumption. The CPLD is mainly composed of a logic block, a programmable interconnection channel and an I/O block, and a user can generate a specific circuit structure according to needs to complete certain functions. Because the CPLD adopts metal wires with fixed length to interconnect each logic block, the designed logic circuit has time predictability, and the defect of incomplete time sequence prediction of a sectional type interconnection structure is avoided. At present, the application of the method is deeply applied to the aspects of networks, instruments and meters, automotive electronics, numerical control machines, aerospace measurement and control equipment and the like.

FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution subject in fig. 1 may be a server decoding card power-off control system.

As shown in fig. 1, the method includes:

step 110, the BMC chip acquires a voltage value of a PCIE power supply interface at the main board end;

step 120, comparing the voltage value with a power-off reference threshold value to confirm that the PCIE power supply interface is in a power-off state;

and step 130, periodically collecting the voltage value, comparing the voltage value with a high level value, and controlling the complex programmable logic device to send a down electric signal to the voltage regulator if the voltage value is lower than the high level value.

In order to facilitate understanding of the present invention, the power-off control method for the server decoding card provided by the present invention is further described below by using the principle of the power-off control method for the server decoding card of the present invention and combining with the process of controlling the power-off of the server decoding card in the embodiment.

Referring to fig. 2, in this embodiment, a BMC chip is added between the PCIE power supply interface and the CPLD at the motherboard end, that is, an input pin of the BMC chip is connected to a middle access point of a voltage dividing resistor of the PCIE power supply interface, the voltage dividing resistor is two series resistors, a series branch is grounded, and a middle line of the two series resistors is provided with a middle access point. The two series resistors have equal resistance values. An output pin of the BMC chip is connected with the CPLD, and an output end of the CPLD is connected with the voltage regulator VR.

A BMC chip is added to add a new level of detection and control, the BMC chip judges whether the system is in a power-off state or a normal power supply state by monitoring the voltage value of P12V _ PCIE in real time, and outputs PG1 to the CPLD according to an internal control strategy and a calculation result, so that an EN signal is output to normally drive a VR power supply of a rear level.

Specifically, as shown in fig. 3, the power-down control method of the server decoding card includes:

s1, the BMC chip collects the voltage value of the PCIE power supply interface at the main board end.

The BMC chip collects the voltage value of the PCIE power supply interface in real time through a voltage dividing resistor middle access point connected with the PCIE power supply interface.

The BMC chip acquires the voltage value of the PCIE power supply interface in real time through the divider resistor.

And S2, comparing the voltage value with a power-down reference threshold value to confirm that the PCIE power supply interface is in a power-down state.

Presetting a power-off reference threshold; and if the voltage value of the PCIE power supply interface is lower than the power-down reference threshold value, judging that the PCIE power supply interface is in a power-down state.

Specifically, the voltage value of the PCIE power supply interface of the server in the normal power-on state is monitored in advance, the fluctuation condition of the voltage value is counted, and the power-off reference threshold is set according to the voltage value and the fluctuation condition in the normal power-on state. If the output voltage of the PCIE power supply interface (P12V _ PCIE) is detected to be smaller than the power-down reference threshold value, the system judges that the power-down sequence is entered at the moment.

And S3, periodically collecting the voltage value, comparing the voltage value with a high level value, and controlling the complex programmable logic device to send a down electric signal to the voltage regulator if the voltage value is lower than the high level value.

Collecting a high-level value determined by a complex programmable logic device and caching the high-level value to the local BMC; collecting the voltage value of a PCIE power supply interface every 100 ms; and if the voltage value is lower than the high level value and lower than the high level value, sending a low level signal to the complex programmable logic device, and triggering the complex programmable logic device to send a down electric signal to the voltage regulator by the low level signal.

After the system is judged to enter a power-off sequence, the output voltage is detected in real time every 100ms, if the voltage of the group of P12V _ PCIE is detected to be still higher than the high level considered by the CPLD, the P12V _ PCIE is not directly judged to be the high level at the moment, and after the time delay of 100ms, the level state of the P12V _ PCIE is detected again until the voltage value of the P12V _ PCIE is detected to be lower than the high level considered by the CPLD. At this time, the BMC outputs a PG1 signal of a low level, so as to control the CPLD to output the low level, and then execute a normal power-down sequence, thereby avoiding the power-down false triggering phenomenon of the CPLD.

The specific control strategy is as follows:

if the output voltage of the P12V _ PCIE is detected to be less than 10V (the normal value is 12V), the system determines that the power-down sequence may be entered, and then delays the power-down sequence by 100ms, and detects the voltage value of the P12V _ PCIE again, and if the output voltage is detected to be less than 9V, the system is considered to be still in the power-down process, and delays the power-down sequence by 100ms again.

If the detected voltage is less than 8V, the system is judged to be powered off, the BMC outputs a PG1 signal of a lower order mark, and the CPLD pulls down the EN after receiving the signal, so that the system is powered off.

The power supply state of the P12V _ PCIE can be determined only by detecting the output voltage of the preceding stage MOS in the CPLD in the prior art, and due to the existence of the capacitor on the board, the electric discharge speed of the P12V _ PCIE is slow, so that whether the voltage at this time is in a normal power supply state or in a power-off state cannot be accurately determined and distinguished, and therefore, the problem that the CPLD still outputs high-level EN to the rear stage VR power supply after the power-off of the system is likely to occur, so that the signal abnormality of the rear stage VR is caused, and the reliability of the system is affected.

After improvement, the BMC chip is added in this embodiment, so that the system can monitor the voltage change of the P12V _ PCIE in real time, and can detect the voltage real-time change state of the P12V _ PCIE in real time according to an internal control policy to determine whether the system is in a power-off state or a normal power-on state at this time, thereby avoiding a malfunction of the CPLD and increasing the reliability of the system.

Specifically, the execution method of the present embodiment is as follows:

1) a voltage is divided to the BMC chip through two voltage dividing resistors R5 and R6;

2) a BMC chip is additionally arranged, and the current power-off state or the normal power supply state of the system is judged in real time by detecting the PG signal divided by the resistor in real time;

3) the BMC outputs a PG1 signal to the CPLD through internal control strategy analysis and calculation, and the CPLD executes the next action of the system by taking the signal as a reference;

4) and if the BMC judges that the system is in a power-down state at the moment, the PG1 outputs a low-level state, the CPLD sequentially outputs an EN signal with low level, the rear-stage VR powers down, and the system powers down. Otherwise, the power supply state is normal.

In the power-off control method for the server decoder card, the voltage value of the PCIE power supply interface at the motherboard end is monitored by using the BMC, so that the power-on and power-off states of the server are determined, a power-off signal is sent to the complex programmable logic device in time in the power-off state, the voltage change of the P12V _ PCIE can be monitored in real time, and the real-time voltage change state of the P12V _ PCIE can be detected in real time according to an internal control strategy to determine whether the system is in the power-off state or the normal power-on state at the time.

As shown in fig. 4, the system 400 includes:

the voltage acquisition unit 410 is used for acquiring a voltage value of a PCIE power supply interface at the mainboard end by the BMC chip;

a state confirmation unit 420, configured to confirm that the PCIE power supply interface is in a power-off state by comparing the voltage value with a power-off reference threshold;

and the power-down control unit 430 is configured to periodically acquire the voltage value, compare the voltage value with a high level value, and control the complex programmable logic device to send a power-down signal to the voltage regulator if the voltage value is lower than the high level value.

Optionally, as an embodiment of the present invention, the voltage acquisition unit includes:

and the voltage acquisition module is used for acquiring the voltage value of the PCIE power supply interface in real time by the BMC chip through the intermediate access point of the divider resistor connected with the PCIE power supply interface.

Optionally, as an embodiment of the present invention, the state confirmation unit includes:

the reference setting module is used for presetting a power-off reference threshold;

and the state determination module is used for determining that the PCIE power supply interface is in a power-off state if the voltage value of the PCIE power supply interface is lower than a power-off reference threshold value.

Optionally, as an embodiment of the present invention, the power-off control unit includes:

the standard cache module is used for acquiring a high-level value identified by the complex programmable logic device and caching the high-level value to the local BMC;

the polling acquisition module is used for acquiring the voltage value of the PCIE power supply interface once every 100 ms;

and the signal issuing module is used for sending a low-level signal to the complex programmable logic device if the voltage value is lower than the high-level value and lower than the high-level value, and the low-level signal triggers the complex programmable logic device to send an issuing signal to the voltage regulator.

Fig. 5 is a schematic structural diagram of a terminal 500 according to an embodiment of the present invention, where the terminal 500 may be used to execute a server decoder card power-down control method according to the embodiment of the present invention.

Among them, the terminal 500 may include: a processor 510, a memory 520, and a communication unit 530. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.

The memory 520 may be used for storing instructions executed by the processor 510, and the memory 520 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 520, when executed by processor 510, enable terminal 500 to perform some or all of the steps in the method embodiments described below.

The processor 510 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 520 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, processor 510 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.

A communication unit 530 for establishing a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.

The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).

Therefore, the voltage value of the PCIE power supply interface at the mainboard end is monitored by using the BMC, the power-on and power-off states of the server are judged, the power-off signal is sent to the complex programmable logic device in time in the power-off state, the voltage change of the P12V _ PCIE can be monitored in real time, the real-time voltage change state of the P12V _ PCIE can be detected in real time according to an internal control strategy to judge whether the system is in the power-off state or the normal power-on state at the moment, and the CPLD can accurately judge the current working state of the system by adding a reliable voltage detection and control strategy, so that the problem that the CPLD still outputs an EN signal due to slow system discharge in the power-off process of the system is avoided, the abnormal working state of a rear-stage VR power supply is avoided, and the reliability of the system is improved. For technical effects that can be achieved by the present embodiment, reference may be made to the above description, and details are not described herein again.

Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.

The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.

In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.