阅读说明：本技术 一种低压带隙基准电压产生电路 (Low-voltage band-gap reference voltage generating circuit ) 是由 宋文星 万海军 李健平 于 2021-09-17 设计创作，主要内容包括：本发明公开了一种低压带隙基准电压产生电路,属于半导体芯片的设计技术领域,该电路包括I-(PTAT)产生器、I-(PTAT)电流镜和I-(CTAT)产生器；所述I-(PTAT)产生器,包括三极管Q1、三极管Q2、电阻R1、PMOS管M1和M2,用于产生I-(PTAT)；所述I-(PTAT)电流镜,连接到所述I-(PTAT)产生器上,包括PMOS管M1、M2、M3及M4,用于对PTAT电流进行偏置,生成偏置电流；本发明,以简洁的方式分别产生PTAT和CTAT电流,然后产生与带隙电压成比例的基准电压；而且,整个电路适合于低电源电压下工作,不需要误差放大器和频率补偿,大大简化了芯片设计,也减少了面积和功耗,同时,本发明也提出针对该带隙基准参考电压的两种校正方案,校正后的参考电压精度在-40℃～125℃温度范围内分别达到±0.4％和±0.2％。(The invention discloses a low-voltage band-gap reference voltage generating circuit, which belongs to the technical field of semiconductor chip design and comprises a first circuit I PTAT Generator, I PTAT Current mirror and I CTAT A generator; said I PTAT The generator comprises a transistor Q1, a transistor Q2, a resistor R1, and PMOS transistors M1 and M2 for generating I PTAT (ii) a Said I PTAT A current mirror connected to the I PTAT The generator comprises PMOS tubes M1, M2, M3 and M4 and is used for biasing the PTAT current and generating a bias current; in the invention, PTAT and CTAT currents are respectively generated in a simple manner, and then reference voltages proportional to band gap voltages are generated; moreover, the whole circuit is suitable for working under low power supply voltage, an error amplifier and frequency compensation are not needed, chip design is greatly simplified, area and power consumption are reduced, meanwhile, the invention also provides two correction schemes aiming at the band gap reference voltage, and the accuracy of the corrected reference voltage respectively reaches +/-0.4 percent and +/-0.2 percent within the temperature range of-40 ℃ to 125 ℃.)

1. A low-voltage bandgap reference voltage generation circuit is characterized by comprising I_PTATGenerator, I_PTATCurrent mirror and I_CTATA generator;

said I_PTATThe generator comprises a transistor Q1, a transistor Q2, a resistor R1, and PMOS transistors M1 and M2 for generating I_PTAT；

Wherein, the voltage difference between the two ends of the resistor R1/the voltage difference between the triodes Q1 and Q2 is delta V_beThe size ratio of the triodes Q2 and Q1 is N, and the currents flowing through Q2 and Q1 are the same neglecting base currents;

said I_PTATA current mirror connected to the I_PTATThe generator comprises PMOS tubes M1, M2, M3 and M4 and is used for biasing the PTAT current and generating a bias current;

said I_CTATA generator connected to I_PTATThe current mirror comprises PMOS tubes M4 and M6, an NMOS tube M5, a triode Q3 and a resistor R2 for generating I_CTAT。

2. The low voltage bandgap reference voltage generating circuit as claimed in claim 1, whereinCharacterized in that the V is_beThe voltage drop between the base (base) and the emitter (emitter) of the triode has negative temperature coefficient, and the voltage difference between the two ends of the resistor R1/the voltage difference between the transistors Q1 and Q2 is delta V_beHas a positive temperature coefficient.

3. A low voltage bandgap reference voltage generating circuit as claimed in claim 1 or 2, wherein the voltage difference across the resistor R1 is:

where k is Boltzmann's constant, q is the charge value constant of electrons, T is the absolute temperature, in (N) is the natural logarithm of N, kT/q is about 26mV at room temperature, and V_beIs the voltage drop between the base (base) and the emitter (emitter) of the triode;

at this time, the current proportional to the absolute temperature is:

the current, which is inversely proportional to absolute temperature, is:

let

The band gap current of the basically eliminated temperature coefficient after superposition is obtained as follows:

finally, the reference voltage V generated by the circuit_REFAnd band gap voltage V_aGIn proportion:

4. the circuit of claim 1, wherein the NMOS transistor M5 is a natural threshold NMOS transistor, and the PMOS transistors M6 and M7 are low threshold PMOS transistors.

Technical Field

The invention belongs to the technical field of semiconductor chip design, and particularly relates to a low-voltage band-gap reference voltage generating circuit.

Background

With the development and progress of semiconductor chip technology and the continuous widening of applications, high-performance and low-cost design technology becomes more and more important. The bandgap reference voltage is the most basic and important chip module. The reference voltage generated by it has high stability and accuracy. As shown in fig. 1, high precision, low noise bandgap voltages or reference voltages proportional thereto are essential for chips and modules such as high precision analog-to-digital and digital-to-analog converters, voltage detection, power management, etc.

The conventional bandgap reference voltage generator suitable for low power supply voltage, as shown in fig. 2, basically needs an Error Amplifier (EA) to implement feedback control. The input offset of the amplifier, and the problems of noise amplification, low bandwidth, frequency compensation and the like of the feedback loop have the defects and shortcomings of the existing chip design method. In addition, the circuit does not generate a positive temperature coefficient (PTAT) and a negative temperature coefficient (CTAT: complementary to absolute temperature) of the current output.

Disclosure of Invention

The invention aims to provide a low-voltage bandgap reference voltage generating circuit, which respectively generates PTAT current and CTAT current in a simple mode and then generates reference voltage proportional to bandgap voltage; moreover, the whole circuit is suitable for working under low power supply voltage, an error amplifier and frequency compensation are not needed, the chip design is greatly simplified, the area and the power consumption are reduced, and the problems in the background technology can be solved.

In order to achieve the purpose, the invention provides the following technical scheme: a low voltage bandgap reference voltage generating circuit comprises I_PTATGenerator, I_PTATCurrent mirror and I_CTATA generator;

said I_PTATThe generator comprises a transistor Q1, a transistor Q2, a resistor R1, and PMOS transistors M1 and M2 for generating I_PTAT；

Wherein, the voltage difference between the two ends of the resistor R1/the voltage difference between the triodes Q1 and Q2 is delta V_beThe size ratio of the triodes Q2 and Q1 is N, and the currents flowing through Q2 and Q1 are the same neglecting base currents;

said I_PTATA current mirror connected to the I_PTATThe generator comprises PMOS tubes M1, M2, M3 and M4 and is used for biasing the PTAT current and generating a bias current;

said I_CTATA generator connected to I_PTATThe current mirror comprises PMOS tubes M4 and M6, an NMOS tube M5, a triode Q3 and a resistor R2 for generating I_CTAT。

Preferably, said V_beThe voltage drop between the base (base) and the emitter (emitter) of the triode has negative temperature coefficient, and the voltage difference between the two ends of the resistor R1/the voltage difference between the transistors Q1 and Q2 is delta V_beHas a positive temperature coefficient.

Preferably, the voltage difference across the resistor R1 is:

where k is Boltzmann's constant, q is the charge value constant of electrons, T is the absolute temperature, in (N) is the natural logarithm of N, kT/q is about 26mV at room temperature, and V_beIs the voltage drop between the base (base) and the emitter (emitter) of the triode;

at this time, the current proportional to the absolute temperature is:

the current, which is inversely proportional to absolute temperature, is:

let

The band gap current of the basically eliminated temperature coefficient after superposition is obtained as follows:

finally, the reference voltage V generated by the circuit_REFAnd band gap voltage V_BGIn proportion:

preferably, the NMOS transistor M5 adopts a natural threshold NMOS transistor, and the PMOS transistors M6 and M7 adopt low threshold PMOS transistors.

Compared with the prior art, the invention has the beneficial effects that:

(1) the invention simplifies the design of the band-gap reference voltage circuit under the low power supply voltage, and omits a feedback loop amplifier and frequency compensation thereof.

(2) The invention eliminates the problem of input offset voltage of the feedback amplifier.

(3) The present invention eliminates the problems of additional noise and noise amplification of the feedback amplifier.

(4) The invention provides a correction method for minimizing temperature drift of band gap reference voltage.

(5) The circuit of the invention has the convenience of outputting PTAT and CTAT currents.

(6) The invention improves the performance and reliability of the chip and also reduces the area and power consumption.

Drawings

FIG. 1 is a schematic diagram of a bandgap reference voltage applied to a chip;

FIG. 2 is a conventional low voltage bandgap reference voltage generating circuit;

FIG. 3 is a low voltage bandgap reference voltage generating circuit of the present invention;

FIG. 4 is a simulation of the low bandgap reference voltage of the present invention in a typical process;

FIG. 5 is a simulation result of the present invention with no correction of the reference voltage at the corner of the extreme process;

FIG. 6 shows that the reference voltage of the present invention corrects only R in extreme process corners₃The simulation result of (2);

FIG. 7 is the present inventionThe inventive reference voltage corrects R simultaneously at extreme process corners₂And R₃And (4) obtaining a simulation result.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in FIG. 3, a low voltage bandgap reference voltage generating circuit comprises I_PTATGenerator, I_PTATCurrent mirror and I_CTATA generator;

said I_PTATThe generator comprises a transistor Q1, a transistor Q2, a resistor R1, and PMOS transistors M1 and M2 for generating I_PTAT；

Wherein, the voltage difference between the two ends of the resistor R1/the voltage difference between the triodes Q1 and Q2 is delta V_beThe size ratio of the triodes Q2 and Q1 is N, and the currents flowing through Q2 and Q1 are the same neglecting base currents;

said I_PTATA current mirror connected to the I_PTATThe generator comprises PMOS tubes M1, M2, M3 and M4 and is used for biasing the PTAT current and generating a bias current;

said I_CTATA generator connected to I_PTATThe current mirror comprises PMOS tubes M4 and M6, an NMOS tube M5, a triode Q3 and a resistor R2 for generating I_CTAT。

As an embodiment of the present invention, the V_beThe voltage drop between the base (base) and the emitter (emitter) of the triode has negative temperature coefficient, and the voltage difference between the two ends of the resistor R1/the voltage difference between the transistors Q1 and Q2 is delta V_beHas a positive temperature coefficient.

As an embodiment of the present invention, the voltage difference across the resistor R1 is:

where k is Boltzmann's constant, q is the charge value constant of electrons, T is the absolute temperature, in (N) is the natural logarithm of N, kT/q is about 26mV at room temperature, and V_beIs the voltage drop between the base (base) and the emitter (emitter) of the triode;

at this time, the current proportional to the absolute temperature is:

the current, which is inversely proportional to absolute temperature, is:

let

The band gap current of the basically eliminated temperature coefficient after superposition is obtained as follows:

finally, the reference voltage V generated by the circuit_REFAnd band gap voltage V_BGIn proportion:

in an embodiment of the present invention, the NMOS transistor M5 adopts a natural threshold NMOS transistor, and the PMOS transistors M6 and M7 adopt low threshold PMOS transistors.

As shown in FIG. 4, the output reference voltage is nominally about 614mV with a voltage variation of less than 0.6mV, i.e., + -0.05%, over the temperature range from-40 deg.C to 125 deg.C.

As shown in fig. 5, the temperature drift range of the output reference voltage is less than 23mV, about ± 2%, taking into account the process variations of the transistor and the resistor.

As shown in fig. 6, the output reference voltage Vref reaches the nominal value 614mV at the normal temperature of 30 ℃, by calibrating the resistance value of the resistor R2. After correction, the temperature drift range of the output reference voltage is about 4.8mV, which is less than + -0.4%.

As shown in FIG. 7, the output reference voltage Vref reaches the nominal value 6114mV by calibrating the resistors R2 and R3 simultaneously and proportionally at the normal temperature of 30 ℃. After correction, the temperature drift range of the output reference voltage is about 2.3mV, which is less than +/-0.2%.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.