阅读说明：本技术 基于cache的缓存数据处理方法、存储介质及芯片 (Cache data processing method based on cache, storage medium and chip ) 是由 谢林庭 卢知伯 于 2021-09-15 设计创作，主要内容包括：本发明涉及数据缓存技术领域,公开了一种基于cache的缓存数据处理方法、存储介质及芯片。基于cache的缓存数据处理方法包括：遍历第一缓存队列的第一地址查询表；根据每个缓存行的内存块起始地址,确定满足内存地址连续条件的缓存行作为候选缓存行；根据各个候选缓存行的缓存长度及预设长度阈值,处理每个候选缓存行的缓存数据。本实施例能够根据内存块起始地址的连续性,结合各个候选缓存行的缓存长度处理每个候选缓存行的缓存数据,避免在淘汰缓存数据时容易将地址连续的多个缓存行的缓存数据予以淘汰,避免在下次访问时,花费较多加载时间加载已被刷掉的地址连续的多个缓存行的缓存数据。(The invention relates to the technical field of data caching, and discloses a cache data processing method based on cache, a storage medium and a chip. The cache data processing method based on the cache comprises the following steps: traversing a first address lookup table of a first cache queue; determining cache lines meeting the memory address continuous condition as candidate cache lines according to the memory block starting address of each cache line; and processing the cache data of each candidate cache line according to the cache length of each candidate cache line and a preset length threshold value. According to the embodiment, the cache data of each candidate cache line can be processed by combining the cache length of each candidate cache line according to the continuity of the starting address of the memory block, so that the cache data of a plurality of cache lines with continuous addresses are prevented from being easily eliminated when the cache data are eliminated, and the cache data of a plurality of cache lines with continuous addresses, which are eliminated and spent in a large loading time, are prevented from being loaded when the cache data are accessed next time.)

1. A cache data processing method based on cache is characterized by comprising the following steps:

traversing a first address lookup table of a first cache queue, where the first cache queue includes a plurality of cache lines, a cache length of each cache line is variable, each cache line is used to store cache data of a mapped memory, and the first address lookup table includes a memory block start address corresponding to each cache line;

determining cache lines meeting the memory address continuous condition as candidate cache lines according to the memory block starting address of each cache line;

and processing the cache data of each candidate cache line according to the cache length of each candidate cache line and a preset length threshold value.

2. The method of claim 1, wherein the processing the cache data of each candidate cache line according to the cache length of each candidate cache line and a preset length threshold comprises:

accumulating the cache length of each candidate cache line according to the address continuous sequence from the initial candidate cache line to obtain the length result after each accumulation;

judging whether the length result after each accumulation is larger than a preset length threshold value or not;

if so, taking the candidate cache lines participating in the accumulation process as target cache lines, and processing the cache data of each target cache line;

if not, continuing to accumulate the cache length of each candidate cache line according to the address continuous sequence.

3. The method of claim 2, wherein the processing the cache data of each of the target cache lines comprises:

acquiring a second cache queue and a second address lookup table;

and transferring all the cache data of the target cache line to a reference cache line in the second cache queue, and updating the first address lookup table and the second address lookup table.

4. The method of claim 3, further comprising, prior to traversing the first address lookup table of the first buffer queue:

determining a target cache queue according to the cache length of the cache data to be loaded and a preset length threshold;

and mapping the cache data to be loaded to the corresponding cache line of the target cache queue.

5. The method of claim 4, wherein the determining the target cache queue according to the cache length of the cache data to be loaded and a preset length threshold comprises:

judging whether the cache length of the cache data to be loaded is greater than or equal to a preset length threshold value or not;

if so, selecting the second cache queue as a target cache queue;

and if not, selecting the first cache queue as a target cache queue.

6. The method according to any of claims 1 to 5, wherein the determining, according to the memory block start address of each cache line, a cache line satisfying a memory address continuity condition as a candidate cache line comprises:

calculating the end address of the memory block of each cache line according to the initial address and the cache length of the memory block of each cache line;

determining one cache line and another candidate cache line of the cache line if the starting address of the memory block of the cache line in the first cache queue and the ending address of the memory block of the other cache line are consecutive.

7. The method of any of claims 1 to 5, further comprising, prior to traversing the first address lookup table of the first buffer queue:

detecting whether the first cache queue loads new cache data or not;

if yes, entering a step of traversing a first address lookup table of a first cache queue;

if not, the cache state of the first cache queue is kept.

8. A storage medium storing computer-executable instructions for causing an electronic device to perform the cache-based cache data processing method according to any one of claims 1 to 7.

9. A chip, comprising:

at least one processor; and the number of the first and second groups,

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the cache-based cache data processing method of any one of claims 1 to 7.

10. A cache controller, comprising:

the cache storage module comprises at least one cache queue, each cache queue comprises a plurality of cache lines, the cache length of each cache line is variable, and each cache line is used for storing cache data of a mapping memory;

the cache storage module is used for storing cache data, and the cache storage module is used for storing cache data in a cache line;

the cache line loading module is used for accessing the memory according to the loading command;

and the cache line updating module is used for updating the data of the corresponding cache line of the cache storage module under the control of the cache line loading module.

Technical Field

The invention relates to the technical field of data caching, in particular to a cache-based cache data processing method, a storage medium and a chip.

Background

The cache technology is one of the core technologies in modern processor design, and effectively solves the matching problem between the processing speed and the memory speed. The cache is used for caching cache data (cache data) of the memory. When the main device accesses the memory, the main device can be transferred to the cache for access, and cache data is captured from the cache. When the storage space of the cache is full, the loaded cache data in the cache needs to be eliminated.

The prior art can provide various cache elimination algorithms to eliminate cache data, but the existing cache elimination algorithms determine the cache condition of a single cache line in isolation and determine whether to eliminate the cache data of the single cache line according to the cache condition of the single cache line, wherein the cache condition comprises access frequency, access times or write-in time of specified duration and the like.

However, in an application scenario where the main device has a strong continuity of accessing the memory, the existing cache elimination algorithm is easy to eliminate the cache data of one or more memories with continuous start addresses of the memory blocks, however, when the cache controller loads the cache data of a plurality of memories with continuous start addresses of the memory blocks from the memories to the cache, a lot of loading time is needed. When the cache data are eliminated and the main equipment needs to use the cache data next time, the cache controller needs a long time to load the cache data from the memory into the cache, so that the data access efficiency is reduced.

Disclosure of Invention

An object of the embodiments of the present invention is to provide a cache data processing method, a storage medium, and a chip based on cache, which are used to solve the above technical defects in the prior art.

In a first aspect, an embodiment of the present invention provides a cache-based cache data processing method, including:

traversing a first address lookup table of a first cache queue, where the first cache queue includes a plurality of cache lines, a cache length of each cache line is variable, each cache line is used to store cache data of a mapped memory, and the first address lookup table includes a memory block start address corresponding to each cache line;

determining cache lines meeting the memory address continuous condition as candidate cache lines according to the memory block starting address of each cache line;

and processing the cache data of each candidate cache line according to the cache length of each candidate cache line and a preset length threshold value.

Optionally, the processing the cache data of each candidate cache line according to the cache length of each candidate cache line and a preset length threshold includes:

accumulating the cache length of each candidate cache line according to the address continuous sequence from the initial candidate cache line to obtain the length result after each accumulation;

judging whether the length result after each accumulation is larger than a preset length threshold value or not;

if so, taking the candidate cache lines participating in the accumulation process as target cache lines, and processing the cache data of each target cache line;

if not, continuing to accumulate the cache length of each candidate cache line according to the address continuous sequence.

Optionally, the processing the cache data of each target cache line includes:

acquiring a second cache queue and a second address lookup table;

and transferring all the cache data of the target cache line to a reference cache line in the second cache queue, and updating the first address lookup table and the second address lookup table.

Optionally, before traversing the first address lookup table of the first cache queue, the method further comprises:

determining a target cache queue according to the cache length of the cache data to be loaded and a preset length threshold;

and mapping the cache data to be loaded to the corresponding cache line of the target cache queue.

Optionally, the determining the target cache queue according to the cache length of the cache data to be loaded and a preset length threshold includes:

judging whether the cache length of the cache data to be loaded is greater than or equal to a preset length threshold value or not;

if so, selecting the second cache queue as a target cache queue;

and if not, selecting the first cache queue as a target cache queue.

Optionally, the determining, according to the memory block start address of each cache line, a cache line that meets a memory address continuity condition as a candidate cache line includes:

calculating the end address of the memory block of each cache line according to the initial address and the cache length of the memory block of each cache line;

determining one cache line and another candidate cache line of the cache line if the starting address of the memory block of the cache line in the first cache queue and the ending address of the memory block of the other cache line are consecutive.

Optionally, before traversing the first address lookup table of the first buffer queue, the method further includes:

detecting whether the first cache queue loads new cache data or not;

if yes, entering a step of traversing a first address lookup table of a first cache queue;

if not, the cache state of the first cache queue is kept.

In a second aspect, an embodiment of the present invention provides a storage medium, where the storage medium stores computer-executable instructions, and the computer-executable instructions are configured to enable an electronic device to execute the cache-based cache data processing method described above.

In a third aspect, an embodiment of the present invention provides a chip, including:

at least one processor; and the number of the first and second groups,

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the cache-based cache data processing method described above.

In a fourth aspect, an embodiment of the present invention provides a cache controller, including:

the cache storage module comprises at least one cache queue, each cache queue comprises a plurality of cache lines, the cache length of each cache line is variable, and each cache line is used for storing cache data of a mapping memory;

the cache storage module is used for storing cache data, and the cache storage module is used for storing cache data in a cache line;

the cache line loading module is used for accessing the memory according to the loading command;

and the cache line updating module is used for updating the data of the corresponding cache line of the cache storage module under the control of the cache line loading module.

In the cache data processing method based on the cache provided in the embodiment of the present invention, a first address lookup table of a first cache queue is traversed, the first cache queue includes a plurality of cache lines, a cache length of each cache line is variable, each cache line is used for storing cache data of a mapped memory, the first address lookup table includes a memory block start address corresponding to each cache line, a cache line meeting an address continuity condition is determined as a candidate cache line according to the memory block start address of each cache line, and the cache data of each candidate cache line is processed according to the cache length of each candidate cache line and a preset length threshold. According to the embodiment, the cache data of each candidate cache line can be processed by combining the cache length of each candidate cache line according to the continuity of the starting address of the memory block, so that the cache data of a plurality of cache lines with continuous addresses are prevented from being easily eliminated when the cache data are eliminated, and the cache data of a plurality of cache lines with continuous addresses, which are eliminated and spent in a large loading time, are prevented from being loaded when the cache data are accessed next time.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a schematic structural diagram of a cache system according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a cache system according to another embodiment of the present invention;

fig. 3 is a first schematic diagram of mapping a memory to a first buffer queue and a second buffer queue according to an embodiment of the present invention;

fig. 4 is a schematic flow chart of a cache data processing method according to an embodiment of the present invention;

FIG. 5a is a schematic flow chart of S42 shown in FIG. 4;

FIG. 5b is a schematic flow chart of S43 shown in FIG. 4;

FIG. 5c is a schematic diagram of the process of S433 shown in FIG. 5 b;

fig. 6 is a second schematic diagram of mapping a memory to a first buffer queue and a second buffer queue according to an embodiment of the present invention;

fig. 7a is a schematic flowchart of a cache-based cache data processing method according to another embodiment of the present invention;

fig. 7b is a schematic flowchart of a cache-based cache data processing method according to yet another embodiment of the present invention;

fig. 8a is a schematic diagram illustrating data transfer between a first buffer queue and a second buffer queue according to an embodiment of the present invention;

fig. 8b is a schematic diagram illustrating data transfer among a first buffer queue, a second buffer queue, and a third buffer queue according to an embodiment of the present invention;

fig. 8c is a schematic diagram of data transfer among the first buffer queue, the second buffer queue, the third buffer queue, and the fourth buffer queue according to the embodiment of the present invention;

fig. 9 is a schematic circuit diagram of a chip according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that, if not conflicted, the various features of the embodiments of the invention may be combined with each other within the scope of protection of the invention. Additionally, while functional block divisions are performed in apparatus schematics, with logical sequences shown in flowcharts, in some cases, steps shown or described may be performed in sequences other than block divisions in apparatus or flowcharts. The terms "first", "second", "third", and the like used in the present invention do not limit data and execution order, but distinguish the same items or similar items having substantially the same function and action.

Referring to fig. 1, the cache system 100 includes a main device 11, a cache controller 12, and a memory 13, where the cache controller 12 is electrically connected to the main device 11 and the memory 13, respectively.

The host device 11 executes the software program and needs to fetch the cached data from the memory 13. When the main device 11 accesses the memory 13, the access to the cache controller 12 is transferred, if the storage address of the corresponding cache line in the cache controller 12 is consistent with the access address of the main device 11 to the memory 13, the cache controller 12 hits, the main device 11 can directly fetch the cache data from the cache line, and if the storage address is not consistent with the access address of the main device 11 to the memory 13, the cache controller 12 does not hit, so that the cache controller 12 sends an access request to the memory 13, and loads the cache data with the same size as the cache line length from the memory 13 to the cache controller 12, so that the main device 11 can fetch the cache data from the cache controller 12.

In some embodiments, the host device 11 may be any suitable type of device, such as an electronic device such as a headset or camera module. It is understood that, referring to fig. 2, the number of the master devices 11 may be multiple, and multiple master devices 11 may access the memory 13 simultaneously.

In some embodiments, with continued reference to fig. 1, the cache controller 12 includes a cache storage module 121, a hit determining module 122, a cache line loading module 123, and a cache line updating module 124.

The cache storage module 121 includes at least one cache queue and an address lookup table corresponding to each cache queue, where each cache queue includes a plurality of cache lines (cachelines), and the address lookup table is used for the hit determining module 122 to perform address determination so as to hit a corresponding cache line, where each cache line is used to store cache data of the mapped memory, and the cache data is memory data of a corresponding memory block in the mapped memory 13.

The address lookup tables of different buffer queues may be constructed in corresponding data structure forms, and in some embodiments, the buffer queues include a first buffer queue, and the address lookup table includes a first address lookup table, and the first buffer queue includes a plurality of buffer lines, where the buffer length of each buffer line in the first buffer queue may be the same or different.

The first address lookup table includes a memory block start address, a cache start address, and valid bit data, where the memory may be divided into a plurality of memory blocks with different byte lengths, the memory block start address is a first memory address of a memory block mapped to a cache line in the memory, the cache start address is a first cache address of a cache queue after the memory block is mapped to the cache line, and the valid bit data includes at least one valid bit, each valid bit is used to indicate validity of cache data of a corresponding cache line, where each valid bit is used to indicate validity of one byte of cache data, when the valid bit is 0, the cache data of the corresponding byte is valid, and when the valid bit is 1, the cache data of the corresponding byte is invalid.

Referring to fig. 3, in order to map the corresponding memory data of the memory 13 to the first cache queue 31, the memory 13 may be divided into a plurality of memory blocks, and the corresponding memory blocks may be mapped to the first cache queue 31, for example, the memory corresponding to the memory addresses 0-29 may be referred to as a memory block a0, which has a data length of 30 bytes. The memory corresponding to the memory addresses 300-419 can be regarded as the memory block a1, and the data length is 120 bytes. The memory corresponding to the memory addresses 800-819 can be regarded as the memory block a2, and the data length is 20 bytes. The memory corresponding to the memory addresses 820 and 879 can be regarded as the memory block a3, and the data length thereof is 60 bytes. The memory corresponding to the memory address 880-1019 can be regarded as the memory block a4, and the data length is 140 bytes. The memory corresponding to the memory address 1200 and 1249 can be regarded as the memory block a5, and the data length thereof is 50 bytes.

It is to be understood that some memory data in the memory 13 shown in fig. 3 is not mapped into the cache queue, and for the sake of intuitive expression, a memory block in the memory 13, to which some memory data is not mapped, is set to be empty.

As shown in fig. 3, in the first address lookup table 32, the buffer length of the 0 th cache line of the first cache queue 31 is 120 bytes, the buffer length of the 1 st cache line of the first cache queue 31 is 30 bytes, the buffer length of the 2 nd cache line of the first cache queue 31 is 20 bytes, the buffer length of the 3 rd cache line of the first cache queue 31 is 60 bytes, the buffer length of the 4 th cache line of the first cache queue 31 is 140 bytes, and the buffer length of the 5 th cache line of the first cache queue 31 is 50 bytes, so the buffer lengths of the cache lines in the first cache queue may be different.

As shown in fig. 3, the cache data of the memory block a1 is mapped to the 0 th cache line of the first cache queue 31, and the first memory address of the memory block a1 is "300", so the memory address "300" is the memory block start address of the memory block a 1. Similarly, the cache data of the memory block a0 is mapped to the 1 st cache line, and the first memory address of the memory block a0 is "0", so that the memory address "0" is the starting address of the memory block a0, and so on.

As shown in fig. 3, after the memory block a1 is mapped to the 0 th cache line of the first cache queue 31, its first cache address in the first cache queue 31 is "0". After the memory block a0 is mapped to the 1 st cache line of the first cache queue 31, its first cache address in the first cache queue 31 is "120". Similarly, the first cache address of the memory block a2 in the first cache queue 31 is "150" after mapping to the 2 nd cache line in the first cache queue 31.

As shown in fig. 3, the cache length of the 0 th cache line of the first cache queue 31 is 120 bytes, and the cache data with the cache length of 120 bytes in the 0 th cache line is valid, so that the valid bit data is 1200, where each valid bit in the valid bit data is used to indicate the validity of one byte of cache data, and normally, when the valid bit is "0", this byte of cache data is valid, and 1200 s indicate that the cache data with the cache length of 120 bytes in the 0 th cache line is valid.

In some embodiments, the buffer queue further includes a second buffer queue, the address lookup table further includes a second address lookup table, the second buffer queue includes a plurality of buffer lines, wherein the second buffer queue is configured to store buffer data having a buffer length greater than a preset length threshold, and the buffer lengths of the buffer lines in the second buffer queue may be the same or different. The second address lookup table includes a memory block start address, a cache start address, and valid bit data, and the meanings of the memory block start address, the cache start address, and the valid bit data are the same as those described above and are not described herein again.

With continued reference to fig. 3, in order to map the corresponding memory data of the memory 13 to the second cache queue 33, the memory 13 may be divided into a plurality of memory blocks, and the corresponding memory blocks may be mapped to the second cache queue 33, for example, the memory corresponding to the memory addresses 30-239 may be referred to as a memory block B0, which has a data length of 210 bytes. The memory corresponding to the memory addresses 420 and 719 can be regarded as the memory block B1, and the data length thereof is 300 bytes. The memory corresponding to the memory address 1250-1649 can be regarded as the memory block B2, and the data length thereof is 400 bytes.

As shown in fig. 3, in the second address lookup table 34, the buffer length of the 0 th cache line of the second buffer queue 33 is 210 bytes, the buffer length of the 1 st cache line of the second buffer queue 33 is 400 bytes, and the buffer length of the 2 nd cache line of the second buffer queue 33 is 300 bytes, so that the buffer lengths of the cache lines in the second buffer queue may be different.

As shown in fig. 3, the cache data of the memory block B0 is mapped to the 0 th cache line of the second cache queue 33, and the first memory address of the memory block B0 is "30", so the memory address "30" is the memory block start address of the memory block B0. Similarly, the cache data of the memory block B2 is mapped to the 1 st cache line of the second cache queue 33, and the first memory address of the memory block B2 is "1250", so the memory address "1250" is the memory block start address of the memory block B2. The cache data of the memory block B1 is mapped to the 2 nd cache line of the second cache queue 33, and the first memory address of the memory block B1 is "420", so the memory address "420" is the memory block start address of the memory block B1.

As shown in fig. 3, after the memory block B0 is mapped to the 0 th cache line of the second cache queue 33, the first cache address of the second cache queue 33 is "1000". After the memory block B2 is mapped to the 1 st cache line in the second cache queue 33, its first cache address in the second cache queue 33 is "1210". Similarly, the first cache address of the memory block B1 in the second cache queue 33 is "1610" after mapping to the 2 nd cache line in the second cache queue 33.

As can be seen from fig. 3, the first buffer queue 31 can store buffer data with a buffer length less than or equal to 200, and the second buffer queue 33 can store buffer data with a buffer length greater than 200.

In some embodiments, the first buffer queue 31, the first address lookup table 32, the second buffer queue 33, and the second address lookup table 34 all adopt a circular loop management manner.

In some embodiments, the cache storage module 121 is a register set or a RAM memory.

The hit determining module 122 is configured to traverse the address lookup table according to the access request to determine whether the cache line is hit, control the cache storage module 121 to interact with the host device 11 if the cache line is hit, and generate a load command if the cache line is not hit.

In some embodiments, the access request carries a minimum memory request address and requested memory size information, and the hit determining module 122 traverses the address lookup table according to the minimum memory request address and the requested memory size information to determine whether the cache line is hit.

Specifically, the step of traversing the address lookup table according to the minimum memory request address and the requested memory size information to determine whether the cache line is hit includes: adding the minimum memory request address and the requested memory size information to obtain a maximum memory request address, judging whether the minimum memory request address and the maximum memory request address fall in a target address mapping range at the same time, wherein the address mapping range is defined by a memory block starting address and a memory block ending address of a cache line, the target address mapping range is one of address mapping ranges corresponding to all the cache lines, and the memory block ending address is equal to the memory block starting address + the cache length-1. If the minimum memory request address and the maximum memory request address both fall within the address mapping range, the hit determining module 122 hits the cache line corresponding to the target address mapping range. If the minimum memory request address or the maximum memory request address does not fall within the address mapping range, the hit determining module 122 misses the cache line of the address lookup table.

For example, the access request carries the minimum memory request address "300" and the requested memory size information "30 byte", and the hit determining module 122 adds the minimum memory request address "300" and the requested memory size information "30 byte" to obtain the maximum memory request address "330". The first cache queue 31 has a0 th cache line with a memory block starting address of "300" and a memory block ending address of "419", so the target address mapping range is [300,419 ]. Since the minimum memory request address "300" and the maximum memory request address "330" both fall within the target address mapping range [300,419], the hit determination module 122 hits in the 0 th cache line of the first cache queue 31.

For another example, the access request carries the minimum memory request address "250" and the requested memory size information "30 byte", and the hit determining module 122 adds the minimum memory request address "250" and the requested memory size information "30 byte" to obtain the maximum memory request address "280". Since the maximum memory request address "280" does not fall within any address mapping range, the hit determining module 122 misses any cache line in the first cache queue 31 or the second cache queue 33.

For another example, the access request carries the minimum memory request address "280" and the requested memory size information "30 byte", and the hit determining module 122 adds the minimum memory request address "280" and the requested memory size information "30 byte" to obtain the maximum memory request address "310". Although the maximum memory request address "310" falls within the address mapping range [300,419], the minimum memory request address "280" does not fall within the address mapping range [300,419], and therefore the hit determining module 122 misses the cache line in either the first cache queue 31 or the second cache queue 33.

For another example, the access request carries the minimum memory request address "430" and the requested memory size information "60 byte", and the hit determining module 122 adds the minimum memory request address "430" and the requested memory size information "60 byte" to obtain the maximum memory request address "490". Although the maximum memory request address "490" does not fall within the address mapping range corresponding to any cache line in the first cache queue 31, the maximum memory request address "490" may fall within the address mapping range [420,719] in the second cache queue 33, and the minimum memory request address "30" also falls within the address mapping range [420,719], so that the hit determining module 122 hits in the 2 nd cache line of the second cache queue 33.

If the hit determining module 122 hits the corresponding cache line in the first cache queue 31 or the second cache queue 33, according to a cache start address, a memory block start address, and requested memory size information corresponding to the hit cache line, a minimum cache request address and a maximum cache request address are calculated, and according to the minimum cache request address and the maximum cache request address, the master device is controlled to read data from the cache storage module, where the minimum cache request address is the minimum memory request address-the memory block start address + the cache start address, and the maximum cache request address is the minimum cache request address + the requested memory size information.

For example, the hit determining module 122 hits in the 0 th cache line of the first cache queue 31, wherein the access request carries the minimum memory request address "300" and the requested memory size information "30 byte". The hit determining module 122 queries the first address lookup table to obtain that the cache start address of the 0 th cache line of the first cache queue 31 is "0" and the memory block start address is "300", so that the minimum cache request address is 300+0 ═ 0, and the maximum cache request address is 0+30 ═ 30, and therefore the hit determining module 122 controls the host device to read data from the cache storage module according to the minimum cache request address "0" and the maximum cache request address "30".

For another example, the hit determining module 122 hits in the 2 nd cache line of the second cache queue 33, wherein the access request carries the minimum memory request address "430" and the requested memory size information "60 byte". The hit determining module 122 queries the second address lookup table to obtain the cache start address of the 2 nd cache line of the second cache queue 33 as "1610" and the memory block start address as "420", so that the minimum cache request address is 430 and 420+1610 respectively as "1620", and the maximum cache request address is 1620 and 60 respectively as "1680", and thus the hit determining module 122 controls the host device to read data from the cache storage module according to the minimum cache request address "1620" and the maximum cache request address "1680".

If the hit determining module 122 misses any cache line in the first cache queue 31 and the second cache queue 33, the hit determining module 122 transmits a load command to the cache line loading module 123, and the cache line loading module 123 is configured to access the memory 13 according to the load command.

The cache line updating module 124 is configured to perform data updating on the corresponding cache line of the cache storage module 121 under the control of the cache line loading module 123, for example, load the cache data from the memory 13 to the first cache queue 31 or the second cache queue 33, and update the first address lookup table 32 or the second address lookup table 34.

It is understood that the hit determining module 122, the cache line loading module 123 and the cache line updating module 124 may be a chip design circuit with logic operation function and storage function, which is composed of integrated circuit devices.

The embodiment of the invention provides a cache data processing method based on cache. Referring to fig. 4, a cache-based cache data processing method S400 includes:

s41, traversing the first address lookup table of the first buffer queue;

the first cache queue comprises a plurality of cache lines, the cache length of each cache line is variable, each cache line is used for storing cache data of the mapped memory, and the first address lookup table comprises a memory block starting address corresponding to each cache line.

S42, determining cache lines meeting the address continuity condition as candidate cache lines according to the initial address of the memory block of each cache line;

by way of example and not limitation, the address continuity condition being met means that the starting address of the memory block mapped to one memory block in the first cache queue is adjacent to the ending address of the memory block of another memory block. For example, referring to fig. 3, the memory block a2 is mapped to the 2 nd cache line of the first cache queue 31, the memory block start address of the memory block a2 is "800", and the memory block end address is "819". The memory chunk A3 is mapped to the 3 rd cache line of the first cache queue 31, the memory chunk start address of the memory chunk A3 is "820", and the memory chunk end address is "879". The memory block a4 is mapped to the 4 th cache line of the first cache queue 31, the memory block start address of the memory block a4 is "880", and the memory block end address is "1019". The memory block end address "819" of the memory block a2 is consecutive to the memory block start address "820" of the memory block A3, and the memory block end address "879" of the memory block A3 is consecutive to the memory block start address "880" of the memory block a4, so the 2 nd cache line of the first cache queue 31, the 3 rd cache line of the first cache queue 31, and the 4 th cache line of the first cache queue 31 are all candidate cache lines.

And S43, processing the cache data of each candidate cache line according to the cache length of each candidate cache line and a preset length threshold value.

According to the embodiment, the cache data of each candidate cache line can be processed by combining the cache length of each candidate cache line according to the continuity of the starting address of the memory block, so that the cache data of a plurality of cache lines with continuous addresses are prevented from being easily eliminated when the cache data are eliminated, and the cache data of a plurality of cache lines with continuous addresses, which are eliminated and spent in a large loading time, are prevented from being loaded when the cache data are accessed next time.

In some embodiments, referring to fig. 5a, S42 includes:

s421, calculating the end address of the memory block of each cache line according to the start address and the cache length of the memory block of each cache line;

s422, if the starting address of the memory block of one cache line in the first cache queue is consecutive to the ending address of the memory block of another cache line, determining a cache line and another cache line candidate cache line;

s423, if the starting address of the memory block of the first cache line in the first cache queue is not consecutive to the ending address of the memory block of the other cache line, determining that the one cache line and the other cache line are not candidate cache lines.

As described above, the memory block end address is memory block start address + cache length-1, and the hit determining module searches the first address lookup table, where the memory block start address of the 2 nd cache line of the first cache queue 31 is "800", and the cache length is 20, and the memory block end address of the 2 nd cache line of the first cache queue 31 is 800+20-1 — 819. If the starting address of the memory block in the 3 rd cache line of the first cache queue 31 is "820" and the cache length is 60, the ending address of the memory block in the 3 rd cache line of the first cache queue 31 is 820+60-1, 879. If the starting address of the memory block in the 4 th cache line of the first cache queue 31 is "880", and the cache length is 140, the ending address of the memory block in the 4 th cache line of the first cache queue 31 is 880+140-1 is 1019.

Since the memory block end address "819" of the memory block a2 is consecutive to the memory block start address "820" of the memory block A3, and the memory block end address "879" of the memory block A3 is consecutive to the memory block start address "880" of the memory block a4, the 2 nd cache line of the first cache queue 31, the 3 rd cache line of the first cache queue 31, and the 4 th cache line of the first cache queue 31 are all candidate cache lines.

For the 1 st cache line of the first cache queue 31, the memory block start address of the 1 st cache line of the first cache queue 31 is "0", and the cache length is 30, and then the memory block end address of the 1 st cache line of the first cache queue 31 is 0+30-1 or 29. Since the end address "29" of the memory block of the 1 st cache line of the first cache queue 31 and the start address "800" of the memory block of the 2 nd cache line of the first cache queue 31 are not consecutive, the 1 st cache line and the 2 nd cache line of the first cache queue 31 are not candidate cache lines.

In some embodiments, referring to fig. 5b, S43 includes:

s431, accumulating the cache length of each candidate cache line according to the address continuous sequence from the initial candidate cache line to obtain the length result after each accumulation;

s432, judging whether the length result after each accumulation is larger than a preset length threshold value;

s433, if yes, taking the candidate cache lines participating in the accumulation process as target cache lines, and processing the cache data of each target cache line;

and S434, if not, continuously accumulating the cache length of each candidate cache line according to the address continuous sequence.

For example, but not limited to, the starting candidate cache line is a candidate cache line corresponding to the minimum starting address or the maximum starting address of the memory block in each candidate cache line, for example, the starting candidate cache line may be a2 nd cache line of the first cache queue 31, or may be a4 th cache line of the first cache queue 31. The addresses are in a consecutive order of the starting addresses of the memory blocks in a big and small order or in a small and big order, for example, the addresses are in a consecutive order of the starting addresses of the memory blocks "800" - - -the starting addresses of the memory blocks "820" - - -the starting addresses of the memory blocks "880".

When step S431 is executed, for example, in the present embodiment, starting from the 2 nd cache line of the first cache queue 31, according to the address continuous sequence of "800-.

When step S432 is executed, the present embodiment determines whether the length result after the first accumulation is greater than a preset length threshold, where the preset length threshold is defined by a user, for example, the preset length threshold is 200. Since the length result "80" after the first accumulation is smaller than the preset length threshold "200", step S434 is executed, i.e. the cache length of each candidate cache line is continuously accumulated according to the address continuous order.

Then, the present embodiment further accumulates the length "140" of the 4 th cache line of the first cache queue 31 and the length result after the first accumulation to obtain a length result after the second accumulation, where the length result is 80+140 ═ 220.

When step S432 is executed, the present embodiment determines whether the length result after the second accumulation is greater than the preset length threshold. Since the length result "220" after the second accumulation is greater than the preset length threshold "200", step S433 is executed, that is, the candidate cache lines participating in the accumulation process are taken as the target cache lines, and the cache data of each target cache line is processed, wherein the 2 nd cache line of the first cache queue 31, the 3 rd cache line of the first cache queue 31, and the 4 th cache line of the first cache queue 31 all participate in the accumulation process, and therefore the 2 nd cache line of the first cache queue 31, the 3 rd cache line of the first cache queue 31, and the 4 th cache line of the first cache queue 31 are all taken as the target cache lines.

In some embodiments, when processing the cache data of each target cache line, referring to fig. 5c, S433 includes:

s4331, acquiring a second cache queue and a second address lookup table;

s4332, transferring all the cache data of the target cache line to the reference cache line in the second cache queue, and updating the first address lookup table and the second address lookup table.

In some embodiments, when updating the first address lookup table, the present embodiment may set all valid bit data corresponding to the target cache line to be in an invalid state in the first address lookup table, that is, set all valid bit data corresponding to the target cache line to 1, for example, referring to fig. 6, for the 2 nd cache line of the first cache queue 61, the 3 rd cache line of the first cache queue 61 and the 4 th cache line of the first cache queue 61, in the first address lookup table 62, the valid bit data corresponding to the 2 nd cache line of the first cache queue 61 is 20 "1", the valid bit data corresponding to the 3 rd cache line of the first cache queue 61 is 60 "1", and the valid bit data corresponding to the 4 th cache line of the first cache queue 61 is 140 "1".

In some embodiments, when the second address lookup table is updated, this embodiment selects a minimum memory address in all target cache lines as the starting address of the memory block of the reference cache line, calculates the cache starting address of the reference cache line according to the cache starting address and the cache length of a latest cache line in the second address lookup table, where the logic positions of the latest cache line and the reference cache line in the second address lookup table are adjacent, and uses the total cache length of all target cache lines as the cache length of the reference cache line.

Since the cache data of the reference cache line is valid, the present embodiment determines the valid bit data of the reference cache line according to the cache length of the reference cache line.

For example, with continued reference to fig. 6, the minimum memory address in the 2 nd cache line of the first cache queue 61, the 3 rd cache line of the first cache queue 61, and the 4 th cache line of the first cache queue 61 is "800", and thus the starting address of the memory block of the reference cache line S0 is "800". In the second address lookup table 64 of the second buffer queue 63, the second buffer queue 332 nd cache line is adjacent to the reference cache line S0 at the logical location of the second address lookup table, and therefore, the second buffer queue 332 nd cache line is the nearest cache line.

In this embodiment, the cache start address "1610" and the cache length "300" of the 2 nd cache line of the second cache queue 33 are added to obtain the cache start address "1910" of the reference cache line S0.

The present embodiment takes the total cache length of all target cache lines as the cache length of the reference cache line, that is, the cache length of the reference cache line is 20+60+140 or 220.

Since the cache data of the reference cache line is all valid, the valid bit data of the reference cache line is 220, which is used to represent 220 "0".

In summary, referring to fig. 3, if the main device accesses the memory continuously, for example, the main device needs to access the memory block a2, the memory block A3, and the memory block a4 continuously for many times, and then the cache loads the memory block a2, the memory block A3, and the memory block a4 into the first cache queue 31. After a period of time, assuming that the first cache queue 31 deletes the memory block a2, the memory block A3, and the memory block a4 from the first cache queue 31 according to a cache elimination algorithm, when the subsequent master device needs to access the memory block a2, the memory block A3, and the memory block a4 again, the cache needs to spend a long time loading the memory block a2, the memory block A3, and the memory block a4 from the memory, which reduces the data access efficiency in some memory access processes with high continuity.

Referring to fig. 6, in this embodiment, the memory block a2, the memory block A3, and the memory block a4 in the first cache queue are entirely transferred to the same cache line of the second cache queue, on one hand, the first cache queue can receive cache data with a shorter cache length for the access of the host device, and on the other hand, by forwarding the multiple memory blocks with consecutive memory addresses to the second cache queue, the first cache queue can be prevented from adopting a cache elimination algorithm to easily delete the multiple memory blocks with a short cache length and consecutive memory addresses, and the cache data of the multiple cache lines with consecutive addresses that have been flushed away is prevented from being loaded in a longer loading time during the next access, thereby improving the data access efficiency.

In some embodiments, before traversing the first address lookup table of the first cache queue, referring to fig. 7a, the cache-based cache data processing method S400 further includes:

s44, determining a target cache queue according to the cache length of the cache data to be loaded and a preset length threshold;

and S45, mapping the cache data to be loaded to the corresponding cache line of the target cache queue.

In some embodiments, when executing S44, the present embodiment determines whether the cache length of the cache data to be loaded is greater than or equal to a preset length threshold, if so, selects the second cache queue as the target cache queue, and if not, selects the first cache queue as the target cache queue.

For example, the cache length of the cache data to be loaded is 120, the preset length threshold is 200, and since the cache length of the cache data to be loaded is smaller than the preset length threshold, the first cache queue is selected as the target cache queue, and the cache data to be loaded is mapped to the corresponding cache line of the first cache queue. Similarly, assuming that the cache length of the cache data to be loaded is 250, since the cache length of the cache data to be loaded is greater than the preset length threshold, the second cache queue is selected as the target cache queue, and the cache data to be loaded is mapped to the corresponding cache line of the second cache queue subsequently.

In some embodiments, when transferring the cache data of the cache line in the first cache queue to the cache line in the second cache queue, the delayed transfer mode may be better than the immediate transfer mode because: in the instant transfer mode, the cache data of the cache line in the first cache queue is transferred to the cache line in the second cache queue, at this time, the storage space of the corresponding cache line of the first cache queue is vacated, meanwhile, although the second cache queue has one more cache data of the cache line, the second cache queue can also eliminate the data according to a cache elimination strategy, the second cache queue can also eliminate the cache data of the corresponding cache line, from the whole, the first cache queue and the second cache queue reduce one cache data, when the master device accesses the cache, the reduced cache data may be the data that the master device needs to capture, the instant transfer mode can reduce the data hit rate, and the cache space cannot be efficiently utilized.

Therefore, in some embodiments, before traversing the first address lookup table of the first cache queue, referring to fig. 7b, the cache-based cache data processing method S400 further includes:

s46, detecting whether the first buffer queue loads new buffer data, if yes, entering the step S41, S47, if no, keeping the buffer state of the first buffer queue.

By adopting the method, the data hit rate is improved, and the cache space is efficiently utilized.

For example, referring to fig. 8a, since the first buffer queue 81 has the above-mentioned situation, the first buffer queue 81 transfers the corresponding buffer data to the same cache line of the second buffer queue 82, and the first buffer queue 81 also receives the addition of the new buffer data. Also, each of the first and second buffer queues 81 and 82 may select a corresponding buffer elimination algorithm to eliminate data, for example, the buffer elimination algorithm includes LRU algorithm, LFU algorithm, FIFO algorithm, 2Q algorithm (double queues) or MQ algorithm (multi queues).

Referring to fig. 8b, the first and second buffer queues 81 and 82 may transfer the to-be-retired buffer data to the third buffer queue 83, wherein the third buffer queue 83 may select a corresponding buffer retirement algorithm to retire the data.

Referring to fig. 8c, according to the cache length eviction algorithm, the cache data to be evicted in the third cache queue 83 is transferred to the fourth cache queue 84 in the present embodiment. In addition, according to the present embodiment, the cache data of the fourth cache queue 84 is eliminated according to a preset elimination algorithm.

It should be noted that, in the foregoing embodiments, a certain order does not necessarily exist between the foregoing steps, and those skilled in the art can understand, according to the description of the embodiments of the present invention, that in different embodiments, the foregoing steps may have different execution orders, that is, may be executed in parallel, may also be executed interchangeably, and the like.

Referring to fig. 9, fig. 9 is a schematic circuit structure diagram of a chip according to an embodiment of the present invention. As shown in fig. 9, chip 900 includes one or more processors 91 and memory 92. In fig. 9, one processor 91 is taken as an example.

The processor 91 and the memory 92 may be connected by a bus or other means, and fig. 9 illustrates the connection by a bus as an example.

The memory 92, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the cache-based cache data processing method in the embodiment of the present invention. The processor 91 implements the functions of the cache-based cache data processing method provided by the above-described method embodiment by running the nonvolatile software program, instructions, and modules stored in the memory 92.

The memory 92 may include high speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory 92 may optionally include memory located remotely from the processor 91, and such remote memory may be connected to the processor 91 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The program instructions/modules are stored in the memory 92 and, when executed by the one or more processors 91, perform the cache-based cache data processing method in any of the above-described method embodiments.

An embodiment of the present invention further provides a non-volatile computer storage medium, where the computer storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors, for example, one processor 91 in fig. 9, so that the one or more processors may execute the cache-based cache data processing method in any method embodiment described above.

An embodiment of the present invention further provides a computer program product, where the computer program product includes a computer program stored on a non-volatile computer-readable storage medium, and the computer program includes program instructions, and when the program instructions are executed by a chip, the chip is caused to execute any cache-based cache data processing method.

The above-described embodiments of the apparatus or device are merely illustrative, wherein the unit modules described as separate parts may or may not be physically separate, and the parts displayed as module units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a general hardware platform, and certainly can also be implemented by hardware. Based on such understanding, the above technical solutions substantially or contributing to the related art may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.