阅读说明：本技术 使用反馈电路控制rram器件的装置 (Apparatus for controlling RRAM device using feedback circuit ) 是由 胡淼 葛宁 于 2021-08-03 设计创作，主要内容包括：本公开实施例公开了一种在交叉开关电路中使用反馈电路控制RRAM器件的装置。一个示例性装置包括一个RRAM单元用于形成沟道、一个包括漏极端、源极端和栅极端的MOSFET,其中所述MOSFET通过所述漏极端连接至所述RRAM单元；一个TIA,通过源极端连接至MOSFET；一个第一信号发生器,连接至RRAM单元；一个第二信号发生器,通过栅极端连接至MOSFET；一个包括第一输入端、第二输入端和输出端的比较器,其中所述比较器通过第一输入端连接至所述TIA,所述第二输入端连接至一个参考电压源,所述输出端连接至所述第一信号发生器和所述第二信号发生器。从而,使得在RRAM器件中形成沟道的过程更容易控制。(The embodiment of the disclosure discloses a device for controlling an RRAM device by using a feedback circuit in a cross switch circuit. An exemplary apparatus includes a RRAM cell for forming a channel, a MOSFET including a drain terminal, a source terminal, and a gate terminal, wherein the MOSFET is connected to the RRAM cell through the drain terminal; a TIA connected to the MOSFET through a source terminal; a first signal generator connected to the RRAM unit; a second signal generator connected to the MOSFET through the gate terminal; a comparator comprising a first input terminal, a second input terminal and an output terminal, wherein the comparator is connected to the TIA via the first input terminal, the second input terminal is connected to a reference voltage source, and the output terminal is connected to the first signal generator and the second signal generator. Thus, the process of forming the channel in the RRAM device is made easier to control.)

1. An apparatus for controlling a Resistive Random Access Memory (RRAM) device using a feedback circuit, comprising:

an RRAM cell for forming a channel;

a metal oxide semiconductor field effect transistor MOSFET comprising a drain terminal, a source terminal and a gate terminal, wherein said MOSEFT is connected to the RRAM cell via the drain terminal;

a transimpedance amplifier TIA connected to the MOSFET via a source terminal;

a first signal generator connected to the RRAM unit;

a second signal generator connected to the mosfet through the gate terminal;

a comparator comprising a first input terminal, a second input terminal and an output terminal, wherein the comparator is connected to the TIA via the first input terminal, the second input terminal is connected to a reference voltage source, and the output terminal is connected to the first signal generator and the second signal generator.

2. The apparatus of claim 1, wherein the comparator is a voltage comparator.

3. The apparatus of claim 1, wherein the comparator is configured to turn off the first signal generator when a channel is formed.

4. The apparatus of claim 1, wherein the first signal generator comprises a dc ramp signal generator or a pulsed ramp signal generator.

5. The apparatus of claim 1, wherein said second signal generator comprises a dc ramp signal generator.

6. The apparatus of claim 1, wherein the second signal generator is configured to limit current.

7. The apparatus of claim 1, wherein the combination of the TIA and the comparator has a propagation delay of less than 1 nanosecond.

8. The apparatus of claim 1, wherein the combination of the TIA and the comparator are configured to operate to 40 ghz.

9. The apparatus of claim 1, wherein the reference voltage source is configured to provide a reference voltage Vref, the TIA configured to output a TIA output voltage Vo; wherein Vo < Vref when the channel is formed; when the channel is not formed, Vo > Vref.

10. The apparatus of claim 1, wherein the RRAM cell comprises a bottom electrode, a channel-forming layer disposed on the bottom electrode, and a top electrode disposed on the channel-forming layer, wherein the channel-forming layer is configured to form the channel.

11. The device of claim 10, wherein the RRAM cell further comprises a bitline fabricated below a bottom electrode and a wordline fabricated on the top electrode.

12. The device of claim 10, wherein the material of the bottom or top electrode comprises Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN, or combinations thereof, or alloys thereof with other conductive materials.

13. The device of claim 10, wherein the material of the channel forming layer comprises TaOx (where x ≦ 2.5), HfOx (where x ≦ 2.0), TiOx (where x ≦ 2.0), or a combination thereof.

14. The device of claim 10, wherein the channel comprises an oxygen-vacancy conductive filament.

15. The apparatus of claim 10, wherein a material of the channel comprises a tantalum-rich, hafnium-rich, or titanium-rich oxide material.

Technical Field

The present disclosure relates to a feedback circuit, and more particularly, to an apparatus for controlling an RRAM device using a feedback circuit in a crossbar switch circuit.

Background

A conventional crossbar array circuit includes rows of horizontal metal lines and columns of vertical metal lines (or other electrodes) that cross each other and crossbar devices formed at their intersections. Crossbar arrays may be used for non-volatile solid-state memory, signal processing, control systems, high-speed image processing systems, neural network systems, and other applications.

Resistive random access memory cells (RRAMs), which are two-terminal passive devices capable of changing resistance in response to sufficient electrical stimulus, have attracted considerable attention in high-performance non-volatile memory applications. The resistance of the RRAM may be electrically switched between two states, a High Resistance State (HRS) and a Low Resistance State (LRS). The switching event from FIRS to LRS is commonly referred to as "setting" or "turning on" the switch; the handoff event from the LRS to the FIRS is commonly referred to as a "reset" or "shutdown" handoff procedure.

In order to allow the RRAM device to switch between these two resistance states, a formation process may be used. The formation process may form a channel or line in the RRAM device for providing switching characteristics. The forming process may be accomplished by applying a voltage or current to the RRAM device; the forming voltage or current is typically much higher than the read and write voltages.

However, the formation process is still technically challenging due to the need for greater control. If the resulting voltage or current is too high, the RRAM device may turn to an over-conducting state, causing difficulty in the subsequent reset process. Conversely, if the voltage or current developed is too low, the formation process may not be successful.

In addition, since the forming process is a self-accelerating process, over-forming may occur within a few nanoseconds, which presents a challenge to conventional open loop forming methods.

Disclosure of Invention

The embodiment of the disclosure discloses a device for controlling an RRAM device by adopting a feedback circuit in a cross switch circuit.

In some embodiments, an apparatus includes a RRAM cell for forming a channel; a MOSFET including a drain terminal, a source terminal and a gate terminal, wherein the MOSFET is connected to the RRAM cell through the drain terminal; a TIA connected to the MOSFET through a source terminal; a first signal generator connected to the RRAM unit; a second signal generator connected to the mosfet through the gate terminal; a comparator comprising a first input terminal, a second input terminal and an output terminal, wherein the comparator is connected to a Trans-Impedance Amplifier (TIA) via the first input terminal, the second input terminal is connected to a reference voltage source, and the output terminal is connected to the first signal generator and the second signal generator.

In some embodiments, the comparator is a voltage comparator. In some embodiments, the comparator is configured to turn off the first signal generator when the channel is formed.

In some embodiments, the first signal generator comprises a dc ramp signal generator or a pulsed ramp signal generator.

In some embodiments, the second signal generator comprises a dc ramp signal generator. In some embodiments, the second signal generator is configured to act as a current limiter.

In some implementations, the combination of the TIA and the comparator has a propagation delay of less than 1 nanosecond. In some embodiments, the combination of the TIA and the comparator is configured to operate to 40 ghz.

In some embodiments, the reference voltage source is configured to provide a reference voltage Vref, the TIA is configured to output a TIA output voltage Vo; wherein Vo < Vref when the channel is formed; when the channel is not formed, Vo > Vref.

In some embodiments, the RRAM cell further comprises a bottom electrode, a channel-forming layer formed on the bottom electrode, and a top electrode formed on the channel-forming layer, wherein the channel-forming layer is configured to form the channel.

In some embodiments, the RRAM cell further includes a bitline fabricated on the bottom electrode and a wordline fabricated on the top electrode.

In some embodiments, the material of the bottom or top electrode is made of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN, or combinations thereof, or alloys of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN and one or more other conductive materials.

In some embodiments, the material of the channel-forming layer is made of one of TaOx (where x.ltoreq.2.5), HfOx (where x.ltoreq.2.0), TiOx (where x.ltoreq.2.0), or a combination thereof.

In some embodiments, the channel comprises an oxygen-vacancy conducting filament. In some embodiments, the channel is made of tantalum-rich, hafnium-rich, or titanium-rich oxide.

Drawings

FIG. 1A is a block diagram of an exemplary cross-switch array circuit in an embodiment of the present disclosure;

FIG. 1B is a block diagram of a partial enlarged view of the exemplary cross circuit shown in FIG. 1A in an embodiment of the present disclosure;

FIG. 2 is a block diagram of a RRAM cell in an embodiment of the disclosure;

FIG. 3 is a block diagram of a feedback circuit in an embodiment of the disclosure;

FIG. 4 is a timing diagram of various characteristics of an exemplary feedback circuit in an embodiment of the present disclosure;

the embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. Like reference numerals refer to corresponding parts throughout the drawings.

Detailed Description

The disclosed embodiments disclose an apparatus for controlling RRAM devices using one or more feedback circuits in a crossbar switch circuit. The device provided by the embodiment of the disclosure has the following beneficial effects:

first, the apparatus disclosed by the embodiments of the present disclosure provides better control for RRAM channel formation. The formation of conventional RRAM channels provides inadequate control: the formation energy may be too strong or too weak to form the channel well. The feedback circuit described in this disclosure makes the formation voltage or current easier to control and can automatically stop the formation process after the channel is formed. The disclosed technology reduces or eliminates overload formation and can be fully automated.

Second, the techniques described in this disclosure involve the use of transimpedance amplifiers and comparators, the combination of which is capable of reducing the delay to less than 1 nanosecond (or increasing the frequency to 40 GHz), while still maintaining low power consumption. The RRAM crossbar array circuit may also be trained faster and more accurate, thereby greatly enhancing the performance of the RRAM crossbar array circuit. Improved performance crossbar array circuits are ideal for circuit implementations for real-time image recognition, neural computation, memory computation, or other related applications.

Finally, a ramp signal generator using the disclosed technology may provide a scalable solution, thereby reducing the loss and area size of the RRAM crossbar circuit. The ramp signal generator may be shared by several word lines and select lines, and the presence of a TIA at the output of each bit line may be used to provide additional functions, such as a feedback function.

Fig. 1A is a block diagram 1000 of an exemplary cross switch array circuit 100 in some embodiments of the present disclosure. As shown in fig. 1A, the crossbar array circuit 100 includes a first word line 101, a first bit line 102, and a crossbar circuit device 103.

Fig. 1B is a block diagram 1500 of a partially enlarged view of the crossbar circuit device 103 shown in fig. 1A in some embodiments of the present disclosure. As shown in fig. 1B, the crossbar circuit device 103 is located between and connected to the first word line 101 and the first bit line 102 in the crossbar array circuit 100 shown in fig. 1A.

In some embodiments, the crossbar circuit device 103 includes one RRAM cell 1031. The RRAM cell 1031 may be a transistor-memory resistor (1T1R) stack, a selector-memory resistor (1S1R0), or a memory resistor.

Fig. 2 is a block diagram 2000 of an RRAM cell 200 according to some embodiments of the present disclosure.

As shown in fig. 2, the RRAM cell 200 includes a substrate 201, a bit line 203 formed on the substrate 201, a bottom electrode 205 formed on the bit line 203, a channel formation layer 207 formed on the bottom electrode 205, a top electrode 209 formed on the channel formation layer 207, and a word line 211 formed on the top electrode 209.

In some embodiments, the substrate 301 is made of silicon (Si), silicon nitride (SiN), silicon dioxide (SiO2), aluminum oxide (Al2O3), or a combination thereof. In some embodiments, the bit line 201 is made of Ag, Al, Au, Cu, Fe, Ni, Mo, Pt, Pb, Ti, TiN, Sn, W, Zn, or a combination thereof, or an alloy of Ag, Al, Au, Cu, Fe, Ni, Mo, Pt, Pb, Ti, TiN, Sn, W, Zn and one or more other conductive materials.

In some embodiments, the word line 211 is made of Ag, Al, Au, Cu, Fe, Ni, Mo, Pt, Pb, Ti, TiN, Sn, W, Zn, or a combination thereof, or an alloy of Ag, Al, Au, Cu, Fe, Ni, Mo, Pt, Pb, Ti, TiN, Sn, W, Zn and one or more other conductive materials.

In some embodiments, the material of the bottom electrode 205 and/or the top electrode 209 comprises Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN, or combinations thereof, or alloys with other conductive materials.

In some embodiments, the bottom electrode 205 is made of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN, combinations thereof, or alloys of Pt, Ti, TiN, Pd, Ir, W, Ta, H, Nb, V, TaN, NbN and one or more other conductive materials.

In some embodiments, the top electrode 209 is made of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN, combinations thereof, or alloys of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN and one or more other conductive materials.

In some embodiments, the channel-forming layer is made of TaOx (where x.ltoreq.2.5), HfOx (where x.ltoreq.2.0), TiOx (where x.ltoreq.2.0), or a combination thereof.

In some embodiments, the channel-forming layer 207 is configured to form a filament or channel 2071 within the channel-forming layer 207 in response to a forming voltage or current applied to the RRAM cell 2000.

The channel or filament 2071 may comprise an oxygen vacancy conducting filament. In some embodiments, the channels or the filaments 2071 are made of tantalum-rich, hafnium-rich, or titanium oxide-rich materials.

As mentioned above, the channel resistance may be kept too low when the forming voltage or current is too high. Conversely, if the formation voltage or current is too low, the formation may not be successful and the channel may not be formed properly.

Furthermore, in an optimal formation process, the formation voltage or current should be stopped immediately after the channel formation (e.g., within nanoseconds or even picoseconds). The conventional formation process is often not optimal: since the formation process is a self-accelerating process. For example, a high voltage or current may cause a stronger formation process, and the formation process may make the device more conductive; more conductive devices in turn produce more current, thereby exacerbating the formation behavior.

Thus, if the formation process does not stop immediately after the channel formation, an overload formation may result. A technique of stopping the formation process immediately after the detection of the channel formation is advantageous.

Fig. 3 is an exemplary block diagram 3000 of the feedback circuit 300 in some embodiments of the present disclosure.

As shown in fig. 3, the feedback circuit 300 includes an RRAM cell 301, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) 305 connected to the RRAM cell 301, a transimpedance amplifier (TIA)303 connected to the MOSFET305, a comparator 311 connected to the TIA303, a first signal generator 307 connected to the RRAM cell 301, and a second signal generator 309 connected to the MOSFET 305.

In some embodiments, the MOSFET305 includes a first terminal 3051 coupled to the second signal generator 309, a second terminal 3053 coupled to the RRAM cell 301, and a third terminal 3055 coupled to the TIA 303.

In some embodiments, the first terminal 3051 is a gate terminal; the second end 3053 is a drain end; and the third terminal 3055 is a source terminal. Said first end 3051 is connected to said second signal generator 309; the second end 3053 is connected to the RRAM cell 301; and the third terminal 3055 is connected to the TIA 303.

In some embodiments, the first signal generator 307 is configured to provide a voltage Vset to the RRAM cell 301; in some embodiments, the second signal generator 309 is configured to provide a voltage Vgate to the first terminal 3051 of the MOSFET 305; the first signal generator 306 may comprise a dc ramp signal generator or a pulsed ramp signal generator.

The second signal generator 309 may comprise a ramp signal generator. The second signal generator and the MOSFET305 may be implemented as a current limiter. This architecture can gradually increase the maximum current through the MOSFET305 in saturation mode.

In some implementations, the TIA303, the comparator 311, or both have a propagation delay of less than 1 nanosecond. The combination of the TIA303 and the comparator 311 has a propagation delay of less than 1 nanosecond in some embodiments.

The comparator 311 includes a first input terminal 3114, a second input terminal 3115 and an output terminal 3111 thereof. The output 3111 is connected to the first signal generator 307 and the second signal generator 309.

In some embodiments, the comparator 311 comprises a voltage comparator. Current comparators have a larger delay and higher power consumption than voltage comparators. The comparator 311 is used to compare the TIA output voltage Vo of the TIA303 with the voltage Vref of the reference voltage source. In some embodiments, the reference voltage Vref may be preset to 1/2 (high Vo + low Vo). If Vo is higher than Vref, the output 3111 will be 1. If Vo is below Vref, output 3111 will be 0. This allows the comparator 311 to turn on and off the first signal generator 307 and the second signal generator 309 simultaneously. Details of the signal processing can be found in fig. 4.

Fig. 4 is a timing diagram 4000 illustrating various characteristics of the feedback circuit 300 in some embodiments of the present disclosure.

As shown in fig. 4, when the first signal generator 307 supplies the boosting signal Vset to the RRAM cell 301, energy (or heat) may gradually accumulate in the RRAM cell 301, resulting in the formation of a channel (or filament) inside the RRAM cell 301. Another boost signal Vgate provided by the second signal generator 309 may be used to limit the current, which increases the maximum current flowing through the RRAM cell 301 and the MOSFET 305.

Vo may be the output voltage of the TIA 303. The current output from the MOSFET305 can be converted into Vo. Vo remains high before the first signal generator 307 starts boosting and the channel is not formed. Once the channel is formed, Vo decreases, resulting in an increase in Vcomp. The comparator 311 then switches its digital output (e.g., from 0 to 1) by turning off the first signal generator 307 and the second signal generator 309. In some embodiments, when the first signal generator 307 is turned off, the boosting voltage Vset is lowered so that the channel formation process can be stopped as needed.

Using the TIA and comparator in these ways may produce a faster response, reducing the delay to below 1 nanosecond. Frequencies up to 40 ghz are achieved using lower power consumption. Since the ramp signal generator can be shared by different word lines and select lines, the feedback circuit 300 can be used for fast array formation testing; the existing TIA (at each bitline output) can also be reused to provide feedback. These techniques allow for better scalability and flexibility of the feedback circuit.

Multiple instances may be provided for a component, operation, or structure described herein as a single instance. Finally, the boundaries between various components, operations and data stores are somewhat arbitrary, and particular operations are illustrated in the context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within the scope of the inventive subject matter. In general, structures and functionality presented as separate components in the exemplary configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements may fall within the scope of the inventive subject matter.

It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first column can be referred to as a second column, and similarly, a second column can be referred to as a first column without changing the meaning of the description, so long as all occurrences of the "first column" are renamed and all occurrences of the "second column" are renamed. The first and second columns are both the s-th column, but they are not the same column.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is also to be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, such as integers, steps, operations, elements, components, and/or groups thereof.

The term "if" as used herein may be interpreted to mean "when" or "at … …" or "in response to a determination" or "according to a determination" or "in response to a detection", the condition precedent being context dependent. Similarly, the phrase "if determined (precedent to a stated condition is true)" or "if (precedent to a stated condition is true)" or "when (a priori to a stated condition is true)" may be interpreted as "above … …". Depending on the context, the conditional prerequisite is true either "determine" or "in response to determine" or "in accordance with detect" or "in response to detect".

The foregoing description includes example systems, methods, techniques, instruction sequences, and computer program products that embody exemplary embodiments. For purposes of explanation, numerous specific details are set forth in order to provide an understanding of various implementations of the inventive subject matter. It will be apparent, however, to one skilled in the art that embodiments of the present subject matter may be practiced without these specific details. In general, well-known instruction instances, protocols, structures, and techniques have not been shown in detail.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles and its practical applications, to thereby enable others skilled in the art to best utilize the embodiments and various embodiments with various modifications as are suited to the particular use contemplated.